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sys/dev/qat/qat_api/firmware/include/icp_qat_hw.h
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****************************************************************************** | ****************************************************************************** | ||||
*/ | */ | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
/* AccelerationEngine */ | /* AccelerationEngine */ | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_AE_0 = 0, /*!< ID of AE0 */ | ICP_QAT_HW_AE_0 = 0, /*!< ID of AE0 */ | ||||
ICP_QAT_HW_AE_1 = 1, /*!< ID of AE1 */ | ICP_QAT_HW_AE_1 = 1, /*!< ID of AE1 */ | ||||
ICP_QAT_HW_AE_2 = 2, /*!< ID of AE2 */ | ICP_QAT_HW_AE_2 = 2, /*!< ID of AE2 */ | ||||
ICP_QAT_HW_AE_3 = 3, /*!< ID of AE3 */ | ICP_QAT_HW_AE_3 = 3, /*!< ID of AE3 */ | ||||
ICP_QAT_HW_AE_4 = 4, /*!< ID of AE4 */ | ICP_QAT_HW_AE_4 = 4, /*!< ID of AE4 */ | ||||
ICP_QAT_HW_AE_5 = 5, /*!< ID of AE5 */ | ICP_QAT_HW_AE_5 = 5, /*!< ID of AE5 */ | ||||
ICP_QAT_HW_AE_6 = 6, /*!< ID of AE6 */ | ICP_QAT_HW_AE_6 = 6, /*!< ID of AE6 */ | ||||
ICP_QAT_HW_AE_7 = 7, /*!< ID of AE7 */ | ICP_QAT_HW_AE_7 = 7, /*!< ID of AE7 */ | ||||
ICP_QAT_HW_AE_8 = 8, /*!< ID of AE8 */ | ICP_QAT_HW_AE_8 = 8, /*!< ID of AE8 */ | ||||
ICP_QAT_HW_AE_9 = 9, /*!< ID of AE9 */ | ICP_QAT_HW_AE_9 = 9, /*!< ID of AE9 */ | ||||
ICP_QAT_HW_AE_10 = 10, /*!< ID of AE10 */ | ICP_QAT_HW_AE_10 = 10, /*!< ID of AE10 */ | ||||
ICP_QAT_HW_AE_11 = 11, /*!< ID of AE11 */ | ICP_QAT_HW_AE_11 = 11, /*!< ID of AE11 */ | ||||
ICP_QAT_HW_AE_12 = 12, /*!< ID of AE12 */ | ICP_QAT_HW_AE_12 = 12, /*!< ID of AE12 */ | ||||
ICP_QAT_HW_AE_13 = 13, /*!< ID of AE13 */ | ICP_QAT_HW_AE_13 = 13, /*!< ID of AE13 */ | ||||
ICP_QAT_HW_AE_14 = 14, /*!< ID of AE14 */ | ICP_QAT_HW_AE_14 = 14, /*!< ID of AE14 */ | ||||
ICP_QAT_HW_AE_15 = 15, /*!< ID of AE15 */ | ICP_QAT_HW_AE_15 = 15, /*!< ID of AE15 */ | ||||
ICP_QAT_HW_AE_DELIMITER = 16 /**< Delimiter type */ | ICP_QAT_HW_AE_DELIMITER = 16 /**< Delimiter type */ | ||||
} icp_qat_hw_ae_id_t; | } icp_qat_hw_ae_id_t; | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
/* QAT */ | /* QAT */ | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_QAT_0 = 0, /*!< ID of QAT0 */ | ICP_QAT_HW_QAT_0 = 0, /*!< ID of QAT0 */ | ||||
ICP_QAT_HW_QAT_1 = 1, /*!< ID of QAT1 */ | ICP_QAT_HW_QAT_1 = 1, /*!< ID of QAT1 */ | ||||
ICP_QAT_HW_QAT_2 = 2, /*!< ID of QAT2 */ | ICP_QAT_HW_QAT_2 = 2, /*!< ID of QAT2 */ | ||||
ICP_QAT_HW_QAT_3 = 3, /*!< ID of QAT3 */ | ICP_QAT_HW_QAT_3 = 3, /*!< ID of QAT3 */ | ||||
ICP_QAT_HW_QAT_4 = 4, /*!< ID of QAT4 */ | ICP_QAT_HW_QAT_4 = 4, /*!< ID of QAT4 */ | ||||
ICP_QAT_HW_QAT_5 = 5, /*!< ID of QAT5 */ | ICP_QAT_HW_QAT_5 = 5, /*!< ID of QAT5 */ | ||||
ICP_QAT_HW_QAT_DELIMITER = 6 /**< Delimiter type */ | ICP_QAT_HW_QAT_DELIMITER = 6 /**< Delimiter type */ | ||||
} icp_qat_hw_qat_id_t; | } icp_qat_hw_qat_id_t; | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
/* AUTH SLICE */ | /* AUTH SLICE */ | ||||
/* ========================================================================= */ | /* ========================================================================= */ | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Supported Authentication Algorithm types | * Supported Authentication Algorithm types | ||||
* @description | * @description | ||||
* Enumeration which is used to define the authenticate algorithms | * Enumeration which is used to define the authenticate algorithms | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_AUTH_ALGO_NULL = 0, /*!< Null hashing */ | ICP_QAT_HW_AUTH_ALGO_NULL = 0, /*!< Null hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, /*!< SHA1 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, /*!< SHA1 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_MD5 = 2, /*!< MD5 hashing */ | ICP_QAT_HW_AUTH_ALGO_MD5 = 2, /*!< MD5 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, /*!< SHA-224 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, /*!< SHA-224 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, /*!< SHA-256 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, /*!< SHA-256 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, /*!< SHA-384 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, /*!< SHA-384 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, /*!< SHA-512 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, /*!< SHA-512 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, /*!< AES-XCBC-MAC hashing */ | ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, /*!< AES-XCBC-MAC hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, /*!< AES-CBC-MAC hashing */ | ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, /*!< AES-CBC-MAC hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, /*!< AES F9 hashing */ | ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, /*!< AES F9 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, /*!< Galois 128 bit hashing */ | ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, /*!< Galois 128 bit hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, /*!< Galois 64 hashing */ | ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, /*!< Galois 64 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, /*!< Kasumi F9 hashing */ | ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, /*!< Kasumi F9 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /*!< UIA2/SNOW_3G F9 hashing */ | ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /*!< UIA2/SNOW_3G F9 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = | ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = | ||||
14, /*!< 128_EIA3/ZUC_3G hashing */ | 14, /*!< 128_EIA3/ZUC_3G hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SM3 = 15, /*!< SM3 hashing */ | ICP_QAT_HW_AUTH_ALGO_SM3 = 15, /*!< SM3 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16, /*!< SHA3-224 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16, /*!< SHA3-224 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, /*!< SHA3-256 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, /*!< SHA3-256 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18, /*!< SHA3-384 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18, /*!< SHA3-384 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, /*!< SHA3-512 hashing */ | ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, /*!< SHA3-512 hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHAKE_128 = 20, /*!< SHAKE-128 hashing */ | ICP_QAT_HW_AUTH_RESERVED_4 = 20, /*!< Reserved */ | ||||
ICP_QAT_HW_AUTH_ALGO_SHAKE_256 = 21, /*!< SHAKE-256 hashing */ | ICP_QAT_HW_AUTH_RESERVED_5 = 21, /*!< Reserved */ | ||||
ICP_QAT_HW_AUTH_ALGO_POLY = 22, /*!< POLY hashing */ | ICP_QAT_HW_AUTH_ALGO_POLY = 22, /*!< POLY hashing */ | ||||
ICP_QAT_HW_AUTH_ALGO_DELIMITER = 23 /**< Delimiter type */ | ICP_QAT_HW_AUTH_ALGO_DELIMITER = 23 /**< Delimiter type */ | ||||
} icp_qat_hw_auth_algo_t; | } icp_qat_hw_auth_algo_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Definition of the supported Authentication modes | * Definition of the supported Authentication modes | ||||
* @description | * @description | ||||
* Enumeration which is used to define the authentication slice modes. | * Enumeration which is used to define the authentication slice modes. | ||||
* The concept of modes is very specific to the QAT implementation. Its | * The concept of modes is very specific to the QAT implementation. Its | ||||
* main use is differentiate how the algorithms are used i.e. mode0 SHA1 | * main use is differentiate how the algorithms are used i.e. mode0 SHA1 | ||||
* will configure the QAT Auth Slice to do plain SHA1 hashing while mode1 | * will configure the QAT Auth Slice to do plain SHA1 hashing while mode1 | ||||
* configures it to do SHA1 HMAC with precomputes and mode2 sets up the | * configures it to do SHA1 HMAC with precomputes and mode2 sets up the | ||||
* slice to do SHA1 HMAC with no precomputes (uses key directly) | * slice to do SHA1 HMAC with no precomputes (uses key directly) | ||||
* | * | ||||
* @Note | * @Note | ||||
* Only some algorithms are valid in some of the modes. If you dont know | * Only some algorithms are valid in some of the modes. If you dont know | ||||
* what you are doing then refer back to the HW documentation | * what you are doing then refer back to the HW documentation | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_AUTH_MODE0 = 0, /*!< QAT Auth Mode0 configuration */ | ICP_QAT_HW_AUTH_MODE0 = 0, /*!< QAT Auth Mode0 configuration */ | ||||
ICP_QAT_HW_AUTH_MODE1 = 1, /*!< QAT Auth Mode1 configuration */ | ICP_QAT_HW_AUTH_MODE1 = 1, /*!< QAT Auth Mode1 configuration */ | ||||
ICP_QAT_HW_AUTH_MODE2 = 2, /*!< QAT AuthMode2 configuration */ | ICP_QAT_HW_AUTH_MODE2 = 2, /*!< QAT AuthMode2 configuration */ | ||||
ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 /**< Delimiter type */ | ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 /**< Delimiter type */ | ||||
} icp_qat_hw_auth_mode_t; | } icp_qat_hw_auth_mode_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Auth configuration structure | * Auth configuration structure | ||||
* | * | ||||
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/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Eight-bit mask used to determine the SHA3 | * Eight-bit mask used to determine the SHA3 | ||||
* flexible programmable padding prefix | * flexible programmable padding prefix | ||||
*/ | */ | ||||
/**< Flag usage - see additional notes @description for | /**< Flag usage - see additional notes @description for | ||||
* ICP_QAT_HW_AUTH_CONFIG_BUILD and | * ICP_QAT_HW_AUTH_CONFIG_BUILD and | ||||
* ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER macros. | * ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER macros. | ||||
*/ | */ | ||||
#define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0 | #define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* This setting enables h/w padding for SHA3. | * This setting enables h/w padding for SHA3. | ||||
*/ | */ | ||||
#define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1 | #define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
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/* ************************************************************************* */ | /* ************************************************************************* */ | ||||
/* ************************************************************************* */ | /* ************************************************************************* */ | ||||
#define QAT_HW_DEFAULT_ALIGNMENT 8 | #define QAT_HW_DEFAULT_ALIGNMENT 8 | ||||
#define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) | #define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) | ||||
/* State1 */ | /* State1 */ | ||||
#define ICP_QAT_HW_NULL_STATE1_SZ 64 | #define ICP_QAT_HW_NULL_STATE1_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for NULL hashing */ | * State1 block size for NULL hashing */ | ||||
#define ICP_QAT_HW_MD5_STATE1_SZ 16 | #define ICP_QAT_HW_MD5_STATE1_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for MD5 */ | * State1 block size for MD5 */ | ||||
#define ICP_QAT_HW_SHA1_STATE1_SZ 20 | #define ICP_QAT_HW_SHA1_STATE1_SZ 20 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the state1 block size for SHA1 - Note that for the QAT HW the state | * Define the state1 block size for SHA1 - Note that for the QAT HW the state | ||||
* is rounded to the nearest 8 byte multiple */ | * is rounded to the nearest 8 byte multiple */ | ||||
#define ICP_QAT_HW_SHA224_STATE1_SZ 32 | #define ICP_QAT_HW_SHA224_STATE1_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA24 */ | * State1 block size for SHA24 */ | ||||
#define ICP_QAT_HW_SHA3_224_STATE1_SZ 32 | #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA3_224 */ | * State1 block size for SHA3_224 */ | ||||
#define ICP_QAT_HW_SHA256_STATE1_SZ 32 | #define ICP_QAT_HW_SHA256_STATE1_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA256 */ | * State1 block size for SHA256 */ | ||||
#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 | #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA3_256 */ | * State1 block size for SHA3_256 */ | ||||
#define ICP_QAT_HW_SHA384_STATE1_SZ 64 | #define ICP_QAT_HW_SHA384_STATE1_SZ 64 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA384 */ | * State1 block size for SHA384 */ | ||||
#define ICP_QAT_HW_SHA3_384_STATE1_SZ 64 | #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA3_384 */ | * State1 block size for SHA3_384 */ | ||||
#define ICP_QAT_HW_SHA512_STATE1_SZ 64 | #define ICP_QAT_HW_SHA512_STATE1_SZ 64 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA512 */ | * State1 block size for SHA512 */ | ||||
#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 | #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for SHA3_512 */ | * State1 block size for SHA3_512 */ | ||||
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/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State1 block size for Galois128 */ | * State1 block size for Galois128 */ | ||||
#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 | #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 | ||||
/**< @ingroup icp_cpm_hw_defs | /**< @ingroup icp_cpm_hw_defs | ||||
* State1 block size for UIA2 */ | * State1 block size for UIA2 */ | ||||
#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 | #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 | ||||
/**< @ingroup icp_cpm_hw_defs | /**< @ingroup icp_cpm_hw_defs | ||||
* State1 block size for EIA3 */ | * State1 block size for EIA3 */ | ||||
#define ICP_QAT_HW_SM3_STATE1_SZ 32 | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* State1 block size for SM3 */ | |||||
#define ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ 200 | #define ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ 200 | ||||
/** <@ingroup icp_cpm_hw_defs | /** <@ingroup icp_cpm_hw_defs | ||||
* State1 block size for stateful SHA3 processing*/ | * State1 block size for stateful SHA3 processing*/ | ||||
#define ICP_QAT_HW_SM3_STATE1_SZ 32 | |||||
/**< @ingroup icp_cpm_hw_defs | |||||
* State1 block size for SM3 */ | |||||
/* State2 */ | /* State2 */ | ||||
#define ICP_QAT_HW_NULL_STATE2_SZ 64 | #define ICP_QAT_HW_NULL_STATE2_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for NULL hashing */ | * State2 block size for NULL hashing */ | ||||
#define ICP_QAT_HW_MD5_STATE2_SZ 16 | #define ICP_QAT_HW_MD5_STATE2_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for MD5 */ | * State2 block size for MD5 */ | ||||
#define ICP_QAT_HW_SHA1_STATE2_SZ 20 | #define ICP_QAT_HW_SHA1_STATE2_SZ 20 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA1 - Note that for the QAT HW the state is rounded | * State2 block size for SHA1 - Note that for the QAT HW the state is rounded | ||||
* to the nearest 8 byte multiple */ | * to the nearest 8 byte multiple */ | ||||
#define ICP_QAT_HW_SHA224_STATE2_SZ 32 | #define ICP_QAT_HW_SHA224_STATE2_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA224 */ | * State2 block size for SHA224 */ | ||||
#define ICP_QAT_HW_SHA3_224_STATE2_SZ 32 | #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA3_224 */ | * State2 block size for SHA3_224 */ | ||||
#define ICP_QAT_HW_SHA256_STATE2_SZ 32 | #define ICP_QAT_HW_SHA256_STATE2_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA256 */ | * State2 block size for SHA256 */ | ||||
#define ICP_QAT_HW_SHA3_256_STATE2_SZ 32 | #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA3_256 */ | * State2 block size for SHA3_256 */ | ||||
#define ICP_QAT_HW_SHA384_STATE2_SZ 64 | #define ICP_QAT_HW_SHA384_STATE2_SZ 64 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA384 */ | * State2 block size for SHA384 */ | ||||
#define ICP_QAT_HW_SHA3_384_STATE2_SZ 64 | #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA3_384 */ | * State2 block size for SHA3_384 */ | ||||
#define ICP_QAT_HW_SHA512_STATE2_SZ 64 | #define ICP_QAT_HW_SHA512_STATE2_SZ 64 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA512 */ | * State2 block size for SHA512 */ | ||||
#define ICP_QAT_HW_SHA3_512_STATE2_SZ 64 | #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SHA3_512 */ | * State2 block size for SHA3_512 */ | ||||
#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 | #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for XCBC */ | * State2 block size for XCBC */ | ||||
#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 | #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for CBC */ | * State2 block size for CBC */ | ||||
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/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for Galois AAD length */ | * State2 block size for Galois AAD length */ | ||||
#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 | #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for Galois Encrypted Counter 0 */ | * State2 block size for Galois Encrypted Counter 0 */ | ||||
#define ICP_QAT_HW_SM3_STATE2_SZ 32 | #define ICP_QAT_HW_SM3_STATE2_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* State2 block size for SM3 */ | * State2 block size for SM3 */ | ||||
#define ICP_QAT_HW_SHA3_STATEFUL_STATE2_SZ 208 | |||||
/** <@ingroup icp_cpm_hw_defs | |||||
* State2 block size for stateful SHA3 processing*/ | |||||
/* ************************************************************************* */ | /* ************************************************************************* */ | ||||
/* ************************************************************************* */ | /* ************************************************************************* */ | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Definition of SHA512 auth algorithm processing struct | * Definition of SHA512 auth algorithm processing struct | ||||
Show All 33 Lines | typedef struct icp_qat_hw_auth_sha3_512_s { | ||||
/**< Inner loop configuration word for the slice */ | /**< Inner loop configuration word for the slice */ | ||||
uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ]; | uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ]; | ||||
/**< Slice state1 variable */ | /**< Slice state1 variable */ | ||||
icp_qat_hw_auth_setup_t outer_setup; | icp_qat_hw_auth_setup_t outer_setup; | ||||
/**< Outer configuration word for the slice */ | /**< Outer configuration word for the slice */ | ||||
/* State2 size is zero - this may change for future implementations */ | |||||
uint8_t state2[ICP_QAT_HW_SHA3_512_STATE2_SZ]; | |||||
} icp_qat_hw_auth_sha3_512_t; | } icp_qat_hw_auth_sha3_512_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Definition of stateful SHA3 auth algorithm processing struct | |||||
* @description | |||||
* This structs described the parameters to pass to the slice for | |||||
* configuring it for stateful SHA3 processing. This is the largest | |||||
* possible setup block for authentication | |||||
* | |||||
*****************************************************************************/ | |||||
typedef struct icp_qat_hw_auth_sha3_stateful_s { | |||||
icp_qat_hw_auth_setup_t inner_setup; | |||||
/**< Inner loop configuration word for the slice */ | |||||
uint8_t inner_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; | |||||
/**< Inner hash block */ | |||||
icp_qat_hw_auth_setup_t outer_setup; | |||||
/**< Outer configuration word for the slice */ | |||||
uint8_t outer_state1[ICP_QAT_HW_SHA3_STATEFUL_STATE1_SZ]; | |||||
/**< Outer hash block */ | |||||
} icp_qat_hw_auth_sha3_stateful_t; | |||||
/** | |||||
***************************************************************************** | |||||
* @ingroup icp_qat_hw_defs | |||||
* Supported hardware authentication algorithms | * Supported hardware authentication algorithms | ||||
* @description | * @description | ||||
* Common grouping of the auth algorithm types supported by the QAT | * Common grouping of the auth algorithm types supported by the QAT | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef union icp_qat_hw_auth_algo_blk_u { | typedef union icp_qat_hw_auth_algo_blk_u { | ||||
icp_qat_hw_auth_sha512_t sha512; | icp_qat_hw_auth_sha512_t sha512; | ||||
/**< SHA512 Hashing */ | /**< SHA512 Hashing */ | ||||
icp_qat_hw_auth_sha3_stateful_t sha3_stateful; | |||||
/**< Stateful SHA3 Hashing */ | |||||
} icp_qat_hw_auth_algo_blk_t; | } icp_qat_hw_auth_algo_blk_t; | ||||
#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 | #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Bit position of the 32 bit A value in the 64 bit A configuration sent to | * Bit position of the 32 bit A value in the 64 bit A configuration sent to | ||||
* the QAT */ | * the QAT */ | ||||
Show All 13 Lines | |||||
* Enumeration used to define the cipher algorithms | * Enumeration used to define the cipher algorithms | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_CIPHER_ALGO_NULL = 0, /*!< Null ciphering */ | ICP_QAT_HW_CIPHER_ALGO_NULL = 0, /*!< Null ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_DES = 1, /*!< DES ciphering */ | ICP_QAT_HW_CIPHER_ALGO_DES = 1, /*!< DES ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_3DES = 2, /*!< 3DES ciphering */ | ICP_QAT_HW_CIPHER_ALGO_3DES = 2, /*!< 3DES ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, /*!< AES-128 ciphering */ | ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, /*!< AES-128 ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, /*!< AES-192 ciphering */ | ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, /*!< AES-192 ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, /*!< AES-256 ciphering */ | ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, /*!< AES-256 ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, /*!< ARC4 ciphering */ | ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, /*!< ARC4 ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, /*!< Kasumi */ | ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, /*!< Kasumi */ | ||||
ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /*!< Snow_3G */ | ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /*!< Snow_3G */ | ||||
ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, /*!< ZUC_3G */ | ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, /*!< ZUC_3G */ | ||||
ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, /*!< SM4 ciphering */ | ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, /*!< SM4 ciphering */ | ||||
ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = | ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = | ||||
11, /*!< CHACHA POLY SPC AEAD */ | 11, /*!< CHACHA POLY SPC AEAD */ | ||||
ICP_QAT_HW_CIPHER_DELIMITER = 12 /**< Delimiter type */ | ICP_QAT_HW_CIPHER_DELIMITER = 12 /**< Delimiter type */ | ||||
} icp_qat_hw_cipher_algo_t; | } icp_qat_hw_cipher_algo_t; | ||||
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*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_CIPHER_ECB_MODE = 0, /*!< ECB mode */ | ICP_QAT_HW_CIPHER_ECB_MODE = 0, /*!< ECB mode */ | ||||
ICP_QAT_HW_CIPHER_CBC_MODE = 1, /*!< CBC more */ | ICP_QAT_HW_CIPHER_CBC_MODE = 1, /*!< CBC more */ | ||||
ICP_QAT_HW_CIPHER_CTR_MODE = 2, /*!< CTR mode */ | ICP_QAT_HW_CIPHER_CTR_MODE = 2, /*!< CTR mode */ | ||||
ICP_QAT_HW_CIPHER_F8_MODE = 3, /*!< F8 mode */ | ICP_QAT_HW_CIPHER_F8_MODE = 3, /*!< F8 mode */ | ||||
ICP_QAT_HW_CIPHER_AEAD_MODE = 4, /*!< AES-GCM SPC AEAD mode */ | ICP_QAT_HW_CIPHER_AEAD_MODE = 4, /*!< AES-GCM SPC AEAD mode */ | ||||
ICP_QAT_HW_CIPHER_RESERVED_MODE = 5, /*!< Reserved */ | ICP_QAT_HW_CIPHER_CCM_MODE = 5, /*!< AES-CCM SPC AEAD mode */ | ||||
ICP_QAT_HW_CIPHER_XTS_MODE = 6, /*!< XTS mode */ | ICP_QAT_HW_CIPHER_XTS_MODE = 6, /*!< XTS mode */ | ||||
ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 /**< Delimiter type */ | ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 /**< Delimiter type */ | ||||
} icp_qat_hw_cipher_mode_t; | } icp_qat_hw_cipher_mode_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Cipher Configuration Struct | * Cipher Configuration Struct | ||||
Show All 9 Lines | typedef struct icp_qat_hw_cipher_config_s { | ||||
uint32_t reserved; | uint32_t reserved; | ||||
/**< Reserved */ | /**< Reserved */ | ||||
} icp_qat_hw_cipher_config_t; | } icp_qat_hw_cipher_config_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Cipher Configuration Struct | |||||
* | |||||
* @description | |||||
* Configuration data used for setting up the QAT UCS Cipher Slice | |||||
* | |||||
*****************************************************************************/ | |||||
typedef struct icp_qat_hw_ucs_cipher_config_s { | |||||
uint32_t val; | |||||
/**< Cipher slice configuration */ | |||||
uint32_t reserved[3]; | |||||
/**< Reserved */ | |||||
} icp_qat_hw_ucs_cipher_config_t; | |||||
/** | |||||
***************************************************************************** | |||||
* @ingroup icp_qat_hw_defs | |||||
* Definition of the cipher direction | * Definition of the cipher direction | ||||
* @description | * @description | ||||
* Enumeration which is used to define the cipher direction to apply | * Enumeration which is used to define the cipher direction to apply | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
/*!< Flag to indicate that encryption is required */ | /*!< Flag to indicate that encryption is required */ | ||||
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#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 | #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define for the cipher mode F8 key size */ | * Define for the cipher mode F8 key size */ | ||||
#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 | #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define for the cipher XTS mode key size */ | * Define for the cipher XTS mode key size */ | ||||
#define QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT 1 | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define for the UCS cipher XTS mode key size */ | |||||
/** | /** | ||||
****************************************************************************** | ****************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* | * | ||||
* @description | * @description | ||||
* Build the cipher configuration field | * Build the cipher configuration field | ||||
* | * | ||||
* @param mode Cipher Mode to use | * @param mode Cipher Mode to use | ||||
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/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES128 */ | * Define the key size for AES128 */ | ||||
#define ICP_QAT_HW_AES_192_KEY_SZ 24 | #define ICP_QAT_HW_AES_192_KEY_SZ 24 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES192 */ | * Define the key size for AES192 */ | ||||
#define ICP_QAT_HW_AES_256_KEY_SZ 32 | #define ICP_QAT_HW_AES_256_KEY_SZ 32 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES256 */ | * Define the key size for AES256 */ | ||||
/* AES UCS */ | |||||
#define ICP_QAT_HW_UCS_AES_128_KEY_SZ ICP_QAT_HW_AES_128_KEY_SZ | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define the key size for AES128 for UCS slice*/ | |||||
#define ICP_QAT_HW_UCS_AES_192_KEY_SZ 32 | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define the key size for AES192 for UCS slice*/ | |||||
#define ICP_QAT_HW_UCS_AES_256_KEY_SZ ICP_QAT_HW_AES_256_KEY_SZ | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define the key size for AES256 for UCS slice*/ | |||||
#define ICP_QAT_HW_AES_128_F8_KEY_SZ \ | #define ICP_QAT_HW_AES_128_F8_KEY_SZ \ | ||||
(ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES128 F8 */ | * Define the key size for AES128 F8 */ | ||||
#define ICP_QAT_HW_AES_192_F8_KEY_SZ \ | #define ICP_QAT_HW_AES_192_F8_KEY_SZ \ | ||||
(ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | (ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES192 F8 */ | * Define the key size for AES192 F8 */ | ||||
#define ICP_QAT_HW_AES_256_F8_KEY_SZ \ | #define ICP_QAT_HW_AES_256_F8_KEY_SZ \ | ||||
(ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES256 F8 */ | * Define the key size for AES256 F8 */ | ||||
#define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ | #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ | ||||
(ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) | (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES128 XTS */ | * Define the key size for AES128 XTS */ | ||||
#define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ | #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ | ||||
(ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) | (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for AES256 XTS */ | * Define the key size for AES256 XTS */ | ||||
#define ICP_QAT_HW_UCS_AES_128_XTS_KEY_SZ \ | |||||
(ICP_QAT_HW_UCS_AES_128_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define the key size for AES128 XTS for the UCS Slice*/ | |||||
#define ICP_QAT_HW_UCS_AES_256_XTS_KEY_SZ \ | |||||
(ICP_QAT_HW_UCS_AES_256_KEY_SZ * QAT_CIPHER_MODE_UCS_XTS_KEY_SZ_MULT) | |||||
/**< @ingroup icp_qat_hw_defs | |||||
* Define the key size for AES256 XTS for the UCS Slice*/ | |||||
#define ICP_QAT_HW_KASUMI_KEY_SZ 16 | #define ICP_QAT_HW_KASUMI_KEY_SZ 16 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for Kasumi */ | * Define the key size for Kasumi */ | ||||
#define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ | #define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ | ||||
(ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | (ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define the key size for Kasumi F8 */ | * Define the key size for Kasumi F8 */ | ||||
#define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ | #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ | ||||
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* Definition of the supported TRNG KAT (known answer test) modes | * Definition of the supported TRNG KAT (known answer test) modes | ||||
* @description | * @description | ||||
* Enumeration which is used to define the TRNG KAT modes. Used by clients | * Enumeration which is used to define the TRNG KAT modes. Used by clients | ||||
* when configuring the TRNG for testing | * when configuring the TRNG for testing | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_TRNG_NEG_0 = 0, /*!< TRNG Neg Zero Test */ | ICP_QAT_HW_TRNG_NEG_0 = 0, /*!< TRNG Neg Zero Test */ | ||||
ICP_QAT_HW_TRNG_NEG_1 = 1, /*!< TRNG Neg One Test */ | ICP_QAT_HW_TRNG_NEG_1 = 1, /*!< TRNG Neg One Test */ | ||||
ICP_QAT_HW_TRNG_POS = 2, /*!< TRNG POS Test */ | ICP_QAT_HW_TRNG_POS = 2, /*!< TRNG POS Test */ | ||||
ICP_QAT_HW_TRNG_POS_VNC = 3, /*!< TRNG POS VNC Test */ | ICP_QAT_HW_TRNG_POS_VNC = 3, /*!< TRNG POS VNC Test */ | ||||
ICP_QAT_HW_TRNG_KAT_DELIMITER = 4 /**< Delimiter type */ | ICP_QAT_HW_TRNG_KAT_DELIMITER = 4 /**< Delimiter type */ | ||||
} icp_qat_hw_trng_kat_mode_t; | } icp_qat_hw_trng_kat_mode_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* TRNG mode configuration structure. | * TRNG mode configuration structure. | ||||
* | * | ||||
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* Definition of the supported compression algorithms | * Definition of the supported compression algorithms | ||||
* @description | * @description | ||||
* Enumeration used to define the compression algorithms | * Enumeration used to define the compression algorithms | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef enum { | typedef enum { | ||||
ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, /*!< Deflate compression */ | ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0, /*!< Deflate compression */ | ||||
ICP_QAT_HW_COMPRESSION_DEPRECATED = 1, /*!< Deprecated */ | ICP_QAT_HW_COMPRESSION_DEPRECATED = 1, /*!< Deprecated */ | ||||
ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 /**< Delimiter type */ | ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2 /**< Delimiter type */ | ||||
} icp_qat_hw_compression_algo_t; | } icp_qat_hw_compression_algo_t; | ||||
/** | /** | ||||
***************************************************************************** | ***************************************************************************** | ||||
* @ingroup icp_qat_hw_defs | * @ingroup icp_qat_hw_defs | ||||
* Definition of the supported compression depths | * Definition of the supported compression depths | ||||
* @description | * @description | ||||
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* Compression Configuration Struct | * Compression Configuration Struct | ||||
* | * | ||||
* @description | * @description | ||||
* Configuration data used for setting up the QAT Compression Slice | * Configuration data used for setting up the QAT Compression Slice | ||||
* | * | ||||
*****************************************************************************/ | *****************************************************************************/ | ||||
typedef struct icp_qat_hw_compression_config_s { | typedef struct icp_qat_hw_compression_config_s { | ||||
uint32_t val; | uint32_t lower_val; | ||||
/**< Compression slice configuration */ | /**< Compression slice configuration lower LW */ | ||||
uint32_t reserved; | uint32_t upper_val; | ||||
/**< Reserved */ | /**< Compression slice configuration upper LW */ | ||||
} icp_qat_hw_compression_config_t; | } icp_qat_hw_compression_config_t; | ||||
/* Private defines */ | /* Private defines */ | ||||
#define QAT_COMPRESSION_DIR_BITPOS 4 | #define QAT_COMPRESSION_DIR_BITPOS 4 | ||||
/**< @ingroup icp_qat_hw_defs | /**< @ingroup icp_qat_hw_defs | ||||
* Define for the compression direction bit position */ | * Define for the compression direction bit position */ | ||||
#define QAT_COMPRESSION_DIR_MASK 0x7 | #define QAT_COMPRESSION_DIR_MASK 0x7 | ||||
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