Page MenuHomeFreeBSD
Differential D36254 Diff 115177 sys/dev/qat/include/common/adf_accel_devices.h

Changeset View

Standalone View

View Options

sys/dev/qat/include/common/adf_accel_devices.h

Show All 13 Lines
#define ADF_C62X_DEVICE_NAME "c6xx" #define ADF_C62X_DEVICE_NAME "c6xx"
#define ADF_C62XVF_DEVICE_NAME "c6xxvf" #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
#define ADF_C3XXX_DEVICE_NAME "c3xxx" #define ADF_C3XXX_DEVICE_NAME "c3xxx"
#define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf" #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
#define ADF_200XX_DEVICE_NAME "200xx" #define ADF_200XX_DEVICE_NAME "200xx"
#define ADF_200XXVF_DEVICE_NAME "200xxvf" #define ADF_200XXVF_DEVICE_NAME "200xxvf"
#define ADF_C4XXX_DEVICE_NAME "c4xxx" #define ADF_C4XXX_DEVICE_NAME "c4xxx"
#define ADF_C4XXXVF_DEVICE_NAME "c4xxxvf" #define ADF_C4XXXVF_DEVICE_NAME "c4xxxvf"
#define ADF_4XXX_DEVICE_NAME "4xxx"
#define ADF_DH895XCC_PCI_DEVICE_ID 0x435 #define ADF_DH895XCC_PCI_DEVICE_ID 0x435
#define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443 #define ADF_DH895XCCIOV_PCI_DEVICE_ID 0x443
#define ADF_C62X_PCI_DEVICE_ID 0x37c8 #define ADF_C62X_PCI_DEVICE_ID 0x37c8
#define ADF_C62XIOV_PCI_DEVICE_ID 0x37c9 #define ADF_C62XIOV_PCI_DEVICE_ID 0x37c9
#define ADF_C3XXX_PCI_DEVICE_ID 0x19e2 #define ADF_C3XXX_PCI_DEVICE_ID 0x19e2
#define ADF_C3XXXIOV_PCI_DEVICE_ID 0x19e3 #define ADF_C3XXXIOV_PCI_DEVICE_ID 0x19e3
#define ADF_200XX_PCI_DEVICE_ID 0x18ee #define ADF_200XX_PCI_DEVICE_ID 0x18ee
#define ADF_200XXIOV_PCI_DEVICE_ID 0x18ef #define ADF_200XXIOV_PCI_DEVICE_ID 0x18ef
#define ADF_D15XX_PCI_DEVICE_ID 0x6f54 #define ADF_D15XX_PCI_DEVICE_ID 0x6f54
#define ADF_D15XXIOV_PCI_DEVICE_ID 0x6f55 #define ADF_D15XXIOV_PCI_DEVICE_ID 0x6f55
#define ADF_C4XXX_PCI_DEVICE_ID 0x18a0 #define ADF_C4XXX_PCI_DEVICE_ID 0x18a0
#define ADF_C4XXXIOV_PCI_DEVICE_ID 0x18a1 #define ADF_C4XXXIOV_PCI_DEVICE_ID 0x18a1
#define ADF_4XXX_PCI_DEVICE_ID 0x4940
#define ADF_401XX_PCI_DEVICE_ID 0x4942
#define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); }) #define IS_QAT_GEN3(ID) ({ (ID == ADF_C4XXX_PCI_DEVICE_ID); })
static inline bool
IS_QAT_GEN4(const unsigned int id)
{
return (id == ADF_4XXX_PCI_DEVICE_ID || id == ADF_401XX_PCI_DEVICE_ID);
}
#define IS_QAT_GEN3_OR_GEN4(ID) (IS_QAT_GEN3(ID) || IS_QAT_GEN4(ID))
#define ADF_VF2PF_SET_SIZE 32 #define ADF_VF2PF_SET_SIZE 32
#define ADF_MAX_VF2PF_SET 4 #define ADF_MAX_VF2PF_SET 4
#define ADF_VF2PF_SET_OFFSET(set_nr) ((set_nr)*ADF_VF2PF_SET_SIZE) #define ADF_VF2PF_SET_OFFSET(set_nr) ((set_nr)*ADF_VF2PF_SET_SIZE)
#define ADF_VF2PF_VFNR_TO_SET(vf_nr) ((vf_nr) / ADF_VF2PF_SET_SIZE) #define ADF_VF2PF_VFNR_TO_SET(vf_nr) ((vf_nr) / ADF_VF2PF_SET_SIZE)
#define ADF_VF2PF_VFNR_TO_MASK(vf_nr) \ #define ADF_VF2PF_VFNR_TO_MASK(vf_nr) \
({ \ ({ \
u32 vf_nr_ = (vf_nr); \ u32 vf_nr_ = (vf_nr); \
BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET( \ BIT((vf_nr_)-ADF_VF2PF_SET_SIZE *ADF_VF2PF_VFNR_TO_SET( \
vf_nr_)); \ vf_nr_)); \
}) })
#define ADF_DEVICE_FUSECTL_OFFSET 0x40 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
#define ADF_DEVICE_LEGFUSE_OFFSET 0x4C #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
#define ADF_DEVICE_FUSECTL_MASK 0x80000000 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
#define ADF_PCI_MAX_BARS 3 #define ADF_PCI_MAX_BARS 3
#define ADF_DEVICE_NAME_LENGTH 32 #define ADF_DEVICE_NAME_LENGTH 32
#define ADF_ETR_MAX_RINGS_PER_BANK 16 #define ADF_ETR_MAX_RINGS_PER_BANK 16
#define ADF_MAX_MSIX_VECTOR_NAME 16 #define ADF_MAX_MSIX_VECTOR_NAME 32
#define ADF_DEVICE_NAME_PREFIX "qat_" #define ADF_DEVICE_NAME_PREFIX "qat_"
#define ADF_STOP_RETRY 50 #define ADF_STOP_RETRY 50
#define ADF_NUM_THREADS_PER_AE (8) #define ADF_NUM_THREADS_PER_AE (8)
#define ADF_AE_ADMIN_THREAD (7) #define ADF_AE_ADMIN_THREAD (7)
#define ADF_NUM_PKE_STRAND (2) #define ADF_NUM_PKE_STRAND (2)
#define ADF_AE_STRAND0_THREAD (8) #define ADF_AE_STRAND0_THREAD (8)
#define ADF_AE_STRAND1_THREAD (9) #define ADF_AE_STRAND1_THREAD (9)
#define ADF_NUM_HB_CNT_PER_AE (ADF_NUM_THREADS_PER_AE + ADF_NUM_PKE_STRAND)
#define ADF_CFG_NUM_SERVICES 4 #define ADF_CFG_NUM_SERVICES 4
#define ADF_SRV_TYPE_BIT_LEN 3 #define ADF_SRV_TYPE_BIT_LEN 3
#define ADF_SRV_TYPE_MASK 0x7 #define ADF_SRV_TYPE_MASK 0x7
#define ADF_RINGS_PER_SRV_TYPE 2 #define ADF_RINGS_PER_SRV_TYPE 2
#define ADF_THRD_ABILITY_BIT_LEN 4 #define ADF_THRD_ABILITY_BIT_LEN 4
#define ADF_THRD_ABILITY_MASK 0xf #define ADF_THRD_ABILITY_MASK 0xf
#define ADF_VF_OFFSET 0x8 #define ADF_VF_OFFSET 0x8
#define ADF_MAX_FUNC_PER_DEV 0x7 #define ADF_MAX_FUNC_PER_DEV 0x7
#define ADF_PCI_DEV_OFFSET 0x3 #define ADF_PCI_DEV_OFFSET 0x3
#define ADF_SRV_TYPE_BIT_LEN 3 #define ADF_SRV_TYPE_BIT_LEN 3
#define ADF_SRV_TYPE_MASK 0x7 #define ADF_SRV_TYPE_MASK 0x7
#define GET_SRV_TYPE(ena_srv_mask, srv) \ #define GET_SRV_TYPE(ena_srv_mask, srv) \
(((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK) (((ena_srv_mask) >> (ADF_SRV_TYPE_BIT_LEN * (srv))) & ADF_SRV_TYPE_MASK)
#define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_info.csr_ops)
#define ADF_DEFAULT_RING_TO_SRV_MAP \ #define ADF_DEFAULT_RING_TO_SRV_MAP \
(CRYPTO | CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \ (CRYPTO | CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
NA << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \ NA << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT) COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
enum adf_accel_capabilities { enum adf_accel_capabilities {
ADF_ACCEL_CAPABILITIES_NULL = 0, ADF_ACCEL_CAPABILITIES_NULL = 0,
ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1, ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Linesget_sku_info(enum dev_sku_info info)
} }
return "Unknown SKU"; return "Unknown SKU";
} }
enum adf_accel_unit_services { enum adf_accel_unit_services {
ADF_ACCEL_SERVICE_NULL = 0, ADF_ACCEL_SERVICE_NULL = 0,
ADF_ACCEL_INLINE_CRYPTO = 1, ADF_ACCEL_INLINE_CRYPTO = 1,
ADF_ACCEL_CRYPTO = 2, ADF_ACCEL_CRYPTO = 2,
ADF_ACCEL_COMPRESSION = 4 ADF_ACCEL_COMPRESSION = 4,
ADF_ACCEL_ASYM = 8,
ADF_ACCEL_ADMIN = 16
}; };
struct adf_ae_info { struct adf_ae_info {
u32 num_asym_thd; u32 num_asym_thd;
u32 num_sym_thd; u32 num_sym_thd;
u32 num_dc_thd; u32 num_dc_thd;
} __packed; } __packed;
Show All 9 Lines
struct adf_accel_unit_info { struct adf_accel_unit_info {
u32 inline_ingress_msk; u32 inline_ingress_msk;
u32 inline_egress_msk; u32 inline_egress_msk;
u32 sym_ae_msk; u32 sym_ae_msk;
u32 asym_ae_msk; u32 asym_ae_msk;
u32 dc_ae_msk; u32 dc_ae_msk;
u8 num_cy_au; u8 num_cy_au;
u8 num_dc_au; u8 num_dc_au;
u8 num_asym_au;
u8 num_inline_au; u8 num_inline_au;
struct adf_accel_unit *au; struct adf_accel_unit *au;
const struct adf_ae_info *ae_info; const struct adf_ae_info *ae_info;
} __packed; } __packed;
struct adf_hw_aram_info { struct adf_hw_aram_info {
/* Inline Egress mask. "1" = AE is working with egress traffic */ /* Inline Egress mask. "1" = AE is working with egress traffic */
u32 inline_direction_egress_mask; u32 inline_direction_egress_mask;
Show All 33 Lines
} __packed; } __packed;
struct admin_info { struct admin_info {
u32 admin_msg_ur; u32 admin_msg_ur;
u32 admin_msg_lr; u32 admin_msg_lr;
u32 mailbox_offset; u32 mailbox_offset;
} __packed; } __packed;
struct adf_hw_csr_ops {
u64 (*build_csr_ring_base_addr)(bus_addr_t addr, u32 size);
u32 (*read_csr_ring_head)(struct resource *csr_base_addr,
u32 bank,
u32 ring);
void (*write_csr_ring_head)(struct resource *csr_base_addr,
u32 bank,
u32 ring,
u32 value);
u32 (*read_csr_ring_tail)(struct resource *csr_base_addr,
u32 bank,
u32 ring);
void (*write_csr_ring_tail)(struct resource *csr_base_addr,
u32 bank,
u32 ring,
u32 value);
u32 (*read_csr_e_stat)(struct resource *csr_base_addr, u32 bank);
void (*write_csr_ring_config)(struct resource *csr_base_addr,
u32 bank,
u32 ring,
u32 value);
void (*write_csr_ring_base)(struct resource *csr_base_addr,
u32 bank,
u32 ring,
bus_addr_t addr);
void (*write_csr_int_flag)(struct resource *csr_base_addr,
u32 bank,
u32 value);
void (*write_csr_int_srcsel)(struct resource *csr_base_addr, u32 bank);
void (*write_csr_int_col_en)(struct resource *csr_base_addr,
u32 bank,
u32 value);
void (*write_csr_int_col_ctl)(struct resource *csr_base_addr,
u32 bank,
u32 value);
void (*write_csr_int_flag_and_col)(struct resource *csr_base_addr,
u32 bank,
u32 value);
u32 (*read_csr_ring_srv_arb_en)(struct resource *csr_base_addr,
u32 bank);
void (*write_csr_ring_srv_arb_en)(struct resource *csr_base_addr,
u32 bank,
u32 value);
};
struct adf_hw_csr_info {
struct adf_hw_csr_ops csr_ops;
u32 csr_addr_offset;
u32 ring_bundle_size;
u32 bank_int_flag_clear_mask;
u32 num_rings_per_int_srcsel;
u32 arb_enable_mask;
};
struct adf_cfg_device_data; struct adf_cfg_device_data;
struct adf_accel_dev; struct adf_accel_dev;
struct adf_etr_data; struct adf_etr_data;
struct adf_etr_ring_data; struct adf_etr_ring_data;
struct adf_hw_device_data { struct adf_hw_device_data {
struct adf_hw_device_class *dev_class; struct adf_hw_device_class *dev_class;
uint32_t (*get_accel_mask)(struct adf_accel_dev *accel_dev); uint32_t (*get_accel_mask)(struct adf_accel_dev *accel_dev);
Show All 35 Linesstruct adf_hw_device_data {
void (*set_asym_rings_mask)(struct adf_accel_dev *accel_dev); void (*set_asym_rings_mask)(struct adf_accel_dev *accel_dev);
int (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev, int (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev,
u16 *ring_to_svc_map); u16 *ring_to_svc_map);
uint32_t (*get_accel_cap)(struct adf_accel_dev *accel_dev); uint32_t (*get_accel_cap)(struct adf_accel_dev *accel_dev);
int (*init_arb)(struct adf_accel_dev *accel_dev); int (*init_arb)(struct adf_accel_dev *accel_dev);
void (*exit_arb)(struct adf_accel_dev *accel_dev); void (*exit_arb)(struct adf_accel_dev *accel_dev);
void (*get_arb_mapping)(struct adf_accel_dev *accel_dev, void (*get_arb_mapping)(struct adf_accel_dev *accel_dev,
const uint32_t **cfg); const uint32_t **cfg);
int (*init_device)(struct adf_accel_dev *accel_dev);
int (*get_heartbeat_status)(struct adf_accel_dev *accel_dev); int (*get_heartbeat_status)(struct adf_accel_dev *accel_dev);
uint32_t (*get_ae_clock)(struct adf_hw_device_data *self); uint32_t (*get_ae_clock)(struct adf_hw_device_data *self);
uint32_t (*get_hb_clock)(struct adf_hw_device_data *self);
void (*disable_iov)(struct adf_accel_dev *accel_dev); void (*disable_iov)(struct adf_accel_dev *accel_dev);
void (*configure_iov_threads)(struct adf_accel_dev *accel_dev, void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
bool enable); bool enable);
void (*enable_ints)(struct adf_accel_dev *accel_dev); void (*enable_ints)(struct adf_accel_dev *accel_dev);
bool (*check_slice_hang)(struct adf_accel_dev *accel_dev); bool (*check_slice_hang)(struct adf_accel_dev *accel_dev);
int (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev); int (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev); int (*enable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
int (*disable_vf2pf_comms)(struct adf_accel_dev *accel_dev); int (*disable_vf2pf_comms)(struct adf_accel_dev *accel_dev);
void (*reset_device)(struct adf_accel_dev *accel_dev); void (*reset_device)(struct adf_accel_dev *accel_dev);
void (*reset_hw_units)(struct adf_accel_dev *accel_dev); void (*reset_hw_units)(struct adf_accel_dev *accel_dev);
int (*measure_clock)(struct adf_accel_dev *accel_dev); int (*measure_clock)(struct adf_accel_dev *accel_dev);
void (*restore_device)(struct adf_accel_dev *accel_dev); void (*restore_device)(struct adf_accel_dev *accel_dev);
uint32_t (*get_obj_cfg_ae_mask)(struct adf_accel_dev *accel_dev, uint32_t (*get_obj_cfg_ae_mask)(struct adf_accel_dev *accel_dev,
enum adf_accel_unit_services services); enum adf_accel_unit_services services);
enum adf_accel_unit_services (
*get_service_type)(struct adf_accel_dev *accel_dev, s32 obj_num);
int (*add_pke_stats)(struct adf_accel_dev *accel_dev); int (*add_pke_stats)(struct adf_accel_dev *accel_dev);
void (*remove_pke_stats)(struct adf_accel_dev *accel_dev); void (*remove_pke_stats)(struct adf_accel_dev *accel_dev);
int (*add_misc_error)(struct adf_accel_dev *accel_dev); int (*add_misc_error)(struct adf_accel_dev *accel_dev);
int (*count_ras_event)(struct adf_accel_dev *accel_dev, int (*count_ras_event)(struct adf_accel_dev *accel_dev,
u32 *ras_event, u32 *ras_event,
char *aeidstr); char *aeidstr);
void (*remove_misc_error)(struct adf_accel_dev *accel_dev); void (*remove_misc_error)(struct adf_accel_dev *accel_dev);
int (*configure_accel_units)(struct adf_accel_dev *accel_dev); int (*configure_accel_units)(struct adf_accel_dev *accel_dev);
uint32_t (*get_objs_num)(struct adf_accel_dev *accel_dev); uint32_t (*get_objs_num)(struct adf_accel_dev *accel_dev);
const char *(*get_obj_name)(struct adf_accel_dev *accel_dev, const char *(*get_obj_name)(struct adf_accel_dev *accel_dev,
enum adf_accel_unit_services services); enum adf_accel_unit_services services);
void (*pre_reset)(struct adf_accel_dev *accel_dev); void (*pre_reset)(struct adf_accel_dev *accel_dev);
void (*post_reset)(struct adf_accel_dev *accel_dev); void (*post_reset)(struct adf_accel_dev *accel_dev);
void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
void (*get_ring_svc_map_data)(int ring_pair_index,
u16 ring_to_svc_map,
u8 *serv_type,
int *ring_index,
int *num_rings_per_srv,
int bundle_num);
struct adf_hw_csr_info csr_info;
const char *fw_name; const char *fw_name;
const char *fw_mmp_name; const char *fw_mmp_name;
bool reset_ack; bool reset_ack;
uint32_t fuses; uint32_t fuses;
uint32_t accel_capabilities_mask; uint32_t accel_capabilities_mask;
uint32_t instance_id; uint32_t instance_id;
uint16_t accel_mask; uint16_t accel_mask;
u32 aerucm_mask; u32 aerucm_mask;
u32 ae_mask; u32 ae_mask;
u32 admin_ae_mask;
u32 service_mask; u32 service_mask;
u32 service_to_load_mask;
u32 heartbeat_ctr_num;
uint16_t tx_rings_mask; uint16_t tx_rings_mask;
uint8_t tx_rx_gap; uint8_t tx_rx_gap;
uint8_t num_banks; uint8_t num_banks;
u8 num_rings_per_bank; u8 num_rings_per_bank;
uint8_t num_accel; uint8_t num_accel;
uint8_t num_logical_accel; uint8_t num_logical_accel;
uint8_t num_engines; uint8_t num_engines;
uint8_t min_iov_compat_ver; uint8_t min_iov_compat_ver;
▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines