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sys/mips/mips/exception.S
Show First 20 Lines • Show All 640 Lines • ▼ Show 20 Lines | |||||
/* | /* | ||||
* Save CPU state, building 'frame'. | * Save CPU state, building 'frame'. | ||||
*/ | */ | ||||
SAVE_CPU | SAVE_CPU | ||||
/* | /* | ||||
* Call the interrupt handler. a0 points at the saved frame. | * Call the interrupt handler. a0 points at the saved frame. | ||||
*/ | */ | ||||
PTR_LA gp, _C_LABEL(_gp) | PTR_LA gp, _C_LABEL(_gp) | ||||
#ifdef MIPS_INTRNG | |||||
PTR_LA k0, _C_LABEL(intr_irq_handler) | |||||
#else | |||||
PTR_LA k0, _C_LABEL(cpu_intr) | PTR_LA k0, _C_LABEL(cpu_intr) | ||||
#endif | |||||
jalr k0 | jalr k0 | ||||
REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging | REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging | ||||
/* | /* | ||||
* Update interrupt and CPU mask in saved status register | * Update interrupt and CPU mask in saved status register | ||||
* Some of interrupts could be disabled by | * Some of interrupts could be disabled by | ||||
* intr filters if interrupts are enabled later | * intr filters if interrupts are enabled later | ||||
* in trap handler | * in trap handler | ||||
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines | #elif defined(CPU_RMI) || defined(CPU_NLM) | ||||
or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) | or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) | ||||
#endif | #endif | ||||
mtc0 t0, MIPS_COP_0_STATUS | mtc0 t0, MIPS_COP_0_STATUS | ||||
ITLBNOPFIX | ITLBNOPFIX | ||||
PTR_ADDU a0, k1, U_PCB_REGS | PTR_ADDU a0, k1, U_PCB_REGS | ||||
/* | /* | ||||
* Call the interrupt handler. | * Call the interrupt handler. | ||||
*/ | */ | ||||
#ifdef MIPS_INTRNG | |||||
PTR_LA k0, _C_LABEL(intr_irq_handler) | |||||
#else | |||||
PTR_LA k0, _C_LABEL(cpu_intr) | PTR_LA k0, _C_LABEL(cpu_intr) | ||||
#endif | |||||
jalr k0 | jalr k0 | ||||
REG_S a3, CALLFRAME_RA(sp) # for debugging | REG_S a3, CALLFRAME_RA(sp) # for debugging | ||||
/* | /* | ||||
* Enable interrupts before doing ast(). | * Enable interrupts before doing ast(). | ||||
* | * | ||||
* On SMP kernels the AST processing might trigger IPI to other processors. | * On SMP kernels the AST processing might trigger IPI to other processors. | ||||
* If that processor is also doing AST processing with interrupts disabled | * If that processor is also doing AST processing with interrupts disabled | ||||
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Lines | FPReturn: | ||||
PTR_L ra, CALLFRAME_RA(sp) | PTR_L ra, CALLFRAME_RA(sp) | ||||
and t0, t0, ~MIPS_SR_COP_1_BIT | and t0, t0, ~MIPS_SR_COP_1_BIT | ||||
mtc0 t0, MIPS_COP_0_STATUS | mtc0 t0, MIPS_COP_0_STATUS | ||||
ITLBNOPFIX | ITLBNOPFIX | ||||
j ra | j ra | ||||
PTR_ADDU sp, sp, CALLFRAME_SIZ | PTR_ADDU sp, sp, CALLFRAME_SIZ | ||||
END(MipsFPTrap) | END(MipsFPTrap) | ||||
#ifndef MIPS_INTRNG | |||||
/* | /* | ||||
* Interrupt counters for vmstat. | * Interrupt counters for vmstat. | ||||
*/ | */ | ||||
.data | .data | ||||
.globl intrcnt | .globl intrcnt | ||||
.globl sintrcnt | .globl sintrcnt | ||||
.globl intrnames | .globl intrnames | ||||
.globl sintrnames | .globl sintrnames | ||||
Show All 10 Lines | |||||
intrcnt: | intrcnt: | ||||
.space INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | .space INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | ||||
sintrcnt: | sintrcnt: | ||||
#ifdef __mips_n64 | #ifdef __mips_n64 | ||||
.quad INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | .quad INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | ||||
#else | #else | ||||
.int INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | .int INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2 | ||||
#endif | #endif | ||||
#endif /* MIPS_INTRNG */ | |||||
/* | /* | ||||
* Vector to real handler in KSEG1. | * Vector to real handler in KSEG1. | ||||
*/ | */ | ||||
.text | .text | ||||
VECTOR(MipsCache, unknown) | VECTOR(MipsCache, unknown) | ||||
PTR_LA k0, _C_LABEL(MipsCacheException) | PTR_LA k0, _C_LABEL(MipsCacheException) | ||||
Show All 36 Lines |