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Differential D37489 Diff 113591 usr.sbin/bhyve/pci_nvme.c

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usr.sbin/bhyve/pci_nvme.c

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} }
static bool static bool
pci_nvme_aer_limit_reached(struct pci_nvme_softc *sc) pci_nvme_aer_limit_reached(struct pci_nvme_softc *sc)
{ {
struct nvme_controller_data *cd = &sc->ctrldata; struct nvme_controller_data *cd = &sc->ctrldata;
/* AERL is a zero based value while aer_count is one's based */ /* AERL is a zero based value while aer_count is one's based */
return (sc->aer_count == (cd->aerl + 1)); return (sc->aer_count == (cd->aerl + 1U));
} }
/* /*
* Add an Async Event Request * Add an Async Event Request
* *
* Stores an AER to be returned later if the Controller needs to notify the * Stores an AER to be returned later if the Controller needs to notify the
* host of an event. * host of an event.
* Note that while the NVMe spec doesn't require Controllers to return AER's * Note that while the NVMe spec doesn't require Controllers to return AER's
▲ Show 20 Lines • Show All 2,428 Lines • ▼ Show 20 Lines if (value != NULL) {
sc->nvstore.size = blockif_size(sc->nvstore.ctx); sc->nvstore.size = blockif_size(sc->nvstore.ctx);
} }
if (sectsz == 512 || sectsz == 4096 || sectsz == 8192) if (sectsz == 512 || sectsz == 4096 || sectsz == 8192)
sc->nvstore.sectsz = sectsz; sc->nvstore.sectsz = sectsz;
else if (sc->nvstore.type != NVME_STOR_RAM) else if (sc->nvstore.type != NVME_STOR_RAM)
sc->nvstore.sectsz = blockif_sectsz(sc->nvstore.ctx); sc->nvstore.sectsz = blockif_sectsz(sc->nvstore.ctx);
for (sc->nvstore.sectsz_bits = 9; for (sc->nvstore.sectsz_bits = 9;
(1 << sc->nvstore.sectsz_bits) < sc->nvstore.sectsz; (1U << sc->nvstore.sectsz_bits) < sc->nvstore.sectsz;
sc->nvstore.sectsz_bits++); sc->nvstore.sectsz_bits++);
if (sc->max_queues <= 0 || sc->max_queues > NVME_QUEUES) if (sc->max_queues <= 0 || sc->max_queues > NVME_QUEUES)
sc->max_queues = NVME_QUEUES; sc->max_queues = NVME_QUEUES;
return (0); return (0);
} }
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