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head/sys/riscv/riscv/swtch.S
Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines | ENTRY(cpu_throw) | ||||
/* TODO: Invalidate the TLB */ | /* TODO: Invalidate the TLB */ | ||||
sfence.vm | sfence.vm | ||||
/* Load registers */ | /* Load registers */ | ||||
ld ra, (PCB_RA)(x13) | ld ra, (PCB_RA)(x13) | ||||
ld sp, (PCB_SP)(x13) | ld sp, (PCB_SP)(x13) | ||||
ld gp, (PCB_GP)(x13) | |||||
ld tp, (PCB_TP)(x13) | |||||
/* s[0-11] */ | /* s[0-11] */ | ||||
ld s0, (PCB_S + 0 * 8)(x13) | ld s0, (PCB_S + 0 * 8)(x13) | ||||
ld s1, (PCB_S + 1 * 8)(x13) | ld s1, (PCB_S + 1 * 8)(x13) | ||||
ld s2, (PCB_S + 2 * 8)(x13) | ld s2, (PCB_S + 2 * 8)(x13) | ||||
ld s3, (PCB_S + 3 * 8)(x13) | ld s3, (PCB_S + 3 * 8)(x13) | ||||
ld s4, (PCB_S + 4 * 8)(x13) | ld s4, (PCB_S + 4 * 8)(x13) | ||||
ld s5, (PCB_S + 5 * 8)(x13) | ld s5, (PCB_S + 5 * 8)(x13) | ||||
Show All 28 Lines | ENTRY(cpu_switch) | ||||
sd x13, PC_CURPCB(x14) | sd x13, PC_CURPCB(x14) | ||||
/* Save the old context. */ | /* Save the old context. */ | ||||
ld x13, TD_PCB(a0) | ld x13, TD_PCB(a0) | ||||
/* Store the callee-saved registers */ | /* Store the callee-saved registers */ | ||||
sd ra, (PCB_RA)(x13) | sd ra, (PCB_RA)(x13) | ||||
sd sp, (PCB_SP)(x13) | sd sp, (PCB_SP)(x13) | ||||
sd gp, (PCB_GP)(x13) | |||||
sd tp, (PCB_TP)(x13) | |||||
/* We use these in fork_trampoline */ | /* We use these in fork_trampoline */ | ||||
sd t0, (PCB_T + 0 * 8)(x13) | sd t0, (PCB_T + 0 * 8)(x13) | ||||
sd t1, (PCB_T + 1 * 8)(x13) | sd t1, (PCB_T + 1 * 8)(x13) | ||||
/* s[0-11] */ | /* s[0-11] */ | ||||
sd s0, (PCB_S + 0 * 8)(x13) | sd s0, (PCB_S + 0 * 8)(x13) | ||||
sd s1, (PCB_S + 1 * 8)(x13) | sd s1, (PCB_S + 1 * 8)(x13) | ||||
Show All 38 Lines | ENTRY(cpu_switch) | ||||
sd a2, TD_LOCK(a0) | sd a2, TD_LOCK(a0) | ||||
#if defined(SCHED_ULE) && defined(SMP) | #if defined(SCHED_ULE) && defined(SMP) | ||||
/* TODO */ | /* TODO */ | ||||
#endif | #endif | ||||
/* Restore the registers */ | /* Restore the registers */ | ||||
ld ra, (PCB_RA)(x13) | ld ra, (PCB_RA)(x13) | ||||
ld sp, (PCB_SP)(x13) | ld sp, (PCB_SP)(x13) | ||||
ld gp, (PCB_GP)(x13) | |||||
ld tp, (PCB_TP)(x13) | |||||
/* We use these in fork_trampoline */ | /* We use these in fork_trampoline */ | ||||
ld t0, (PCB_T + 0 * 8)(x13) | ld t0, (PCB_T + 0 * 8)(x13) | ||||
ld t1, (PCB_T + 1 * 8)(x13) | ld t1, (PCB_T + 1 * 8)(x13) | ||||
/* s[0-11] */ | /* s[0-11] */ | ||||
ld s0, (PCB_S + 0 * 8)(x13) | ld s0, (PCB_S + 0 * 8)(x13) | ||||
ld s1, (PCB_S + 1 * 8)(x13) | ld s1, (PCB_S + 1 * 8)(x13) | ||||
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines | ENTRY(fork_trampoline) | ||||
ld a1, (TF_A + 1 * 8)(sp) | ld a1, (TF_A + 1 * 8)(sp) | ||||
ld a2, (TF_A + 2 * 8)(sp) | ld a2, (TF_A + 2 * 8)(sp) | ||||
ld a3, (TF_A + 3 * 8)(sp) | ld a3, (TF_A + 3 * 8)(sp) | ||||
ld a4, (TF_A + 4 * 8)(sp) | ld a4, (TF_A + 4 * 8)(sp) | ||||
ld a5, (TF_A + 5 * 8)(sp) | ld a5, (TF_A + 5 * 8)(sp) | ||||
ld a6, (TF_A + 6 * 8)(sp) | ld a6, (TF_A + 6 * 8)(sp) | ||||
ld a7, (TF_A + 7 * 8)(sp) | ld a7, (TF_A + 7 * 8)(sp) | ||||
/* Load user ra and sp */ | |||||
ld tp, (TF_TP)(sp) | |||||
ld ra, (TF_RA)(sp) | |||||
/* | |||||
* Store our pcpup on stack, we will load it back | |||||
* on kernel mode trap. | |||||
*/ | |||||
sd gp, (TF_SIZE)(sp) | |||||
ld gp, (TF_GP)(sp) | |||||
/* Save kernel stack so we can use it doing a user trap */ | /* Save kernel stack so we can use it doing a user trap */ | ||||
addi sp, sp, TF_SIZE | |||||
csrw sscratch, sp | csrw sscratch, sp | ||||
/* Load user ra and sp */ | /* Load user stack */ | ||||
ld ra, (TF_RA)(sp) | ld sp, (TF_SP - TF_SIZE)(sp) | ||||
ld sp, (TF_SP)(sp) | |||||
eret | eret | ||||
END(fork_trampoline) | END(fork_trampoline) | ||||
ENTRY(savectx) | ENTRY(savectx) | ||||
la a0, .Lsavectx_panic_str | la a0, .Lsavectx_panic_str | ||||
call panic | call panic | ||||
.Lsavectx_panic_str: | .Lsavectx_panic_str: | ||||
.asciz "savectx_panic: %p\0" | .asciz "savectx_panic: %p\0" | ||||
END(savectx) | END(savectx) |