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sys/dev/irdma/irdma_defs.h

/*- /*-
* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
* *
* Copyright (c) 2015 - 2021 Intel Corporation * Copyright (c) 2015 - 2022 Intel Corporation
* *
* This software is available to you under a choice of one of two * This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU * licenses. You may choose to be licensed under the terms of the GNU
Context not available.
#define IRDMA_PE_DB_SIZE_4M 1 #define IRDMA_PE_DB_SIZE_4M 1
#define IRDMA_PE_DB_SIZE_8M 2 #define IRDMA_PE_DB_SIZE_8M 2
#define IRDMA_DDP_VER 1
#define IRDMA_RDMAP_VER 1
#define IRDMA_RDMA_MODE_RDMAC 0
#define IRDMA_RDMA_MODE_IETF 1
#define IRDMA_STAG_STATE_INVALID 0
#define IRDMA_STAG_STATE_VALID 1
#define IRDMA_STAG_TYPE_SHARED 0
#define IRDMA_STAG_TYPE_NONSHARED 1
#define QS_HANDLE_UNKNOWN 0xffff
#define USER_PRI_UNKNOWN 0xff
#define IRDMA_INVALID_WQE_INDEX 0xffffffff
#define IRDMA_CQP_SW_SQSIZE_8 8
#define IRDMA_CQP_SW_SQSIZE_16 16
#define IRDMA_CQP_SW_SQSIZE_32 32
#define IRDMA_CQP_SW_SQSIZE_64 64
#define IRDMA_CQP_SW_SQSIZE_128 128
#define IRDMA_CQP_SW_SQSIZE_256 256
#define IRDMA_CQP_SW_SQSIZE_512 512
#define IRDMA_CQP_SW_SQSIZE_1024 1024
#define IRDMA_CQP_HW_SQSIZE_4 1
#define IRDMA_CQP_HW_SQSIZE_8 2
#define IRDMA_CQP_HW_SQSIZE_16 3
#define IRDMA_CQP_HW_SQSIZE_32 4
#define IRDMA_CQP_HW_SQSIZE_64 5
#define IRDMA_CQP_HW_SQSIZE_128 6
#define IRDMA_CQP_HW_SQSIZE_256 7
#define IRDMA_CQP_HW_SQSIZE_512 8
#define IRDMA_CQP_HW_SQSIZE_1024 9
#define IRDMA_CQP_HW_SQSIZE_2048 10
/* WQE size considering 32 bytes per WQE*/
#define IRDMAQP_SW_WQSIZE_8 8 /* 256 bytes */
#define IRDMAQP_SW_WQSIZE_16 16 /* 512 bytes */
#define IRDMAQP_SW_WQSIZE_32 32 /* 1024 bytes */
#define IRDMAQP_SW_WQSIZE_64 64 /* 2048 bytes */
#define IRDMAQP_SW_WQSIZE_128 128 /* 4096 bytes */
#define IRDMAQP_SW_WQSIZE_256 256 /* 8192 bytes */
#define IRDMAQP_SW_WQSIZE_512 512 /* 16384 bytes */
#define IRDMAQP_SW_WQSIZE_1024 1024 /* 32768 bytes */
#define IRDMAQP_SW_WQSIZE_2048 2048 /* 65536 bytes */
#define IRDMAQP_SW_WQSIZE_4096 4096 /* 131072 bytes */
#define IRDMAQP_SW_WQSIZE_8192 8192 /* 262144 bytes */
#define IRDMAQP_SW_WQSIZE_16384 16384 /* 524288 bytes */
#define IRDMAQP_SW_WQSIZE_32768 32768 /* 1048576 bytes */
#define IRDMAQP_HW_WQSIZE_8 1
#define IRDMAQP_HW_WQSIZE_16 2
#define IRDMAQP_HW_WQSIZE_32 3
#define IRDMAQP_HW_WQSIZE_64 4
#define IRDMAQP_HW_WQSIZE_128 5
#define IRDMAQP_HW_WQSIZE_256 6
#define IRDMAQP_HW_WQSIZE_512 7
#define IRDMAQP_HW_WQSIZE_1024 8
#define IRDMAQP_HW_WQSIZE_2048 9
#define IRDMAQP_HW_WQSIZE_4096 10
#define IRDMAQP_HW_WQSIZE_8192 11
#define IRDMAQP_HW_WQSIZE_16384 12
#define IRDMAQP_HW_WQSIZE_32768 13
#define IRDMA_IRD_HW_SIZE_4 0 #define IRDMA_IRD_HW_SIZE_4 0
#define IRDMA_IRD_HW_SIZE_16 1 #define IRDMA_IRD_HW_SIZE_16 1
#define IRDMA_IRD_HW_SIZE_64 2 #define IRDMA_IRD_HW_SIZE_64 2
#define IRDMA_IRD_HW_SIZE_128 3 #define IRDMA_IRD_HW_SIZE_128 3
#define IRDMA_IRD_HW_SIZE_256 4 #define IRDMA_IRD_HW_SIZE_256 4
enum irdma_protocol_used {
IRDMA_ANY_PROTOCOL = 0,
IRDMA_IWARP_PROTOCOL_ONLY = 1,
IRDMA_ROCE_PROTOCOL_ONLY = 2,
};
#define IRDMA_QP_STATE_INVALID 0 #define IRDMA_QP_STATE_INVALID 0
#define IRDMA_QP_STATE_IDLE 1 #define IRDMA_QP_STATE_IDLE 1
#define IRDMA_QP_STATE_RTS 2 #define IRDMA_QP_STATE_RTS 2
Context not available.
#define IRDMA_QP_SW_MAX_WQ_QUANTA 32768 #define IRDMA_QP_SW_MAX_WQ_QUANTA 32768
#define IRDMA_QP_SW_MAX_SQ_QUANTA 32768 #define IRDMA_QP_SW_MAX_SQ_QUANTA 32768
#define IRDMA_QP_SW_MAX_RQ_QUANTA 32768 #define IRDMA_QP_SW_MAX_RQ_QUANTA 32768
#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \ #define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \
((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr)) ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
Context not available.
#define IRDMA_CQE_QTYPE_RQ 0 #define IRDMA_CQE_QTYPE_RQ 0
#define IRDMA_CQE_QTYPE_SQ 1 #define IRDMA_CQE_QTYPE_SQ 1
#define IRDMA_QP_SW_MIN_WQSIZE 8u /* in WRs*/
#define IRDMA_QP_WQE_MIN_SIZE 32 #define IRDMA_QP_WQE_MIN_SIZE 32
#define IRDMA_QP_WQE_MAX_SIZE 256 #define IRDMA_QP_WQE_MAX_SIZE 256
#define IRDMA_QP_WQE_MIN_QUANTA 1 #define IRDMA_QP_WQE_MIN_QUANTA 1
Context not available.
#define IRDMA_SQ_RSVD 258 #define IRDMA_SQ_RSVD 258
#define IRDMA_RQ_RSVD 1 #define IRDMA_RQ_RSVD 1
#define IRDMA_FEATURE_RTS_AE 1ULL #define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
#define IRDMA_FEATURE_CQ_RESIZE 2ULL #define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
#define IRDMA_FEATURE_RELAX_RQ_ORDER 4ULL #define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2)
#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
#define IRDMAQP_OP_RDMA_WRITE 0x00 #define IRDMAQP_OP_RDMA_WRITE 0x00
#define IRDMAQP_OP_RDMA_READ 0x01 #define IRDMAQP_OP_RDMA_READ 0x01
#define IRDMAQP_OP_RDMA_SEND 0x03 #define IRDMAQP_OP_RDMA_SEND 0x03
Context not available.
IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 49, IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 49,
IRDMA_OP_CQ_MODIFY = 50, IRDMA_OP_CQ_MODIFY = 50,
/* Must be last entry*/ /* Must be last entry */
IRDMA_MAX_CQP_OPS = 51, IRDMA_MAX_CQP_OPS = 51,
}; };
Context not available.
#define IRDMA_CQP_OP_GATHER_STATS 0x2e #define IRDMA_CQP_OP_GATHER_STATS 0x2e
#define IRDMA_CQP_OP_UP_MAP 0x2f #define IRDMA_CQP_OP_UP_MAP 0x2f
/* Async Events codes */
#define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102
#define IRDMA_AE_AMP_INVALID_STAG 0x0103
#define IRDMA_AE_AMP_BAD_QP 0x0104
#define IRDMA_AE_AMP_BAD_PD 0x0105
#define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106
#define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107
#define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108
#define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109
#define IRDMA_AE_AMP_TO_WRAP 0x010a
#define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c
#define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d
#define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e
#define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110
#define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111
#define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112
#define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113
#define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114
#define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115
#define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116
#define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117
#define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118
#define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
#define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
#define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b
#define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c
#define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d
#define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e
#define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f
#define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120
#define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121
#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132
#define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133
#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134
#define IRDMA_AE_UDA_L4LEN_INVALID 0x0135
#define IRDMA_AE_BAD_CLOSE 0x0201
#define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
#define IRDMA_AE_CQ_OPERATION_ERROR 0x0203
#define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
#define IRDMA_AE_STAG_ZERO_INVALID 0x0206
#define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207
#define IRDMA_AE_IB_INVALID_REQUEST 0x0208
#define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a
#define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b
#define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c
#define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d
#define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e
#define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220
#define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
#define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
#define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
#define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305
#define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306
#define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307
#define IRDMA_AE_DDP_NO_L_BIT 0x0308
#define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311
#define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312
#define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313
#define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314
#define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316
#define IRDMA_AE_ROCE_EMPTY_MCG 0x0380
#define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381
#define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382
#define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383
#define IRDMA_AE_INVALID_ARP_ENTRY 0x0401
#define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402
#define IRDMA_AE_STALE_ARP_ENTRY 0x0403
#define IRDMA_AE_INVALID_AH_ENTRY 0x0406
#define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501
#define IRDMA_AE_LLP_CONNECTION_RESET 0x0502
#define IRDMA_AE_LLP_FIN_RECEIVED 0x0503
#define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504
#define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
#define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507
#define IRDMA_AE_LLP_SYN_RECEIVED 0x0508
#define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509
#define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a
#define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b
#define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c
#define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e
#define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520
#define IRDMA_AE_RESET_SENT 0x0601
#define IRDMA_AE_TERMINATE_SENT 0x0602
#define IRDMA_AE_RESET_NOT_SENT 0x0603
#define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700
#define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
#define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702
#define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900
#ifndef LS_64_1 #ifndef LS_64_1
#define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits)) #define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits))
#define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits)) #define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits))
#define LS_32_1(val, bits) ((u32)((val) << (bits))) #define LS_32_1(val, bits) ((u32)((val) << (bits)))
#define RS_32_1(val, bits) ((u32)((val) >> (bits))) #define RS_32_1(val, bits) ((u32)((val) >> (bits)))
#endif #endif
#define LS_64(val, field) (((u64)(val) << field ## _S) & (field ## _M)) #ifndef GENMASK_ULL
#define RS_64(val, field) ((u64)((val) & field ## _M) >> field ## _S) #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (low))
#define LS_32(val, field) (((val) << field ## _S) & (field ## _M)) #endif /* GENMASK_ULL */
#define RS_32(val, field) (((val) & field ## _M) >> field ## _S) #ifndef GENMASK
#define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
#endif /* GENMASK */
#ifndef FIELD_PREP
#define FIELD_PREP(mask, val) (((u64)(val) << mask##_S) & (mask))
#define FIELD_GET(mask, val) (((val) & mask) >> mask##_S)
#endif /* FIELD_PREP */
#define FLD_LS_64(dev, val, field) \ #define FLD_LS_64(dev, val, field) \
(((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
Context not available.
#define IRDMA_MAX_STATS_64 0xffffffffffffffffULL #define IRDMA_MAX_STATS_64 0xffffffffffffffffULL
#define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
/* ILQ CQP hash table fields */
#define IRDMA_CQPSQ_QHASH_VLANID_S 32 #define IRDMA_CQPSQ_QHASH_VLANID_S 32
#define IRDMA_CQPSQ_QHASH_VLANID_M \ #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
((u64)0xfff << IRDMA_CQPSQ_QHASH_VLANID_S)
#define IRDMA_CQPSQ_QHASH_QPN_S 32 #define IRDMA_CQPSQ_QHASH_QPN_S 32
#define IRDMA_CQPSQ_QHASH_QPN_M \ #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
((u64)0x3ffff << IRDMA_CQPSQ_QHASH_QPN_S)
#define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0 #define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0
#define IRDMA_CQPSQ_QHASH_QS_HANDLE_M ((u64)0x3ff << IRDMA_CQPSQ_QHASH_QS_HANDLE_S) #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
#define IRDMA_CQPSQ_QHASH_SRC_PORT_S 16 #define IRDMA_CQPSQ_QHASH_SRC_PORT_S 16
#define IRDMA_CQPSQ_QHASH_SRC_PORT_M \ #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
((u64)0xffff << IRDMA_CQPSQ_QHASH_SRC_PORT_S)
#define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0 #define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0
#define IRDMA_CQPSQ_QHASH_DEST_PORT_M \ #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
((u64)0xffff << IRDMA_CQPSQ_QHASH_DEST_PORT_S)
#define IRDMA_CQPSQ_QHASH_ADDR0_S 32 #define IRDMA_CQPSQ_QHASH_ADDR0_S 32
#define IRDMA_CQPSQ_QHASH_ADDR0_M \ #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
((u64)0xffffffff << IRDMA_CQPSQ_QHASH_ADDR0_S)
#define IRDMA_CQPSQ_QHASH_ADDR1_S 0 #define IRDMA_CQPSQ_QHASH_ADDR1_S 0
#define IRDMA_CQPSQ_QHASH_ADDR1_M \ #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
((u64)0xffffffff << IRDMA_CQPSQ_QHASH_ADDR1_S)
#define IRDMA_CQPSQ_QHASH_ADDR2_S 32 #define IRDMA_CQPSQ_QHASH_ADDR2_S 32
#define IRDMA_CQPSQ_QHASH_ADDR2_M \ #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
((u64)0xffffffff << IRDMA_CQPSQ_QHASH_ADDR2_S)
#define IRDMA_CQPSQ_QHASH_ADDR3_S 0 #define IRDMA_CQPSQ_QHASH_ADDR3_S 0
#define IRDMA_CQPSQ_QHASH_ADDR3_M \ #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
((u64)0xffffffff << IRDMA_CQPSQ_QHASH_ADDR3_S)
#define IRDMA_CQPSQ_QHASH_WQEVALID_S 63 #define IRDMA_CQPSQ_QHASH_WQEVALID_S 63
#define IRDMA_CQPSQ_QHASH_WQEVALID_M \ #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_QHASH_WQEVALID_S)
#define IRDMA_CQPSQ_QHASH_OPCODE_S 32 #define IRDMA_CQPSQ_QHASH_OPCODE_S 32
#define IRDMA_CQPSQ_QHASH_OPCODE_M \ #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_QHASH_OPCODE_S)
#define IRDMA_CQPSQ_QHASH_MANAGE_S 61 #define IRDMA_CQPSQ_QHASH_MANAGE_S 61
#define IRDMA_CQPSQ_QHASH_MANAGE_M \ #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
((u64)0x3 << IRDMA_CQPSQ_QHASH_MANAGE_S)
#define IRDMA_CQPSQ_QHASH_IPV4VALID_S 60 #define IRDMA_CQPSQ_QHASH_IPV4VALID_S 60
#define IRDMA_CQPSQ_QHASH_IPV4VALID_M \ #define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
BIT_ULL(IRDMA_CQPSQ_QHASH_IPV4VALID_S)
#define IRDMA_CQPSQ_QHASH_VLANVALID_S 59 #define IRDMA_CQPSQ_QHASH_VLANVALID_S 59
#define IRDMA_CQPSQ_QHASH_VLANVALID_M \ #define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
BIT_ULL(IRDMA_CQPSQ_QHASH_VLANVALID_S)
#define IRDMA_CQPSQ_QHASH_ENTRYTYPE_S 42 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE_S 42
#define IRDMA_CQPSQ_QHASH_ENTRYTYPE_M \ #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
((u64)0x7 << IRDMA_CQPSQ_QHASH_ENTRYTYPE_S)
/* Stats */
#define IRDMA_CQPSQ_STATS_WQEVALID_S 63 #define IRDMA_CQPSQ_STATS_WQEVALID_S 63
#define IRDMA_CQPSQ_STATS_WQEVALID_M \ #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_STATS_WQEVALID_S)
#define IRDMA_CQPSQ_STATS_ALLOC_INST_S 62 #define IRDMA_CQPSQ_STATS_ALLOC_INST_S 62
#define IRDMA_CQPSQ_STATS_ALLOC_INST_M \ #define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_STATS_ALLOC_INST_S)
#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S 60 #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S 60
#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_M \ #define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
BIT_ULL(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S)
#define IRDMA_CQPSQ_STATS_USE_INST_S 61 #define IRDMA_CQPSQ_STATS_USE_INST_S 61
#define IRDMA_CQPSQ_STATS_USE_INST_M \ #define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_STATS_USE_INST_S)
#define IRDMA_CQPSQ_STATS_OP_S 32 #define IRDMA_CQPSQ_STATS_OP_S 32
#define IRDMA_CQPSQ_STATS_OP_M \ #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_STATS_OP_S)
#define IRDMA_CQPSQ_STATS_INST_INDEX_S 0 #define IRDMA_CQPSQ_STATS_INST_INDEX_S 0
#define IRDMA_CQPSQ_STATS_INST_INDEX_M \ #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
((u64)0x7f << IRDMA_CQPSQ_STATS_INST_INDEX_S)
#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0
#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_M \ #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)
((u64)0x3f << IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S)
/* WS - Work Scheduler */
#define IRDMA_CQPSQ_WS_WQEVALID_S 63 #define IRDMA_CQPSQ_WS_WQEVALID_S 63
#define IRDMA_CQPSQ_WS_WQEVALID_M \ #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_WS_WQEVALID_S)
#define IRDMA_CQPSQ_WS_NODEOP_S 52 #define IRDMA_CQPSQ_WS_NODEOP_S 52
#define IRDMA_CQPSQ_WS_NODEOP_M \ #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52)
((u64)0x3 << IRDMA_CQPSQ_WS_NODEOP_S)
#define IRDMA_CQPSQ_WS_ENABLENODE_S 62 #define IRDMA_CQPSQ_WS_ENABLENODE_S 62
#define IRDMA_CQPSQ_WS_ENABLENODE_M \ #define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_WS_ENABLENODE_S)
#define IRDMA_CQPSQ_WS_NODETYPE_S 61 #define IRDMA_CQPSQ_WS_NODETYPE_S 61
#define IRDMA_CQPSQ_WS_NODETYPE_M \ #define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_WS_NODETYPE_S)
#define IRDMA_CQPSQ_WS_PRIOTYPE_S 59 #define IRDMA_CQPSQ_WS_PRIOTYPE_S 59
#define IRDMA_CQPSQ_WS_PRIOTYPE_M \ #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
((u64)0x3 << IRDMA_CQPSQ_WS_PRIOTYPE_S)
#define IRDMA_CQPSQ_WS_TC_S 56 #define IRDMA_CQPSQ_WS_TC_S 56
#define IRDMA_CQPSQ_WS_TC_M \ #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
((u64)0x7 << IRDMA_CQPSQ_WS_TC_S)
#define IRDMA_CQPSQ_WS_VMVFTYPE_S 54 #define IRDMA_CQPSQ_WS_VMVFTYPE_S 54
#define IRDMA_CQPSQ_WS_VMVFTYPE_M \ #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
((u64)0x3 << IRDMA_CQPSQ_WS_VMVFTYPE_S)
#define IRDMA_CQPSQ_WS_VMVFNUM_S 42 #define IRDMA_CQPSQ_WS_VMVFNUM_S 42
#define IRDMA_CQPSQ_WS_VMVFNUM_M \ #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
((u64)0x3ff << IRDMA_CQPSQ_WS_VMVFNUM_S)
#define IRDMA_CQPSQ_WS_OP_S 32 #define IRDMA_CQPSQ_WS_OP_S 32
#define IRDMA_CQPSQ_WS_OP_M \ #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_WS_OP_S)
#define IRDMA_CQPSQ_WS_PARENTID_S 16 #define IRDMA_CQPSQ_WS_PARENTID_S 16
#define IRDMA_CQPSQ_WS_PARENTID_M \ #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)
((u64)0x3ff << IRDMA_CQPSQ_WS_PARENTID_S)
#define IRDMA_CQPSQ_WS_NODEID_S 0 #define IRDMA_CQPSQ_WS_NODEID_S 0
#define IRDMA_CQPSQ_WS_NODEID_M \ #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
((u64)0x3ff << IRDMA_CQPSQ_WS_NODEID_S)
#define IRDMA_CQPSQ_WS_VSI_S 48 #define IRDMA_CQPSQ_WS_VSI_S 48
#define IRDMA_CQPSQ_WS_VSI_M \ #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
((u64)0x3ff << IRDMA_CQPSQ_WS_VSI_S)
#define IRDMA_CQPSQ_WS_WEIGHT_S 32 #define IRDMA_CQPSQ_WS_WEIGHT_S 32
#define IRDMA_CQPSQ_WS_WEIGHT_M \ #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
((u64)0x7f << IRDMA_CQPSQ_WS_WEIGHT_S)
/* UP to UP mapping */
#define IRDMA_CQPSQ_UP_WQEVALID_S 63 #define IRDMA_CQPSQ_UP_WQEVALID_S 63
#define IRDMA_CQPSQ_UP_WQEVALID_M \ #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_UP_WQEVALID_S)
#define IRDMA_CQPSQ_UP_USEVLAN_S 62 #define IRDMA_CQPSQ_UP_USEVLAN_S 62
#define IRDMA_CQPSQ_UP_USEVLAN_M \ #define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_UP_USEVLAN_S)
#define IRDMA_CQPSQ_UP_USEOVERRIDE_S 61 #define IRDMA_CQPSQ_UP_USEOVERRIDE_S 61
#define IRDMA_CQPSQ_UP_USEOVERRIDE_M \ #define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_UP_USEOVERRIDE_S)
#define IRDMA_CQPSQ_UP_OP_S 32 #define IRDMA_CQPSQ_UP_OP_S 32
#define IRDMA_CQPSQ_UP_OP_M \ #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_UP_OP_S)
#define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0 #define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0
#define IRDMA_CQPSQ_UP_HMCFCNIDX_M \ #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
((u64)0x3f << IRDMA_CQPSQ_UP_HMCFCNIDX_S)
#define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32 #define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32
#define IRDMA_CQPSQ_UP_CNPOVERRIDE_M \ #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_UP_CNPOVERRIDE_S)
/* Query RDMA features*/
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
((u64)0xffffffff << IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
((u64)0x3f << IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
(0xffffULL << IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S 16 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S 16
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
(0xffULL << IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_M \ #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
(0xffULL << IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S)
/* CQP Host Context */
#define IRDMA_CQPHC_SQSIZE_S 8 #define IRDMA_CQPHC_SQSIZE_S 8
#define IRDMA_CQPHC_SQSIZE_M (0xfULL << IRDMA_CQPHC_SQSIZE_S) #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
#define IRDMA_CQPHC_DISABLE_PFPDUS_S 1 #define IRDMA_CQPHC_DISABLE_PFPDUS_S 1
#define IRDMA_CQPHC_DISABLE_PFPDUS_M BIT_ULL(IRDMA_CQPHC_DISABLE_PFPDUS_S) #define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
#define IRDMA_CQPHC_ROCEV2_RTO_POLICY_S 2 #define IRDMA_CQPHC_ROCEV2_RTO_POLICY_S 2
#define IRDMA_CQPHC_ROCEV2_RTO_POLICY_M BIT_ULL(IRDMA_CQPHC_ROCEV2_RTO_POLICY_S) #define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)
#define IRDMA_CQPHC_PROTOCOL_USED_S 3 #define IRDMA_CQPHC_PROTOCOL_USED_S 3
#define IRDMA_CQPHC_PROTOCOL_USED_M (0x3ULL << IRDMA_CQPHC_PROTOCOL_USED_S) #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
#define IRDMA_CQPHC_MIN_RATE_S 48 #define IRDMA_CQPHC_MIN_RATE_S 48
#define IRDMA_CQPHC_MIN_RATE_M (0xfULL << IRDMA_CQPHC_MIN_RATE_S) #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
#define IRDMA_CQPHC_MIN_DEC_FACTOR_S 56 #define IRDMA_CQPHC_MIN_DEC_FACTOR_S 56
#define IRDMA_CQPHC_MIN_DEC_FACTOR_M (0xfULL << IRDMA_CQPHC_MIN_DEC_FACTOR_S) #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
#define IRDMA_CQPHC_DCQCN_T_S 0 #define IRDMA_CQPHC_DCQCN_T_S 0
#define IRDMA_CQPHC_DCQCN_T_M (0xffffULL << IRDMA_CQPHC_DCQCN_T_S) #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
#define IRDMA_CQPHC_HAI_FACTOR_S 32 #define IRDMA_CQPHC_HAI_FACTOR_S 32
#define IRDMA_CQPHC_HAI_FACTOR_M \ #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
(0xffffULL << IRDMA_CQPHC_HAI_FACTOR_S)
#define IRDMA_CQPHC_RAI_FACTOR_S 48 #define IRDMA_CQPHC_RAI_FACTOR_S 48
#define IRDMA_CQPHC_RAI_FACTOR_M \ #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
(0xffffULL << IRDMA_CQPHC_RAI_FACTOR_S)
#define IRDMA_CQPHC_DCQCN_B_S 0 #define IRDMA_CQPHC_DCQCN_B_S 0
#define IRDMA_CQPHC_DCQCN_B_M (0x1ffffffULL << IRDMA_CQPHC_DCQCN_B_S) #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
#define IRDMA_CQPHC_DCQCN_F_S 25 #define IRDMA_CQPHC_DCQCN_F_S 25
#define IRDMA_CQPHC_DCQCN_F_M (0x7ULL << IRDMA_CQPHC_DCQCN_F_S) #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
#define IRDMA_CQPHC_CC_CFG_VALID_S 31 #define IRDMA_CQPHC_CC_CFG_VALID_S 31
#define IRDMA_CQPHC_CC_CFG_VALID_M BIT_ULL(IRDMA_CQPHC_CC_CFG_VALID_S) #define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)
#define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32 #define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32
#define IRDMA_CQPHC_RREDUCE_MPERIOD_M \ #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_CQPHC_RREDUCE_MPERIOD_S)
#define IRDMA_CQPHC_HW_MINVER_S 0 #define IRDMA_CQPHC_HW_MINVER_S 0
#define IRDMA_CQPHC_HW_MINVER_M (0xffffULL << IRDMA_CQPHC_HW_MINVER_S) #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
#define IRDMA_CQPHC_HW_MAJVER_GEN_1 0 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
#define IRDMA_CQPHC_HW_MAJVER_GEN_2 1 #define IRDMA_CQPHC_HW_MAJVER_GEN_2 1
#define IRDMA_CQPHC_HW_MAJVER_GEN_3 2 #define IRDMA_CQPHC_HW_MAJVER_GEN_3 2
#define IRDMA_CQPHC_HW_MAJVER_S 16 #define IRDMA_CQPHC_HW_MAJVER_S 16
#define IRDMA_CQPHC_HW_MAJVER_M (0xffffULL << IRDMA_CQPHC_HW_MAJVER_S) #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
#define IRDMA_CQPHC_CEQPERVF_S 32 #define IRDMA_CQPHC_CEQPERVF_S 32
#define IRDMA_CQPHC_CEQPERVF_M (0xffULL << IRDMA_CQPHC_CEQPERVF_S) #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
#define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S 3 #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S 3
#define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_M BIT_ULL(IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S) #define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK BIT_ULL(3)
#define IRDMA_CQPHC_ENABLED_VFS_S 32 #define IRDMA_CQPHC_ENABLED_VFS_S 32
#define IRDMA_CQPHC_ENABLED_VFS_M (0x3fULL << IRDMA_CQPHC_ENABLED_VFS_S) #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
#define IRDMA_CQPHC_HMC_PROFILE_S 0 #define IRDMA_CQPHC_HMC_PROFILE_S 0
#define IRDMA_CQPHC_HMC_PROFILE_M (0x7ULL << IRDMA_CQPHC_HMC_PROFILE_S) #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
#define IRDMA_CQPHC_SVER_S 24 #define IRDMA_CQPHC_SVER_S 24
#define IRDMA_CQPHC_SVER_M (0xffULL << IRDMA_CQPHC_SVER_S) #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
#define IRDMA_CQPHC_SQBASE_S 9 #define IRDMA_CQPHC_SQBASE_S 9
#define IRDMA_CQPHC_SQBASE_M \ #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
(0xfffffffffffffeULL << IRDMA_CQPHC_SQBASE_S)
#define IRDMA_CQPHC_QPCTX_S 0 #define IRDMA_CQPHC_QPCTX_S 0
#define IRDMA_CQPHC_QPCTX_M \ #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
(0xffffffffffffffffULL << IRDMA_CQPHC_QPCTX_S)
/* iWARP QP Doorbell shadow area */
#define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
#define IRDMA_QP_DBSA_HW_SQ_TAIL_M \ #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
(0x7fffULL << IRDMA_QP_DBSA_HW_SQ_TAIL_S)
/* Completion Queue Doorbell shadow area */
#define IRDMA_CQ_DBSA_CQEIDX_S 0 #define IRDMA_CQ_DBSA_CQEIDX_S 0
#define IRDMA_CQ_DBSA_CQEIDX_M (0xfffffULL << IRDMA_CQ_DBSA_CQEIDX_S) #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
#define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
#define IRDMA_CQ_DBSA_SW_CQ_SELECT_M \ #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
(0x3fffULL << IRDMA_CQ_DBSA_SW_CQ_SELECT_S)
#define IRDMA_CQ_DBSA_ARM_NEXT_S 14 #define IRDMA_CQ_DBSA_ARM_NEXT_S 14
#define IRDMA_CQ_DBSA_ARM_NEXT_M BIT_ULL(IRDMA_CQ_DBSA_ARM_NEXT_S) #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
#define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15 #define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15
#define IRDMA_CQ_DBSA_ARM_NEXT_SE_M BIT_ULL(IRDMA_CQ_DBSA_ARM_NEXT_SE_S) #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
#define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16
#define IRDMA_CQ_DBSA_ARM_SEQ_NUM_M \ #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
(0x3ULL << IRDMA_CQ_DBSA_ARM_SEQ_NUM_S)
/* CQP and iWARP Completion Queue */ /* CQP and iWARP Completion Queue */
#define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQ_QPCTX_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX
#define IRDMA_CCQ_OPRETVAL_S 0 #define IRDMA_CCQ_OPRETVAL_S 0
#define IRDMA_CCQ_OPRETVAL_M (0xffffffffULL << IRDMA_CCQ_OPRETVAL_S) #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
#define IRDMA_CQ_MINERR_S 0 #define IRDMA_CQ_MINERR_S 0
#define IRDMA_CQ_MINERR_M (0xffffULL << IRDMA_CQ_MINERR_S) #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
#define IRDMA_CQ_MAJERR_S 16 #define IRDMA_CQ_MAJERR_S 16
#define IRDMA_CQ_MAJERR_M (0xffffULL << IRDMA_CQ_MAJERR_S) #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
#define IRDMA_CQ_WQEIDX_S 32 #define IRDMA_CQ_WQEIDX_S 32
#define IRDMA_CQ_WQEIDX_M (0x7fffULL << IRDMA_CQ_WQEIDX_S) #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
#define IRDMA_CQ_EXTCQE_S 50 #define IRDMA_CQ_EXTCQE_S 50
#define IRDMA_CQ_EXTCQE_M BIT_ULL(IRDMA_CQ_EXTCQE_S) #define IRDMA_CQ_EXTCQE BIT_ULL(50)
#define IRDMA_OOO_CMPL_S 54 #define IRDMA_OOO_CMPL_S 54
#define IRDMA_OOO_CMPL_M BIT_ULL(IRDMA_OOO_CMPL_S) #define IRDMA_OOO_CMPL BIT_ULL(54)
#define IRDMA_CQ_ERROR_S 55 #define IRDMA_CQ_ERROR_S 55
#define IRDMA_CQ_ERROR_M BIT_ULL(IRDMA_CQ_ERROR_S) #define IRDMA_CQ_ERROR BIT_ULL(55)
#define IRDMA_CQ_SQ_S 62 #define IRDMA_CQ_SQ_S 62
#define IRDMA_CQ_SQ_M BIT_ULL(IRDMA_CQ_SQ_S) #define IRDMA_CQ_SQ BIT_ULL(62)
#define IRDMA_CQ_VALID_S 63 #define IRDMA_CQ_VALID_S 63
#define IRDMA_CQ_VALID_M BIT_ULL(IRDMA_CQ_VALID_S) #define IRDMA_CQ_VALID BIT_ULL(63)
#define IRDMA_CQ_IMMVALID BIT_ULL(62)
#define IRDMA_CQ_IMMVALID_S 62
#define IRDMA_CQ_IMMVALID_M BIT_ULL(IRDMA_CQ_IMMVALID_S)
#define IRDMA_CQ_UDSMACVALID_S 61 #define IRDMA_CQ_UDSMACVALID_S 61
#define IRDMA_CQ_UDSMACVALID_M BIT_ULL(IRDMA_CQ_UDSMACVALID_S) #define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
#define IRDMA_CQ_UDVLANVALID_S 60 #define IRDMA_CQ_UDVLANVALID_S 60
#define IRDMA_CQ_UDVLANVALID_M BIT_ULL(IRDMA_CQ_UDVLANVALID_S) #define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
#define IRDMA_CQ_UDSMAC_S 0 #define IRDMA_CQ_UDSMAC_S 0
#define IRDMA_CQ_UDSMAC_M (0xffffffffffffULL << IRDMA_CQ_UDSMAC_S) #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
#define IRDMA_CQ_UDVLAN_S 48 #define IRDMA_CQ_UDVLAN_S 48
#define IRDMA_CQ_UDVLAN_M (0xffffULL << IRDMA_CQ_UDVLAN_S) #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
#define IRDMA_CQ_IMMDATA_S 0 #define IRDMA_CQ_IMMDATA_S 0
#define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S) #define IRDMA_CQ_IMMVALID_S 62
#define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62)
#define IRDMA_CQ_IMMDATALOW32_S 0 #define IRDMA_CQ_IMMDATALOW32_S 0
#define IRDMA_CQ_IMMDATALOW32_M (0xffffffffULL << IRDMA_CQ_IMMDATALOW32_S) #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
#define IRDMA_CQ_IMMDATAUP32_S 32 #define IRDMA_CQ_IMMDATAUP32_S 32
#define IRDMA_CQ_IMMDATAUP32_M (0xffffffffULL << IRDMA_CQ_IMMDATAUP32_S) #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
#define IRDMACQ_PAYLDLEN_S 0 #define IRDMACQ_PAYLDLEN_S 0
#define IRDMACQ_PAYLDLEN_M (0xffffffffULL << IRDMACQ_PAYLDLEN_S) #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
#define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32
#define IRDMACQ_TCPSEQNUMRTT_S 32 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
#define IRDMACQ_TCPSEQNUMRTT_M (0xffffffffULL << IRDMACQ_TCPSEQNUMRTT_S)
#define IRDMACQ_INVSTAG_S 0 #define IRDMACQ_INVSTAG_S 0
#define IRDMACQ_INVSTAG_M (0xffffffffULL << IRDMACQ_INVSTAG_S) #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
#define IRDMACQ_QPID_S 32 #define IRDMACQ_QPID_S 32
#define IRDMACQ_QPID_M (0xffffffULL << IRDMACQ_QPID_S) #define IRDMACQ_QPID GENMASK_ULL(55, 32)
#define IRDMACQ_UDSRCQPN_S 0 #define IRDMACQ_UDSRCQPN_S 0
#define IRDMACQ_UDSRCQPN_M (0xffffffffULL << IRDMACQ_UDSRCQPN_S) #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
#define IRDMACQ_PSHDROP_S 51 #define IRDMACQ_PSHDROP_S 51
#define IRDMACQ_PSHDROP_M BIT_ULL(IRDMACQ_PSHDROP_S) #define IRDMACQ_PSHDROP BIT_ULL(51)
#define IRDMACQ_STAG_S 53 #define IRDMACQ_STAG_S 53
#define IRDMACQ_STAG_M BIT_ULL(IRDMACQ_STAG_S) #define IRDMACQ_STAG BIT_ULL(53)
#define IRDMACQ_IPV4_S 53 #define IRDMACQ_IPV4_S 53
#define IRDMACQ_IPV4_M BIT_ULL(IRDMACQ_IPV4_S) #define IRDMACQ_IPV4 BIT_ULL(53)
#define IRDMACQ_SOEVENT_S 54 #define IRDMACQ_SOEVENT_S 54
#define IRDMACQ_SOEVENT_M BIT_ULL(IRDMACQ_SOEVENT_S) #define IRDMACQ_SOEVENT BIT_ULL(54)
#define IRDMACQ_OP_S 56 #define IRDMACQ_OP_S 56
#define IRDMACQ_OP_M (0x3fULL << IRDMACQ_OP_S) #define IRDMACQ_OP GENMASK_ULL(61, 56)
/* CEQE format */
#define IRDMA_CEQE_CQCTX_S 0 #define IRDMA_CEQE_CQCTX_S 0
#define IRDMA_CEQE_CQCTX_M \ #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
(0x7fffffffffffffffULL << IRDMA_CEQE_CQCTX_S)
#define IRDMA_CEQE_VALID_S 63 #define IRDMA_CEQE_VALID_S 63
#define IRDMA_CEQE_VALID_M BIT_ULL(IRDMA_CEQE_VALID_S) #define IRDMA_CEQE_VALID BIT_ULL(63)
/* AEQE format */ /* AEQE format */
#define IRDMA_AEQE_COMPCTX_S IRDMA_CQPHC_QPCTX_S #define IRDMA_AEQE_COMPCTX_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_AEQE_COMPCTX_M IRDMA_CQPHC_QPCTX_M #define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX
#define IRDMA_AEQE_QPCQID_LOW_S 0 #define IRDMA_AEQE_QPCQID_LOW_S 0
#define IRDMA_AEQE_QPCQID_LOW_M (0x3ffffULL << IRDMA_AEQE_QPCQID_LOW_S) #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
#define IRDMA_AEQE_QPCQID_HI_S 46 #define IRDMA_AEQE_QPCQID_HI_S 46
#define IRDMA_AEQE_QPCQID_HI_M BIT_ULL(IRDMA_AEQE_QPCQID_HI_S) #define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)
#define IRDMA_AEQE_WQDESCIDX_S 18 #define IRDMA_AEQE_WQDESCIDX_S 18
#define IRDMA_AEQE_WQDESCIDX_M (0x7fffULL << IRDMA_AEQE_WQDESCIDX_S) #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
#define IRDMA_AEQE_OVERFLOW_S 33 #define IRDMA_AEQE_OVERFLOW_S 33
#define IRDMA_AEQE_OVERFLOW_M BIT_ULL(IRDMA_AEQE_OVERFLOW_S) #define IRDMA_AEQE_OVERFLOW BIT_ULL(33)
#define IRDMA_AEQE_AECODE_S 34 #define IRDMA_AEQE_AECODE_S 34
#define IRDMA_AEQE_AECODE_M (0xfffULL << IRDMA_AEQE_AECODE_S) #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
#define IRDMA_AEQE_AESRC_S 50 #define IRDMA_AEQE_AESRC_S 50
#define IRDMA_AEQE_AESRC_M (0xfULL << IRDMA_AEQE_AESRC_S) #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
#define IRDMA_AEQE_IWSTATE_S 54 #define IRDMA_AEQE_IWSTATE_S 54
#define IRDMA_AEQE_IWSTATE_M (0x7ULL << IRDMA_AEQE_IWSTATE_S) #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
#define IRDMA_AEQE_TCPSTATE_S 57 #define IRDMA_AEQE_TCPSTATE_S 57
#define IRDMA_AEQE_TCPSTATE_M (0xfULL << IRDMA_AEQE_TCPSTATE_S) #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
#define IRDMA_AEQE_Q2DATA_S 61 #define IRDMA_AEQE_Q2DATA_S 61
#define IRDMA_AEQE_Q2DATA_M (0x3ULL << IRDMA_AEQE_Q2DATA_S) #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
#define IRDMA_AEQE_VALID_S 63 #define IRDMA_AEQE_VALID_S 63
#define IRDMA_AEQE_VALID_M BIT_ULL(IRDMA_AEQE_VALID_S) #define IRDMA_AEQE_VALID BIT_ULL(63)
#define IRDMA_UDA_QPSQ_NEXT_HDR_S 16 #define IRDMA_UDA_QPSQ_NEXT_HDR_S 16
#define IRDMA_UDA_QPSQ_NEXT_HDR_M ((u64)0xff << IRDMA_UDA_QPSQ_NEXT_HDR_S) #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
#define IRDMA_UDA_QPSQ_OPCODE_S 32 #define IRDMA_UDA_QPSQ_OPCODE_S 32
#define IRDMA_UDA_QPSQ_OPCODE_M ((u64)0x3f << IRDMA_UDA_QPSQ_OPCODE_S) #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
#define IRDMA_UDA_QPSQ_L4LEN_S 42 #define IRDMA_UDA_QPSQ_L4LEN_S 42
#define IRDMA_UDA_QPSQ_L4LEN_M ((u64)0xf << IRDMA_UDA_QPSQ_L4LEN_S) #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
#define IRDMA_GEN1_UDA_QPSQ_L4LEN_S 24 #define IRDMA_GEN1_UDA_QPSQ_L4LEN_S 24
#define IRDMA_GEN1_UDA_QPSQ_L4LEN_M ((u64)0xf << IRDMA_GEN1_UDA_QPSQ_L4LEN_S) #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
#define IRDMA_UDA_QPSQ_AHIDX_S 0 #define IRDMA_UDA_QPSQ_AHIDX_S 0
#define IRDMA_UDA_QPSQ_AHIDX_M ((u64)0x1ffff << IRDMA_UDA_QPSQ_AHIDX_S) #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
#define IRDMA_UDA_QPSQ_VALID_S 63 #define IRDMA_UDA_QPSQ_VALID_S 63
#define IRDMA_UDA_QPSQ_VALID_M \ #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
BIT_ULL(IRDMA_UDA_QPSQ_VALID_S)
#define IRDMA_UDA_QPSQ_SIGCOMPL_S 62 #define IRDMA_UDA_QPSQ_SIGCOMPL_S 62
#define IRDMA_UDA_QPSQ_SIGCOMPL_M BIT_ULL(IRDMA_UDA_QPSQ_SIGCOMPL_S) #define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)
#define IRDMA_UDA_QPSQ_MACLEN_S 56 #define IRDMA_UDA_QPSQ_MACLEN_S 56
#define IRDMA_UDA_QPSQ_MACLEN_M \ #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
((u64)0x7f << IRDMA_UDA_QPSQ_MACLEN_S)
#define IRDMA_UDA_QPSQ_IPLEN_S 48 #define IRDMA_UDA_QPSQ_IPLEN_S 48
#define IRDMA_UDA_QPSQ_IPLEN_M \ #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
((u64)0x7f << IRDMA_UDA_QPSQ_IPLEN_S)
#define IRDMA_UDA_QPSQ_L4T_S 30 #define IRDMA_UDA_QPSQ_L4T_S 30
#define IRDMA_UDA_QPSQ_L4T_M \ #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
((u64)0x3 << IRDMA_UDA_QPSQ_L4T_S)
#define IRDMA_UDA_QPSQ_IIPT_S 28 #define IRDMA_UDA_QPSQ_IIPT_S 28
#define IRDMA_UDA_QPSQ_IIPT_M \ #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
((u64)0x3 << IRDMA_UDA_QPSQ_IIPT_S)
#define IRDMA_UDA_PAYLOADLEN_S 0 #define IRDMA_UDA_PAYLOADLEN_S 0
#define IRDMA_UDA_PAYLOADLEN_M ((u64)0x3fff << IRDMA_UDA_PAYLOADLEN_S) #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
#define IRDMA_UDA_HDRLEN_S 16 #define IRDMA_UDA_HDRLEN_S 16
#define IRDMA_UDA_HDRLEN_M ((u64)0x1ff << IRDMA_UDA_HDRLEN_S) #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
#define IRDMA_VLAN_TAG_VALID_S 50 #define IRDMA_VLAN_TAG_VALID_S 50
#define IRDMA_VLAN_TAG_VALID_M BIT_ULL(IRDMA_VLAN_TAG_VALID_S) #define IRDMA_VLAN_TAG_VALID BIT_ULL(50)
#define IRDMA_UDA_L3PROTO_S 0 #define IRDMA_UDA_L3PROTO_S 0
#define IRDMA_UDA_L3PROTO_M ((u64)0x3 << IRDMA_UDA_L3PROTO_S) #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
#define IRDMA_UDA_L4PROTO_S 16 #define IRDMA_UDA_L4PROTO_S 16
#define IRDMA_UDA_L4PROTO_M ((u64)0x3 << IRDMA_UDA_L4PROTO_S) #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
#define IRDMA_UDA_QPSQ_DOLOOPBACK_S 44 #define IRDMA_UDA_QPSQ_DOLOOPBACK_S 44
#define IRDMA_UDA_QPSQ_DOLOOPBACK_M \ #define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)
BIT_ULL(IRDMA_UDA_QPSQ_DOLOOPBACK_S)
/* CQP SQ WQE common fields */
#define IRDMA_CQPSQ_BUFSIZE_S 0 #define IRDMA_CQPSQ_BUFSIZE_S 0
#define IRDMA_CQPSQ_BUFSIZE_M (0xffffffffULL << IRDMA_CQPSQ_BUFSIZE_S) #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
#define IRDMA_CQPSQ_OPCODE_S 32 #define IRDMA_CQPSQ_OPCODE_S 32
#define IRDMA_CQPSQ_OPCODE_M (0x3fULL << IRDMA_CQPSQ_OPCODE_S) #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
#define IRDMA_CQPSQ_WQEVALID_S 63 #define IRDMA_CQPSQ_WQEVALID_S 63
#define IRDMA_CQPSQ_WQEVALID_M BIT_ULL(IRDMA_CQPSQ_WQEVALID_S) #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_TPHVAL_S 0 #define IRDMA_CQPSQ_TPHVAL_S 0
#define IRDMA_CQPSQ_TPHVAL_M (0xffULL << IRDMA_CQPSQ_TPHVAL_S) #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
#define IRDMA_CQPSQ_VSIIDX_S 8 #define IRDMA_CQPSQ_VSIIDX_S 8
#define IRDMA_CQPSQ_VSIIDX_M (0x3ffULL << IRDMA_CQPSQ_VSIIDX_S) #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)
#define IRDMA_CQPSQ_TPHEN_S 60 #define IRDMA_CQPSQ_TPHEN_S 60
#define IRDMA_CQPSQ_TPHEN_M BIT_ULL(IRDMA_CQPSQ_TPHEN_S) #define IRDMA_CQPSQ_TPHEN BIT_ULL(60)
#define IRDMA_CQPSQ_PBUFADDR_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_PBUFADDR_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_PBUFADDR_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX
/* Create/Modify/Destroy QP */ /* Create/Modify/Destroy QP */
#define IRDMA_CQPSQ_QP_NEWMSS_S 32 #define IRDMA_CQPSQ_QP_NEWMSS_S 32
#define IRDMA_CQPSQ_QP_NEWMSS_M (0x3fffULL << IRDMA_CQPSQ_QP_NEWMSS_S) #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
#define IRDMA_CQPSQ_QP_TERMLEN_S 48 #define IRDMA_CQPSQ_QP_TERMLEN_S 48
#define IRDMA_CQPSQ_QP_TERMLEN_M (0xfULL << IRDMA_CQPSQ_QP_TERMLEN_S) #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
#define IRDMA_CQPSQ_QP_QPCTX_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_QP_QPCTX_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_QP_QPCTX_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX
#define IRDMA_CQPSQ_QP_QPID_S 0 #define IRDMA_CQPSQ_QP_QPID_S 0
#define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL) #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
#define IRDMA_CQPSQ_QP_OP_S 32 #define IRDMA_CQPSQ_QP_OP_S 32
#define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M #define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M
#define IRDMA_CQPSQ_QP_ORDVALID_S 42 #define IRDMA_CQPSQ_QP_ORDVALID_S 42
#define IRDMA_CQPSQ_QP_ORDVALID_M BIT_ULL(IRDMA_CQPSQ_QP_ORDVALID_S) #define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)
#define IRDMA_CQPSQ_QP_TOECTXVALID_S 43 #define IRDMA_CQPSQ_QP_TOECTXVALID_S 43
#define IRDMA_CQPSQ_QP_TOECTXVALID_M \ #define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)
BIT_ULL(IRDMA_CQPSQ_QP_TOECTXVALID_S)
#define IRDMA_CQPSQ_QP_CACHEDVARVALID_S 44 #define IRDMA_CQPSQ_QP_CACHEDVARVALID_S 44
#define IRDMA_CQPSQ_QP_CACHEDVARVALID_M \ #define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)
BIT_ULL(IRDMA_CQPSQ_QP_CACHEDVARVALID_S)
#define IRDMA_CQPSQ_QP_VQ_S 45 #define IRDMA_CQPSQ_QP_VQ_S 45
#define IRDMA_CQPSQ_QP_VQ_M BIT_ULL(IRDMA_CQPSQ_QP_VQ_S) #define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)
#define IRDMA_CQPSQ_QP_FORCELOOPBACK_S 46 #define IRDMA_CQPSQ_QP_FORCELOOPBACK_S 46
#define IRDMA_CQPSQ_QP_FORCELOOPBACK_M \ #define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)
BIT_ULL(IRDMA_CQPSQ_QP_FORCELOOPBACK_S)
#define IRDMA_CQPSQ_QP_CQNUMVALID_S 47 #define IRDMA_CQPSQ_QP_CQNUMVALID_S 47
#define IRDMA_CQPSQ_QP_CQNUMVALID_M \ #define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
BIT_ULL(IRDMA_CQPSQ_QP_CQNUMVALID_S)
#define IRDMA_CQPSQ_QP_QPTYPE_S 48 #define IRDMA_CQPSQ_QP_QPTYPE_S 48
#define IRDMA_CQPSQ_QP_QPTYPE_M (0x7ULL << IRDMA_CQPSQ_QP_QPTYPE_S) #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
#define IRDMA_CQPSQ_QP_MACVALID_S 51 #define IRDMA_CQPSQ_QP_MACVALID_S 51
#define IRDMA_CQPSQ_QP_MACVALID_M BIT_ULL(IRDMA_CQPSQ_QP_MACVALID_S) #define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)
#define IRDMA_CQPSQ_QP_MSSCHANGE_S 52 #define IRDMA_CQPSQ_QP_MSSCHANGE_S 52
#define IRDMA_CQPSQ_QP_MSSCHANGE_M BIT_ULL(IRDMA_CQPSQ_QP_MSSCHANGE_S) #define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)
#define IRDMA_CQPSQ_QP_IGNOREMWBOUND_S 54 #define IRDMA_CQPSQ_QP_IGNOREMWBOUND_S 54
#define IRDMA_CQPSQ_QP_IGNOREMWBOUND_M \ #define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)
BIT_ULL(IRDMA_CQPSQ_QP_IGNOREMWBOUND_S)
#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S 55 #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S 55
#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_M \ #define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)
BIT_ULL(IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S)
#define IRDMA_CQPSQ_QP_TERMACT_S 56 #define IRDMA_CQPSQ_QP_TERMACT_S 56
#define IRDMA_CQPSQ_QP_TERMACT_M (0x3ULL << IRDMA_CQPSQ_QP_TERMACT_S) #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
#define IRDMA_CQPSQ_QP_RESETCON_S 58 #define IRDMA_CQPSQ_QP_RESETCON_S 58
#define IRDMA_CQPSQ_QP_RESETCON_M BIT_ULL(IRDMA_CQPSQ_QP_RESETCON_S) #define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)
#define IRDMA_CQPSQ_QP_ARPTABIDXVALID_S 59 #define IRDMA_CQPSQ_QP_ARPTABIDXVALID_S 59
#define IRDMA_CQPSQ_QP_ARPTABIDXVALID_M \ #define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)
BIT_ULL(IRDMA_CQPSQ_QP_ARPTABIDXVALID_S)
#define IRDMA_CQPSQ_QP_NEXTIWSTATE_S 60 #define IRDMA_CQPSQ_QP_NEXTIWSTATE_S 60
#define IRDMA_CQPSQ_QP_NEXTIWSTATE_M \ #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
(0x7ULL << IRDMA_CQPSQ_QP_NEXTIWSTATE_S)
#define IRDMA_CQPSQ_QP_DBSHADOWADDR_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_QP_DBSHADOWADDR_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_QP_DBSHADOWADDR_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX
/* Create/Modify/Destroy CQ */
#define IRDMA_CQPSQ_CQ_CQSIZE_S 0 #define IRDMA_CQPSQ_CQ_CQSIZE_S 0
#define IRDMA_CQPSQ_CQ_CQSIZE_M (0x1fffffULL << IRDMA_CQPSQ_CQ_CQSIZE_S) #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
#define IRDMA_CQPSQ_CQ_CQCTX_S 0 #define IRDMA_CQPSQ_CQ_CQCTX_S 0
#define IRDMA_CQPSQ_CQ_CQCTX_M \ #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
(0x7fffffffffffffffULL << IRDMA_CQPSQ_CQ_CQCTX_S)
#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0
#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_M \ #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
(0x3ffff << IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S)
#define IRDMA_CQPSQ_CQ_OP_S 32 #define IRDMA_CQPSQ_CQ_OP_S 32
#define IRDMA_CQPSQ_CQ_OP_M (0x3fULL << IRDMA_CQPSQ_CQ_OP_S) #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
#define IRDMA_CQPSQ_CQ_CQRESIZE_S 43 #define IRDMA_CQPSQ_CQ_CQRESIZE_S 43
#define IRDMA_CQPSQ_CQ_CQRESIZE_M BIT_ULL(IRDMA_CQPSQ_CQ_CQRESIZE_S) #define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)
#define IRDMA_CQPSQ_CQ_LPBLSIZE_S 44 #define IRDMA_CQPSQ_CQ_LPBLSIZE_S 44
#define IRDMA_CQPSQ_CQ_LPBLSIZE_M (3ULL << IRDMA_CQPSQ_CQ_LPBLSIZE_S) #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
#define IRDMA_CQPSQ_CQ_CHKOVERFLOW_S 46 #define IRDMA_CQPSQ_CQ_CHKOVERFLOW_S 46
#define IRDMA_CQPSQ_CQ_CHKOVERFLOW_M \ #define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)
BIT_ULL(IRDMA_CQPSQ_CQ_CHKOVERFLOW_S)
#define IRDMA_CQPSQ_CQ_VIRTMAP_S 47 #define IRDMA_CQPSQ_CQ_VIRTMAP_S 47
#define IRDMA_CQPSQ_CQ_VIRTMAP_M BIT_ULL(IRDMA_CQPSQ_CQ_VIRTMAP_S) #define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
#define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48 #define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48
#define IRDMA_CQPSQ_CQ_ENCEQEMASK_M \ #define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
BIT_ULL(IRDMA_CQPSQ_CQ_ENCEQEMASK_S)
#define IRDMA_CQPSQ_CQ_CEQIDVALID_S 49 #define IRDMA_CQPSQ_CQ_CEQIDVALID_S 49
#define IRDMA_CQPSQ_CQ_CEQIDVALID_M \ #define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)
BIT_ULL(IRDMA_CQPSQ_CQ_CEQIDVALID_S)
#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S 61 #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S 61
#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_M \ #define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S)
#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0
#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_M \ #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
(0xfffffffULL << IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S)
/* Allocate/Register/Register Shared/Deallocate Stag */ /* Allocate/Register/Register Shared/Deallocate Stag */
#define IRDMA_CQPSQ_STAG_VA_FBO_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_STAG_VA_FBO_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_STAG_VA_FBO_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX
#define IRDMA_CQPSQ_STAG_STAGLEN_S 0 #define IRDMA_CQPSQ_STAG_STAGLEN_S 0
#define IRDMA_CQPSQ_STAG_STAGLEN_M \ #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
(0x3fffffffffffULL << IRDMA_CQPSQ_STAG_STAGLEN_S)
#define IRDMA_CQPSQ_STAG_KEY_S 0 #define IRDMA_CQPSQ_STAG_KEY_S 0
#define IRDMA_CQPSQ_STAG_KEY_M (0xffULL << IRDMA_CQPSQ_STAG_KEY_S) #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
#define IRDMA_CQPSQ_STAG_IDX_S 8 #define IRDMA_CQPSQ_STAG_IDX_S 8
#define IRDMA_CQPSQ_STAG_IDX_M (0xffffffULL << IRDMA_CQPSQ_STAG_IDX_S) #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32
#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_M \ #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
(0xffffffULL << IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S)
#define IRDMA_CQPSQ_STAG_MR_S 43 #define IRDMA_CQPSQ_STAG_MR_S 43
#define IRDMA_CQPSQ_STAG_MR_M BIT_ULL(IRDMA_CQPSQ_STAG_MR_S) #define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)
#define IRDMA_CQPSQ_STAG_MWTYPE_S 42 #define IRDMA_CQPSQ_STAG_MWTYPE_S 42
#define IRDMA_CQPSQ_STAG_MWTYPE_M BIT_ULL(IRDMA_CQPSQ_STAG_MWTYPE_S) #define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)
#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S 58 #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S 58
#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_M \ #define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)
BIT_ULL(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S)
#define IRDMA_CQPSQ_STAG_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S #define IRDMA_CQPSQ_STAG_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
#define IRDMA_CQPSQ_STAG_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M #define IRDMA_CQPSQ_STAG_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
#define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
#define IRDMA_CQPSQ_STAG_HPAGESIZE_S 46 #define IRDMA_CQPSQ_STAG_HPAGESIZE_S 46
#define IRDMA_CQPSQ_STAG_HPAGESIZE_M \ #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
((u64)3 << IRDMA_CQPSQ_STAG_HPAGESIZE_S)
#define IRDMA_CQPSQ_STAG_ARIGHTS_S 48 #define IRDMA_CQPSQ_STAG_ARIGHTS_S 48
#define IRDMA_CQPSQ_STAG_ARIGHTS_M \ #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
(0x1fULL << IRDMA_CQPSQ_STAG_ARIGHTS_S)
#define IRDMA_CQPSQ_STAG_REMACCENABLED_S 53 #define IRDMA_CQPSQ_STAG_REMACCENABLED_S 53
#define IRDMA_CQPSQ_STAG_REMACCENABLED_M \ #define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)
BIT_ULL(IRDMA_CQPSQ_STAG_REMACCENABLED_S)
#define IRDMA_CQPSQ_STAG_VABASEDTO_S 59 #define IRDMA_CQPSQ_STAG_VABASEDTO_S 59
#define IRDMA_CQPSQ_STAG_VABASEDTO_M \ #define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)
BIT_ULL(IRDMA_CQPSQ_STAG_VABASEDTO_S)
#define IRDMA_CQPSQ_STAG_USEHMCFNIDX_S 60 #define IRDMA_CQPSQ_STAG_USEHMCFNIDX_S 60
#define IRDMA_CQPSQ_STAG_USEHMCFNIDX_M \ #define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)
BIT_ULL(IRDMA_CQPSQ_STAG_USEHMCFNIDX_S)
#define IRDMA_CQPSQ_STAG_USEPFRID_S 61 #define IRDMA_CQPSQ_STAG_USEPFRID_S 61
#define IRDMA_CQPSQ_STAG_USEPFRID_M \ #define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_STAG_USEPFRID_S)
#define IRDMA_CQPSQ_STAG_PBA_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_STAG_PBA_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_STAG_PBA_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX
#define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0 #define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0
#define IRDMA_CQPSQ_STAG_HMCFNIDX_M \ #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
(0x3fULL << IRDMA_CQPSQ_STAG_HMCFNIDX_S)
#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0
#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_M \ #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
(0xfffffffULL << IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S)
#define IRDMA_CQPSQ_QUERYSTAG_IDX_S IRDMA_CQPSQ_STAG_IDX_S #define IRDMA_CQPSQ_QUERYSTAG_IDX_S IRDMA_CQPSQ_STAG_IDX_S
#define IRDMA_CQPSQ_QUERYSTAG_IDX_M IRDMA_CQPSQ_STAG_IDX_M #define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX
/* Manage Local MAC Table - MLM */
#define IRDMA_CQPSQ_MLM_TABLEIDX_S 0 #define IRDMA_CQPSQ_MLM_TABLEIDX_S 0
#define IRDMA_CQPSQ_MLM_TABLEIDX_M \ #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
(0x3fULL << IRDMA_CQPSQ_MLM_TABLEIDX_S)
#define IRDMA_CQPSQ_MLM_FREEENTRY_S 62 #define IRDMA_CQPSQ_MLM_FREEENTRY_S 62
#define IRDMA_CQPSQ_MLM_FREEENTRY_M \ #define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_MLM_FREEENTRY_S)
#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S 61 #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S 61
#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_M \ #define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S)
#define IRDMA_CQPSQ_MLM_MAC0_S 0 #define IRDMA_CQPSQ_MLM_MAC0_S 0
#define IRDMA_CQPSQ_MLM_MAC0_M (0xffULL << IRDMA_CQPSQ_MLM_MAC0_S) #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
#define IRDMA_CQPSQ_MLM_MAC1_S 8 #define IRDMA_CQPSQ_MLM_MAC1_S 8
#define IRDMA_CQPSQ_MLM_MAC1_M (0xffULL << IRDMA_CQPSQ_MLM_MAC1_S) #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
#define IRDMA_CQPSQ_MLM_MAC2_S 16 #define IRDMA_CQPSQ_MLM_MAC2_S 16
#define IRDMA_CQPSQ_MLM_MAC2_M (0xffULL << IRDMA_CQPSQ_MLM_MAC2_S) #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
#define IRDMA_CQPSQ_MLM_MAC3_S 24 #define IRDMA_CQPSQ_MLM_MAC3_S 24
#define IRDMA_CQPSQ_MLM_MAC3_M (0xffULL << IRDMA_CQPSQ_MLM_MAC3_S) #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
#define IRDMA_CQPSQ_MLM_MAC4_S 32 #define IRDMA_CQPSQ_MLM_MAC4_S 32
#define IRDMA_CQPSQ_MLM_MAC4_M (0xffULL << IRDMA_CQPSQ_MLM_MAC4_S) #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
#define IRDMA_CQPSQ_MLM_MAC5_S 40 #define IRDMA_CQPSQ_MLM_MAC5_S 40
#define IRDMA_CQPSQ_MLM_MAC5_M (0xffULL << IRDMA_CQPSQ_MLM_MAC5_S) #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
/* Manage ARP Table - MAT */
#define IRDMA_CQPSQ_MAT_REACHMAX_S 0 #define IRDMA_CQPSQ_MAT_REACHMAX_S 0
#define IRDMA_CQPSQ_MAT_REACHMAX_M \ #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMA_CQPSQ_MAT_REACHMAX_S)
#define IRDMA_CQPSQ_MAT_MACADDR_S 0 #define IRDMA_CQPSQ_MAT_MACADDR_S 0
#define IRDMA_CQPSQ_MAT_MACADDR_M \ #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
(0xffffffffffffULL << IRDMA_CQPSQ_MAT_MACADDR_S)
#define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0
#define IRDMA_CQPSQ_MAT_ARPENTRYIDX_M \ #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
(0xfffULL << IRDMA_CQPSQ_MAT_ARPENTRYIDX_S)
#define IRDMA_CQPSQ_MAT_ENTRYVALID_S 42 #define IRDMA_CQPSQ_MAT_ENTRYVALID_S 42
#define IRDMA_CQPSQ_MAT_ENTRYVALID_M \ #define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)
BIT_ULL(IRDMA_CQPSQ_MAT_ENTRYVALID_S)
#define IRDMA_CQPSQ_MAT_PERMANENT_S 43 #define IRDMA_CQPSQ_MAT_PERMANENT_S 43
#define IRDMA_CQPSQ_MAT_PERMANENT_M \ #define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)
BIT_ULL(IRDMA_CQPSQ_MAT_PERMANENT_S)
#define IRDMA_CQPSQ_MAT_QUERY_S 44 #define IRDMA_CQPSQ_MAT_QUERY_S 44
#define IRDMA_CQPSQ_MAT_QUERY_M BIT_ULL(IRDMA_CQPSQ_MAT_QUERY_S) #define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)
/* Manage VF PBLE Backing Pages - MVPBP*/
#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0
#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_M \ #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
(0x3ffULL << IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S)
#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S 16 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S 16
#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_M \ #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
(0x1ffULL << IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S)
#define IRDMA_CQPSQ_MVPBP_SD_INX_S 32 #define IRDMA_CQPSQ_MVPBP_SD_INX_S 32
#define IRDMA_CQPSQ_MVPBP_SD_INX_M \ #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
(0xfffULL << IRDMA_CQPSQ_MVPBP_SD_INX_S)
#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S 62 #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S 62
#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_M \ #define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S)
#define IRDMA_CQPSQ_MVPBP_PD_PLPBA_S 3 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA_S 3
#define IRDMA_CQPSQ_MVPBP_PD_PLPBA_M \ #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
(0x1fffffffffffffffULL << IRDMA_CQPSQ_MVPBP_PD_PLPBA_S)
/* Manage Push Page - MPP */ /* Manage Push Page - MPP */
#define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
#define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
#define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0 #define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0
#define IRDMA_CQPSQ_MPP_QS_HANDLE_M \ #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
(0x3ffULL << IRDMA_CQPSQ_MPP_QS_HANDLE_S)
#define IRDMA_CQPSQ_MPP_PPIDX_S 0 #define IRDMA_CQPSQ_MPP_PPIDX_S 0
#define IRDMA_CQPSQ_MPP_PPIDX_M (0x3ffULL << IRDMA_CQPSQ_MPP_PPIDX_S) #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
#define IRDMA_CQPSQ_MPP_PPTYPE_S 60 #define IRDMA_CQPSQ_MPP_PPTYPE_S 60
#define IRDMA_CQPSQ_MPP_PPTYPE_M (0x3ULL << IRDMA_CQPSQ_MPP_PPTYPE_S) #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
#define IRDMA_CQPSQ_MPP_FREE_PAGE_S 62 #define IRDMA_CQPSQ_MPP_FREE_PAGE_S 62
#define IRDMA_CQPSQ_MPP_FREE_PAGE_M BIT_ULL(IRDMA_CQPSQ_MPP_FREE_PAGE_S) #define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)
/* Upload Context - UCTX */ /* Upload Context - UCTX */
#define IRDMA_CQPSQ_UCTX_QPCTXADDR_S IRDMA_CQPHC_QPCTX_S #define IRDMA_CQPSQ_UCTX_QPCTXADDR_S IRDMA_CQPHC_QPCTX_S
#define IRDMA_CQPSQ_UCTX_QPCTXADDR_M IRDMA_CQPHC_QPCTX_M #define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX
#define IRDMA_CQPSQ_UCTX_QPID_S 0 #define IRDMA_CQPSQ_UCTX_QPID_S 0
#define IRDMA_CQPSQ_UCTX_QPID_M (0xffffffULL << IRDMA_CQPSQ_UCTX_QPID_S) #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
#define IRDMA_CQPSQ_UCTX_QPTYPE_S 48 #define IRDMA_CQPSQ_UCTX_QPTYPE_S 48
#define IRDMA_CQPSQ_UCTX_QPTYPE_M (0xfULL << IRDMA_CQPSQ_UCTX_QPTYPE_S) #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
#define IRDMA_CQPSQ_UCTX_RAWFORMAT_S 61 #define IRDMA_CQPSQ_UCTX_RAWFORMAT_S 61
#define IRDMA_CQPSQ_UCTX_RAWFORMAT_M \ #define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)
BIT_ULL(IRDMA_CQPSQ_UCTX_RAWFORMAT_S)
#define IRDMA_CQPSQ_UCTX_FREEZEQP_S 62 #define IRDMA_CQPSQ_UCTX_FREEZEQP_S 62
#define IRDMA_CQPSQ_UCTX_FREEZEQP_M \ #define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_UCTX_FREEZEQP_S)
/* Manage HMC PM Function Table - MHMC */
#define IRDMA_CQPSQ_MHMC_VFIDX_S 0 #define IRDMA_CQPSQ_MHMC_VFIDX_S 0
#define IRDMA_CQPSQ_MHMC_VFIDX_M (0xffffULL << IRDMA_CQPSQ_MHMC_VFIDX_S) #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
#define IRDMA_CQPSQ_MHMC_FREEPMFN_S 62 #define IRDMA_CQPSQ_MHMC_FREEPMFN_S 62
#define IRDMA_CQPSQ_MHMC_FREEPMFN_M \ #define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)
BIT_ULL(IRDMA_CQPSQ_MHMC_FREEPMFN_S)
/* Set HMC Resource Profile - SHMCRP */
#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0
#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_M \ #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
(0x7ULL << IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S)
#define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32 #define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32
#define IRDMA_CQPSQ_SHMCRP_VFNUM_M (0x3fULL << IRDMA_CQPSQ_SHMCRP_VFNUM_S) #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
/* Create/Destroy CEQ */
#define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0 #define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0
#define IRDMA_CQPSQ_CEQ_CEQSIZE_M \ #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
(0x3fffffULL << IRDMA_CQPSQ_CEQ_CEQSIZE_S)
#define IRDMA_CQPSQ_CEQ_CEQID_S 0 #define IRDMA_CQPSQ_CEQ_CEQID_S 0
#define IRDMA_CQPSQ_CEQ_CEQID_M (0x3ffULL << IRDMA_CQPSQ_CEQ_CEQID_S) #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
#define IRDMA_CQPSQ_CEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S #define IRDMA_CQPSQ_CEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
#define IRDMA_CQPSQ_CEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M #define IRDMA_CQPSQ_CEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
#define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
#define IRDMA_CQPSQ_CEQ_VMAP_S 47 #define IRDMA_CQPSQ_CEQ_VMAP_S 47
#define IRDMA_CQPSQ_CEQ_VMAP_M BIT_ULL(IRDMA_CQPSQ_CEQ_VMAP_S) #define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S 46 #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S 46
#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_M BIT_ULL(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S) #define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)
#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0
#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_M \ #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
(0xfffffffULL << IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S)
/* Create/Destroy AEQ */
#define IRDMA_CQPSQ_AEQ_AEQECNT_S 0 #define IRDMA_CQPSQ_AEQ_AEQECNT_S 0
#define IRDMA_CQPSQ_AEQ_AEQECNT_M \ #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
(0x7ffffULL << IRDMA_CQPSQ_AEQ_AEQECNT_S)
#define IRDMA_CQPSQ_AEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S #define IRDMA_CQPSQ_AEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S
#define IRDMA_CQPSQ_AEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M #define IRDMA_CQPSQ_AEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M
#define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE
#define IRDMA_CQPSQ_AEQ_VMAP_S 47 #define IRDMA_CQPSQ_AEQ_VMAP_S 47
#define IRDMA_CQPSQ_AEQ_VMAP_M BIT_ULL(IRDMA_CQPSQ_AEQ_VMAP_S) #define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0
#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_M \ #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
(0xfffffffULL << IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S)
/* Commit FPM Values - CFPM */
#define IRDMA_COMMIT_FPM_QPCNT_S 0 #define IRDMA_COMMIT_FPM_QPCNT_S 0
#define IRDMA_COMMIT_FPM_QPCNT_M (0x7ffffULL << IRDMA_COMMIT_FPM_QPCNT_S) #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
#define IRDMA_COMMIT_FPM_BASE_S 32 #define IRDMA_COMMIT_FPM_BASE_S 32
#define IRDMA_CQPSQ_CFPM_HMCFNID_S 0 #define IRDMA_CQPSQ_CFPM_HMCFNID_S 0
#define IRDMA_CQPSQ_CFPM_HMCFNID_M (0x3fULL << IRDMA_CQPSQ_CFPM_HMCFNID_S) #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
/* Flush WQEs - FWQE */
#define IRDMA_CQPSQ_FWQE_AECODE_S 0 #define IRDMA_CQPSQ_FWQE_AECODE_S 0
#define IRDMA_CQPSQ_FWQE_AECODE_M (0xffffULL << IRDMA_CQPSQ_FWQE_AECODE_S) #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
#define IRDMA_CQPSQ_FWQE_AESOURCE_S 16 #define IRDMA_CQPSQ_FWQE_AESOURCE_S 16
#define IRDMA_CQPSQ_FWQE_AESOURCE_M \ #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
(0xfULL << IRDMA_CQPSQ_FWQE_AESOURCE_S)
#define IRDMA_CQPSQ_FWQE_RQMNERR_S 0 #define IRDMA_CQPSQ_FWQE_RQMNERR_S 0
#define IRDMA_CQPSQ_FWQE_RQMNERR_M \ #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
(0xffffULL << IRDMA_CQPSQ_FWQE_RQMNERR_S)
#define IRDMA_CQPSQ_FWQE_RQMJERR_S 16 #define IRDMA_CQPSQ_FWQE_RQMJERR_S 16
#define IRDMA_CQPSQ_FWQE_RQMJERR_M \ #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
(0xffffULL << IRDMA_CQPSQ_FWQE_RQMJERR_S)
#define IRDMA_CQPSQ_FWQE_SQMNERR_S 32 #define IRDMA_CQPSQ_FWQE_SQMNERR_S 32
#define IRDMA_CQPSQ_FWQE_SQMNERR_M \ #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
(0xffffULL << IRDMA_CQPSQ_FWQE_SQMNERR_S)
#define IRDMA_CQPSQ_FWQE_SQMJERR_S 48 #define IRDMA_CQPSQ_FWQE_SQMJERR_S 48
#define IRDMA_CQPSQ_FWQE_SQMJERR_M \ #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
(0xffffULL << IRDMA_CQPSQ_FWQE_SQMJERR_S)
#define IRDMA_CQPSQ_FWQE_QPID_S 0 #define IRDMA_CQPSQ_FWQE_QPID_S 0
#define IRDMA_CQPSQ_FWQE_QPID_M (0xffffffULL << IRDMA_CQPSQ_FWQE_QPID_S) #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
#define IRDMA_CQPSQ_FWQE_GENERATE_AE_S 59 #define IRDMA_CQPSQ_FWQE_GENERATE_AE_S 59
#define IRDMA_CQPSQ_FWQE_GENERATE_AE_M \ #define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)
BIT_ULL(IRDMA_CQPSQ_FWQE_GENERATE_AE_S)
#define IRDMA_CQPSQ_FWQE_USERFLCODE_S 60 #define IRDMA_CQPSQ_FWQE_USERFLCODE_S 60
#define IRDMA_CQPSQ_FWQE_USERFLCODE_M \ #define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)
BIT_ULL(IRDMA_CQPSQ_FWQE_USERFLCODE_S)
#define IRDMA_CQPSQ_FWQE_FLUSHSQ_S 61 #define IRDMA_CQPSQ_FWQE_FLUSHSQ_S 61
#define IRDMA_CQPSQ_FWQE_FLUSHSQ_M BIT_ULL(IRDMA_CQPSQ_FWQE_FLUSHSQ_S) #define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)
#define IRDMA_CQPSQ_FWQE_FLUSHRQ_S 62 #define IRDMA_CQPSQ_FWQE_FLUSHRQ_S 62
#define IRDMA_CQPSQ_FWQE_FLUSHRQ_M BIT_ULL(IRDMA_CQPSQ_FWQE_FLUSHRQ_S) #define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)
/* Manage Accelerated Port Table - MAPT */
#define IRDMA_CQPSQ_MAPT_PORT_S 0 #define IRDMA_CQPSQ_MAPT_PORT_S 0
#define IRDMA_CQPSQ_MAPT_PORT_M (0xffffULL << IRDMA_CQPSQ_MAPT_PORT_S) #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
#define IRDMA_CQPSQ_MAPT_ADDPORT_S 62 #define IRDMA_CQPSQ_MAPT_ADDPORT_S 62
#define IRDMA_CQPSQ_MAPT_ADDPORT_M BIT_ULL(IRDMA_CQPSQ_MAPT_ADDPORT_S) #define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)
/* Update Protocol Engine SDs */
#define IRDMA_CQPSQ_UPESD_SDCMD_S 0 #define IRDMA_CQPSQ_UPESD_SDCMD_S 0
#define IRDMA_CQPSQ_UPESD_SDCMD_M (0xffffffffULL << IRDMA_CQPSQ_UPESD_SDCMD_S) #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
#define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0 #define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0
#define IRDMA_CQPSQ_UPESD_SDDATALOW_M \ #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMA_CQPSQ_UPESD_SDDATALOW_S)
#define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32 #define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32
#define IRDMA_CQPSQ_UPESD_SDDATAHI_M \ #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_CQPSQ_UPESD_SDDATAHI_S)
#define IRDMA_CQPSQ_UPESD_HMCFNID_S 0
#define IRDMA_CQPSQ_UPESD_HMCFNID_M \
(0x3fULL << IRDMA_CQPSQ_UPESD_HMCFNID_S)
#define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63
#define IRDMA_CQPSQ_UPESD_ENTRY_VALID_M \ #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
BIT_ULL(IRDMA_CQPSQ_UPESD_ENTRY_VALID_S)
#define IRDMA_CQPSQ_UPESD_BM_PF 0 #define IRDMA_CQPSQ_UPESD_BM_PF 0
#define IRDMA_CQPSQ_UPESD_BM_CP_LM 1 #define IRDMA_CQPSQ_UPESD_BM_CP_LM 1
#define IRDMA_CQPSQ_UPESD_BM_AXF 2 #define IRDMA_CQPSQ_UPESD_BM_AXF 2
#define IRDMA_CQPSQ_UPESD_BM_LM 4 #define IRDMA_CQPSQ_UPESD_BM_LM 4
#define IRDMA_CQPSQ_UPESD_BM_S 32 #define IRDMA_CQPSQ_UPESD_BM_S 32
#define IRDMA_CQPSQ_UPESD_BM_M \ #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
(0x7ULL << IRDMA_CQPSQ_UPESD_BM_S)
#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0
#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_M \ #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
(0xfULL << IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S)
#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S 7 #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S 7
#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_M \ #define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)
BIT_ULL(IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S)
/* Suspend QP */ /* Suspend QP */
#define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0 #define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0
#define IRDMA_CQPSQ_SUSPENDQP_QPID_M (0xFFFFFFULL) #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
/* Resume QP */
#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0
#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_M \ #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S)
#define IRDMA_CQPSQ_RESUMEQP_QPID_S 0 #define IRDMA_CQPSQ_RESUMEQP_QPID_S IRDMA_CQPSQ_SUSPENDQP_QPID_S
#define IRDMA_CQPSQ_RESUMEQP_QPID_M (0xFFFFFFUL) #define IRDMA_CQPSQ_RESUMEQP_QPID_M IRDMA_CQPSQ_SUSPENDQP_QPID_M
#define IRDMA_CQPSQ_RESUMEQP_QPID IRDMA_CQPSQ_SUSPENDQP_QPID
#define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
#define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
Context not available.
#define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
#define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
#define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
/* IW QP Context */
#define IRDMAQPC_DDP_VER_S 0 #define IRDMAQPC_DDP_VER_S 0
#define IRDMAQPC_DDP_VER_M (3ULL << IRDMAQPC_DDP_VER_S) #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
#define IRDMAQPC_IBRDENABLE_S 2 #define IRDMAQPC_IBRDENABLE_S 2
#define IRDMAQPC_IBRDENABLE_M BIT_ULL(IRDMAQPC_IBRDENABLE_S) #define IRDMAQPC_IBRDENABLE BIT_ULL(2)
#define IRDMAQPC_IPV4_S 3 #define IRDMAQPC_IPV4_S 3
#define IRDMAQPC_IPV4_M BIT_ULL(IRDMAQPC_IPV4_S) #define IRDMAQPC_IPV4 BIT_ULL(3)
#define IRDMAQPC_NONAGLE_S 4 #define IRDMAQPC_NONAGLE_S 4
#define IRDMAQPC_NONAGLE_M BIT_ULL(IRDMAQPC_NONAGLE_S) #define IRDMAQPC_NONAGLE BIT_ULL(4)
#define IRDMAQPC_INSERTVLANTAG_S 5 #define IRDMAQPC_INSERTVLANTAG_S 5
#define IRDMAQPC_INSERTVLANTAG_M BIT_ULL(IRDMAQPC_INSERTVLANTAG_S) #define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)
#define IRDMAQPC_ISQP1_S 6 #define IRDMAQPC_ISQP1_S 6
#define IRDMAQPC_ISQP1_M BIT_ULL(IRDMAQPC_ISQP1_S) #define IRDMAQPC_ISQP1 BIT_ULL(6)
#define IRDMAQPC_TIMESTAMP_S 7 #define IRDMAQPC_TIMESTAMP_S 7
#define IRDMAQPC_TIMESTAMP_M BIT_ULL(IRDMAQPC_TIMESTAMP_S) #define IRDMAQPC_TIMESTAMP BIT_ULL(7)
#define IRDMAQPC_RQWQESIZE_S 8 #define IRDMAQPC_RQWQESIZE_S 8
#define IRDMAQPC_RQWQESIZE_M (3ULL << IRDMAQPC_RQWQESIZE_S) #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
#define IRDMAQPC_INSERTL2TAG2_S 11 #define IRDMAQPC_INSERTL2TAG2_S 11
#define IRDMAQPC_INSERTL2TAG2_M BIT_ULL(IRDMAQPC_INSERTL2TAG2_S) #define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)
#define IRDMAQPC_LIMIT_S 12 #define IRDMAQPC_LIMIT_S 12
#define IRDMAQPC_LIMIT_M (3ULL << IRDMAQPC_LIMIT_S) #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
#define IRDMAQPC_ECN_EN_S 14 #define IRDMAQPC_ECN_EN_S 14
#define IRDMAQPC_ECN_EN_M BIT_ULL(IRDMAQPC_ECN_EN_S) #define IRDMAQPC_ECN_EN BIT_ULL(14)
#define IRDMAQPC_DROPOOOSEG_S 15 #define IRDMAQPC_DROPOOOSEG_S 15
#define IRDMAQPC_DROPOOOSEG_M BIT_ULL(IRDMAQPC_DROPOOOSEG_S) #define IRDMAQPC_DROPOOOSEG BIT_ULL(15)
#define IRDMAQPC_DUPACK_THRESH_S 16 #define IRDMAQPC_DUPACK_THRESH_S 16
#define IRDMAQPC_DUPACK_THRESH_M (7ULL << IRDMAQPC_DUPACK_THRESH_S) #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
#define IRDMAQPC_ERR_RQ_IDX_VALID_S 19 #define IRDMAQPC_ERR_RQ_IDX_VALID_S 19
#define IRDMAQPC_ERR_RQ_IDX_VALID_M BIT_ULL(IRDMAQPC_ERR_RQ_IDX_VALID_S) #define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)
#define IRDMAQPC_DIS_VLAN_CHECKS_S 19 #define IRDMAQPC_DIS_VLAN_CHECKS_S 19
#define IRDMAQPC_DIS_VLAN_CHECKS_M (7ULL << IRDMAQPC_DIS_VLAN_CHECKS_S) #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
#define IRDMAQPC_DC_TCP_EN_S 25 #define IRDMAQPC_DC_TCP_EN_S 25
#define IRDMAQPC_DC_TCP_EN_M BIT_ULL(IRDMAQPC_DC_TCP_EN_S) #define IRDMAQPC_DC_TCP_EN BIT_ULL(25)
#define IRDMAQPC_RCVTPHEN_S 28 #define IRDMAQPC_RCVTPHEN_S 28
#define IRDMAQPC_RCVTPHEN_M BIT_ULL(IRDMAQPC_RCVTPHEN_S) #define IRDMAQPC_RCVTPHEN BIT_ULL(28)
#define IRDMAQPC_XMITTPHEN_S 29 #define IRDMAQPC_XMITTPHEN_S 29
#define IRDMAQPC_XMITTPHEN_M BIT_ULL(IRDMAQPC_XMITTPHEN_S) #define IRDMAQPC_XMITTPHEN BIT_ULL(29)
#define IRDMAQPC_RQTPHEN_S 30 #define IRDMAQPC_RQTPHEN_S 30
#define IRDMAQPC_RQTPHEN_M BIT_ULL(IRDMAQPC_RQTPHEN_S) #define IRDMAQPC_RQTPHEN BIT_ULL(30)
#define IRDMAQPC_SQTPHEN_S 31 #define IRDMAQPC_SQTPHEN_S 31
#define IRDMAQPC_SQTPHEN_M BIT_ULL(IRDMAQPC_SQTPHEN_S) #define IRDMAQPC_SQTPHEN BIT_ULL(31)
#define IRDMAQPC_PPIDX_S 32 #define IRDMAQPC_PPIDX_S 32
#define IRDMAQPC_PPIDX_M (0x3ffULL << IRDMAQPC_PPIDX_S) #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
#define IRDMAQPC_PMENA_S 47 #define IRDMAQPC_PMENA_S 47
#define IRDMAQPC_PMENA_M BIT_ULL(IRDMAQPC_PMENA_S) #define IRDMAQPC_PMENA BIT_ULL(47)
#define IRDMAQPC_RDMAP_VER_S 62 #define IRDMAQPC_RDMAP_VER_S 62
#define IRDMAQPC_RDMAP_VER_M (3ULL << IRDMAQPC_RDMAP_VER_S) #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
#define IRDMAQPC_ROCE_TVER_S 60 #define IRDMAQPC_ROCE_TVER_S 60
#define IRDMAQPC_ROCE_TVER_M (0x0fULL << IRDMAQPC_ROCE_TVER_S) #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
#define IRDMAQPC_SQADDR_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPC_SQADDR_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPC_SQADDR_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX
#define IRDMAQPC_RQADDR_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPC_RQADDR_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPC_RQADDR_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX
#define IRDMAQPC_TTL_S 0 #define IRDMAQPC_TTL_S 0
#define IRDMAQPC_TTL_M (0xffULL << IRDMAQPC_TTL_S) #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
#define IRDMAQPC_RQSIZE_S 8 #define IRDMAQPC_RQSIZE_S 8
#define IRDMAQPC_RQSIZE_M (0xfULL << IRDMAQPC_RQSIZE_S) #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
#define IRDMAQPC_SQSIZE_S 12 #define IRDMAQPC_SQSIZE_S 12
#define IRDMAQPC_SQSIZE_M (0xfULL << IRDMAQPC_SQSIZE_S) #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
#define IRDMAQPC_GEN1_SRCMACADDRIDX_S 16 #define IRDMAQPC_GEN1_SRCMACADDRIDX_S 16
#define IRDMAQPC_GEN1_SRCMACADDRIDX_M (0x3fUL << IRDMAQPC_GEN1_SRCMACADDRIDX_S) #define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16)
#define IRDMAQPC_AVOIDSTRETCHACK_S 23 #define IRDMAQPC_AVOIDSTRETCHACK_S 23
#define IRDMAQPC_AVOIDSTRETCHACK_M BIT_ULL(IRDMAQPC_AVOIDSTRETCHACK_S) #define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)
#define IRDMAQPC_TOS_S 24 #define IRDMAQPC_TOS_S 24
#define IRDMAQPC_TOS_M (0xffULL << IRDMAQPC_TOS_S) #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
#define IRDMAQPC_SRCPORTNUM_S 32 #define IRDMAQPC_SRCPORTNUM_S 32
#define IRDMAQPC_SRCPORTNUM_M (0xffffULL << IRDMAQPC_SRCPORTNUM_S) #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
#define IRDMAQPC_DESTPORTNUM_S 48 #define IRDMAQPC_DESTPORTNUM_S 48
#define IRDMAQPC_DESTPORTNUM_M (0xffffULL << IRDMAQPC_DESTPORTNUM_S) #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
#define IRDMAQPC_DESTIPADDR0_S 32 #define IRDMAQPC_DESTIPADDR0_S 32
#define IRDMAQPC_DESTIPADDR0_M \ #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPC_DESTIPADDR0_S)
#define IRDMAQPC_DESTIPADDR1_S 0 #define IRDMAQPC_DESTIPADDR1_S 0
#define IRDMAQPC_DESTIPADDR1_M \ #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMAQPC_DESTIPADDR1_S)
#define IRDMAQPC_DESTIPADDR2_S 32 #define IRDMAQPC_DESTIPADDR2_S 32
#define IRDMAQPC_DESTIPADDR2_M \ #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPC_DESTIPADDR2_S)
#define IRDMAQPC_DESTIPADDR3_S 0 #define IRDMAQPC_DESTIPADDR3_S 0
#define IRDMAQPC_DESTIPADDR3_M \ #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMAQPC_DESTIPADDR3_S)
#define IRDMAQPC_SNDMSS_S 16 #define IRDMAQPC_SNDMSS_S 16
#define IRDMAQPC_SNDMSS_M (0x3fffULL << IRDMAQPC_SNDMSS_S) #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
#define IRDMAQPC_SYN_RST_HANDLING_S 30 #define IRDMAQPC_SYN_RST_HANDLING_S 30
#define IRDMAQPC_SYN_RST_HANDLING_M (0x3ULL << IRDMAQPC_SYN_RST_HANDLING_S) #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
#define IRDMAQPC_VLANTAG_S 32 #define IRDMAQPC_VLANTAG_S 32
#define IRDMAQPC_VLANTAG_M (0xffffULL << IRDMAQPC_VLANTAG_S) #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
#define IRDMAQPC_ARPIDX_S 48 #define IRDMAQPC_ARPIDX_S 48
#define IRDMAQPC_ARPIDX_M (0xffffULL << IRDMAQPC_ARPIDX_S) #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
#define IRDMAQPC_FLOWLABEL_S 0 #define IRDMAQPC_FLOWLABEL_S 0
#define IRDMAQPC_FLOWLABEL_M (0xfffffULL << IRDMAQPC_FLOWLABEL_S) #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
#define IRDMAQPC_WSCALE_S 20 #define IRDMAQPC_WSCALE_S 20
#define IRDMAQPC_WSCALE_M BIT_ULL(IRDMAQPC_WSCALE_S) #define IRDMAQPC_WSCALE BIT_ULL(20)
#define IRDMAQPC_KEEPALIVE_S 21 #define IRDMAQPC_KEEPALIVE_S 21
#define IRDMAQPC_KEEPALIVE_M BIT_ULL(IRDMAQPC_KEEPALIVE_S) #define IRDMAQPC_KEEPALIVE BIT_ULL(21)
#define IRDMAQPC_IGNORE_TCP_OPT_S 22 #define IRDMAQPC_IGNORE_TCP_OPT_S 22
#define IRDMAQPC_IGNORE_TCP_OPT_M BIT_ULL(IRDMAQPC_IGNORE_TCP_OPT_S) #define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)
#define IRDMAQPC_IGNORE_TCP_UNS_OPT_S 23 #define IRDMAQPC_IGNORE_TCP_UNS_OPT_S 23
#define IRDMAQPC_IGNORE_TCP_UNS_OPT_M \ #define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)
BIT_ULL(IRDMAQPC_IGNORE_TCP_UNS_OPT_S)
#define IRDMAQPC_TCPSTATE_S 28 #define IRDMAQPC_TCPSTATE_S 28
#define IRDMAQPC_TCPSTATE_M (0xfULL << IRDMAQPC_TCPSTATE_S) #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
#define IRDMAQPC_RCVSCALE_S 32 #define IRDMAQPC_RCVSCALE_S 32
#define IRDMAQPC_RCVSCALE_M (0xfULL << IRDMAQPC_RCVSCALE_S) #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
#define IRDMAQPC_SNDSCALE_S 40 #define IRDMAQPC_SNDSCALE_S 40
#define IRDMAQPC_SNDSCALE_M (0xfULL << IRDMAQPC_SNDSCALE_S) #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
#define IRDMAQPC_PDIDX_S 48 #define IRDMAQPC_PDIDX_S 48
#define IRDMAQPC_PDIDX_M (0xffffULL << IRDMAQPC_PDIDX_S) #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
#define IRDMAQPC_PDIDXHI_S 20 #define IRDMAQPC_PDIDXHI_S 20
#define IRDMAQPC_PDIDXHI_M (0x3ULL << IRDMAQPC_PDIDXHI_S) #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
#define IRDMAQPC_PKEY_S 32 #define IRDMAQPC_PKEY_S 32
#define IRDMAQPC_PKEY_M (0xffffULL << IRDMAQPC_PKEY_S) #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
#define IRDMAQPC_ACKCREDITS_S 20 #define IRDMAQPC_ACKCREDITS_S 20
#define IRDMAQPC_ACKCREDITS_M (0x1fULL << IRDMAQPC_ACKCREDITS_S) #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
#define IRDMAQPC_QKEY_S 32 #define IRDMAQPC_QKEY_S 32
#define IRDMAQPC_QKEY_M (0xffffffffULL << IRDMAQPC_QKEY_S) #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
#define IRDMAQPC_DESTQP_S 0 #define IRDMAQPC_DESTQP_S 0
#define IRDMAQPC_DESTQP_M (0xffffffULL << IRDMAQPC_DESTQP_S) #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S 16 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S 16
#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_M \ #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
(0xffULL << IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S)
#define IRDMAQPC_KEEPALIVE_INTERVAL_S 24 #define IRDMAQPC_KEEPALIVE_INTERVAL_S 24
#define IRDMAQPC_KEEPALIVE_INTERVAL_M \ #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
(0xffULL << IRDMAQPC_KEEPALIVE_INTERVAL_S)
#define IRDMAQPC_TIMESTAMP_RECENT_S 0 #define IRDMAQPC_TIMESTAMP_RECENT_S 0
#define IRDMAQPC_TIMESTAMP_RECENT_M \ #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMAQPC_TIMESTAMP_RECENT_S)
#define IRDMAQPC_TIMESTAMP_AGE_S 32 #define IRDMAQPC_TIMESTAMP_AGE_S 32
#define IRDMAQPC_TIMESTAMP_AGE_M \ #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPC_TIMESTAMP_AGE_S)
#define IRDMAQPC_SNDNXT_S 0 #define IRDMAQPC_SNDNXT_S 0
#define IRDMAQPC_SNDNXT_M (0xffffffffULL << IRDMAQPC_SNDNXT_S) #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
#define IRDMAQPC_ISN_S 32 #define IRDMAQPC_ISN_S 32
#define IRDMAQPC_ISN_M (0x00ffffffULL << IRDMAQPC_ISN_S) #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
#define IRDMAQPC_PSNNXT_S 0 #define IRDMAQPC_PSNNXT_S 0
#define IRDMAQPC_PSNNXT_M (0x00ffffffULL << IRDMAQPC_PSNNXT_S) #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
#define IRDMAQPC_LSN_S 32 #define IRDMAQPC_LSN_S 32
#define IRDMAQPC_LSN_M (0x00ffffffULL << IRDMAQPC_LSN_S) #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
#define IRDMAQPC_SNDWND_S 32 #define IRDMAQPC_SNDWND_S 32
#define IRDMAQPC_SNDWND_M (0xffffffffULL << IRDMAQPC_SNDWND_S) #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
#define IRDMAQPC_RCVNXT_S 0 #define IRDMAQPC_RCVNXT_S 0
#define IRDMAQPC_RCVNXT_M (0xffffffffULL << IRDMAQPC_RCVNXT_S) #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
#define IRDMAQPC_EPSN_S 0 #define IRDMAQPC_EPSN_S 0
#define IRDMAQPC_EPSN_M (0x00ffffffULL << IRDMAQPC_EPSN_S) #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
#define IRDMAQPC_RCVWND_S 32 #define IRDMAQPC_RCVWND_S 32
#define IRDMAQPC_RCVWND_M (0xffffffffULL << IRDMAQPC_RCVWND_S) #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
#define IRDMAQPC_SNDMAX_S 0 #define IRDMAQPC_SNDMAX_S 0
#define IRDMAQPC_SNDMAX_M (0xffffffffULL << IRDMAQPC_SNDMAX_S) #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
#define IRDMAQPC_SNDUNA_S 32 #define IRDMAQPC_SNDUNA_S 32
#define IRDMAQPC_SNDUNA_M (0xffffffffULL << IRDMAQPC_SNDUNA_S) #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
#define IRDMAQPC_PSNMAX_S 0 #define IRDMAQPC_PSNMAX_S 0
#define IRDMAQPC_PSNMAX_M (0x00ffffffULL << IRDMAQPC_PSNMAX_S) #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
#define IRDMAQPC_PSNUNA_S 32 #define IRDMAQPC_PSNUNA_S 32
#define IRDMAQPC_PSNUNA_M (0xffffffULL << IRDMAQPC_PSNUNA_S) #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
#define IRDMAQPC_SRTT_S 0 #define IRDMAQPC_SRTT_S 0
#define IRDMAQPC_SRTT_M (0xffffffffULL << IRDMAQPC_SRTT_S) #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
#define IRDMAQPC_RTTVAR_S 32 #define IRDMAQPC_RTTVAR_S 32
#define IRDMAQPC_RTTVAR_M (0xffffffffULL << IRDMAQPC_RTTVAR_S) #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
#define IRDMAQPC_SSTHRESH_S 0 #define IRDMAQPC_SSTHRESH_S 0
#define IRDMAQPC_SSTHRESH_M (0xffffffffULL << IRDMAQPC_SSTHRESH_S) #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
#define IRDMAQPC_CWND_S 32 #define IRDMAQPC_CWND_S 32
#define IRDMAQPC_CWND_M (0xffffffffULL << IRDMAQPC_CWND_S) #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
#define IRDMAQPC_CWNDROCE_S 32 #define IRDMAQPC_CWNDROCE_S 32
#define IRDMAQPC_CWNDROCE_M (0xffffffULL << IRDMAQPC_CWNDROCE_S) #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
#define IRDMAQPC_SNDWL1_S 0 #define IRDMAQPC_SNDWL1_S 0
#define IRDMAQPC_SNDWL1_M (0xffffffffULL << IRDMAQPC_SNDWL1_S) #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
#define IRDMAQPC_SNDWL2_S 32 #define IRDMAQPC_SNDWL2_S 32
#define IRDMAQPC_SNDWL2_M (0xffffffffULL << IRDMAQPC_SNDWL2_S) #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
#define IRDMAQPC_ERR_RQ_IDX_S 32 #define IRDMAQPC_ERR_RQ_IDX_S 32
#define IRDMAQPC_ERR_RQ_IDX_M (0x3fffULL << IRDMAQPC_ERR_RQ_IDX_S) #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
#define IRDMAQPC_RTOMIN_S 57 #define IRDMAQPC_RTOMIN_S 57
#define IRDMAQPC_RTOMIN_M (0x7fULL << IRDMAQPC_RTOMIN_S) #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
#define IRDMAQPC_MAXSNDWND_S 0 #define IRDMAQPC_MAXSNDWND_S 0
#define IRDMAQPC_MAXSNDWND_M (0xffffffffULL << IRDMAQPC_MAXSNDWND_S) #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
#define IRDMAQPC_REXMIT_THRESH_S 48 #define IRDMAQPC_REXMIT_THRESH_S 48
#define IRDMAQPC_REXMIT_THRESH_M (0x3fULL << IRDMAQPC_REXMIT_THRESH_S) #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
#define IRDMAQPC_RNRNAK_THRESH_S 54 #define IRDMAQPC_RNRNAK_THRESH_S 54
#define IRDMAQPC_RNRNAK_THRESH_M (0x7ULL << IRDMAQPC_RNRNAK_THRESH_S) #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
#define IRDMAQPC_TXCQNUM_S 0 #define IRDMAQPC_TXCQNUM_S 0
#define IRDMAQPC_TXCQNUM_M (0x7ffffULL << IRDMAQPC_TXCQNUM_S) #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
#define IRDMAQPC_RXCQNUM_S 32 #define IRDMAQPC_RXCQNUM_S 32
#define IRDMAQPC_RXCQNUM_M (0x7ffffULL << IRDMAQPC_RXCQNUM_S) #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
#define IRDMAQPC_STAT_INDEX_S 0 #define IRDMAQPC_STAT_INDEX_S 0
#define IRDMAQPC_STAT_INDEX_M (0x7fULL << IRDMAQPC_STAT_INDEX_S) #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
#define IRDMAQPC_Q2ADDR_S 8 #define IRDMAQPC_Q2ADDR_S 8
#define IRDMAQPC_Q2ADDR_M (0xffffffffffffffULL << IRDMAQPC_Q2ADDR_S) #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
#define IRDMAQPC_LASTBYTESENT_S 0 #define IRDMAQPC_LASTBYTESENT_S 0
#define IRDMAQPC_LASTBYTESENT_M (0xffULL << IRDMAQPC_LASTBYTESENT_S) #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
#define IRDMAQPC_MACADDRESS_S 16 #define IRDMAQPC_MACADDRESS_S 16
#define IRDMAQPC_MACADDRESS_M (0xffffffffffffULL << IRDMAQPC_MACADDRESS_S) #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
#define IRDMAQPC_ORDSIZE_S 0 #define IRDMAQPC_ORDSIZE_S 0
#define IRDMAQPC_ORDSIZE_M (0xffULL << IRDMAQPC_ORDSIZE_S) #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
#define IRDMAQPC_IRDSIZE_S 16 #define IRDMAQPC_IRDSIZE_S 16
#define IRDMAQPC_IRDSIZE_M (0x7ULL << IRDMAQPC_IRDSIZE_S) #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
#define IRDMAQPC_UDPRIVCQENABLE_S 19 #define IRDMAQPC_UDPRIVCQENABLE_S 19
#define IRDMAQPC_UDPRIVCQENABLE_M BIT_ULL(IRDMAQPC_UDPRIVCQENABLE_S) #define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
#define IRDMAQPC_WRRDRSPOK_S 20 #define IRDMAQPC_WRRDRSPOK_S 20
#define IRDMAQPC_WRRDRSPOK_M BIT_ULL(IRDMAQPC_WRRDRSPOK_S) #define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
#define IRDMAQPC_RDOK_S 21 #define IRDMAQPC_RDOK_S 21
#define IRDMAQPC_RDOK_M BIT_ULL(IRDMAQPC_RDOK_S) #define IRDMAQPC_RDOK BIT_ULL(21)
#define IRDMAQPC_SNDMARKERS_S 22 #define IRDMAQPC_SNDMARKERS_S 22
#define IRDMAQPC_SNDMARKERS_M BIT_ULL(IRDMAQPC_SNDMARKERS_S) #define IRDMAQPC_SNDMARKERS BIT_ULL(22)
#define IRDMAQPC_DCQCNENABLE_S 22 #define IRDMAQPC_DCQCNENABLE_S 22
#define IRDMAQPC_DCQCNENABLE_M BIT_ULL(IRDMAQPC_DCQCNENABLE_S) #define IRDMAQPC_DCQCNENABLE BIT_ULL(22)
#define IRDMAQPC_FW_CC_ENABLE_S 28 #define IRDMAQPC_FW_CC_ENABLE_S 28
#define IRDMAQPC_FW_CC_ENABLE_M BIT_ULL(IRDMAQPC_FW_CC_ENABLE_S) #define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)
#define IRDMAQPC_RCVNOICRC_S 31 #define IRDMAQPC_RCVNOICRC_S 31
#define IRDMAQPC_RCVNOICRC_M BIT_ULL(IRDMAQPC_RCVNOICRC_S) #define IRDMAQPC_RCVNOICRC BIT_ULL(31)
#define IRDMAQPC_BINDEN_S 23 #define IRDMAQPC_BINDEN_S 23
#define IRDMAQPC_BINDEN_M BIT_ULL(IRDMAQPC_BINDEN_S) #define IRDMAQPC_BINDEN BIT_ULL(23)
#define IRDMAQPC_FASTREGEN_S 24 #define IRDMAQPC_FASTREGEN_S 24
#define IRDMAQPC_FASTREGEN_M BIT_ULL(IRDMAQPC_FASTREGEN_S) #define IRDMAQPC_FASTREGEN BIT_ULL(24)
#define IRDMAQPC_PRIVEN_S 25 #define IRDMAQPC_PRIVEN_S 25
#define IRDMAQPC_PRIVEN_M BIT_ULL(IRDMAQPC_PRIVEN_S) #define IRDMAQPC_PRIVEN BIT_ULL(25)
#define IRDMAQPC_TIMELYENABLE_S 27 #define IRDMAQPC_TIMELYENABLE_S 27
#define IRDMAQPC_TIMELYENABLE_M BIT_ULL(IRDMAQPC_TIMELYENABLE_S) #define IRDMAQPC_TIMELYENABLE BIT_ULL(27)
#define IRDMAQPC_THIGH_S 52 #define IRDMAQPC_THIGH_S 52
#define IRDMAQPC_THIGH_M ((u64)0xfff << IRDMAQPC_THIGH_S) #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
#define IRDMAQPC_TLOW_S 32 #define IRDMAQPC_TLOW_S 32
#define IRDMAQPC_TLOW_M ((u64)0xFF << IRDMAQPC_TLOW_S) #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
#define IRDMAQPC_REMENDPOINTIDX_S 0 #define IRDMAQPC_REMENDPOINTIDX_S 0
#define IRDMAQPC_REMENDPOINTIDX_M ((u64)0x1FFFF << IRDMAQPC_REMENDPOINTIDX_S) #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
#define IRDMAQPC_USESTATSINSTANCE_S 26 #define IRDMAQPC_USESTATSINSTANCE_S 26
#define IRDMAQPC_USESTATSINSTANCE_M BIT_ULL(IRDMAQPC_USESTATSINSTANCE_S) #define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)
#define IRDMAQPC_IWARPMODE_S 28 #define IRDMAQPC_IWARPMODE_S 28
#define IRDMAQPC_IWARPMODE_M BIT_ULL(IRDMAQPC_IWARPMODE_S) #define IRDMAQPC_IWARPMODE BIT_ULL(28)
#define IRDMAQPC_RCVMARKERS_S 29 #define IRDMAQPC_RCVMARKERS_S 29
#define IRDMAQPC_RCVMARKERS_M BIT_ULL(IRDMAQPC_RCVMARKERS_S) #define IRDMAQPC_RCVMARKERS BIT_ULL(29)
#define IRDMAQPC_ALIGNHDRS_S 30 #define IRDMAQPC_ALIGNHDRS_S 30
#define IRDMAQPC_ALIGNHDRS_M BIT_ULL(IRDMAQPC_ALIGNHDRS_S) #define IRDMAQPC_ALIGNHDRS BIT_ULL(30)
#define IRDMAQPC_RCVNOMPACRC_S 31 #define IRDMAQPC_RCVNOMPACRC_S 31
#define IRDMAQPC_RCVNOMPACRC_M BIT_ULL(IRDMAQPC_RCVNOMPACRC_S) #define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)
#define IRDMAQPC_RCVMARKOFFSET_S 32 #define IRDMAQPC_RCVMARKOFFSET_S 32
#define IRDMAQPC_RCVMARKOFFSET_M (0x1ffULL << IRDMAQPC_RCVMARKOFFSET_S) #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
#define IRDMAQPC_SNDMARKOFFSET_S 48 #define IRDMAQPC_SNDMARKOFFSET_S 48
#define IRDMAQPC_SNDMARKOFFSET_M (0x1ffULL << IRDMAQPC_SNDMARKOFFSET_S) #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
#define IRDMAQPC_QPCOMPCTX_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPC_QPCOMPCTX_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPC_QPCOMPCTX_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX
#define IRDMAQPC_SQTPHVAL_S 0 #define IRDMAQPC_SQTPHVAL_S 0
#define IRDMAQPC_SQTPHVAL_M (0xffULL << IRDMAQPC_SQTPHVAL_S) #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
#define IRDMAQPC_RQTPHVAL_S 8 #define IRDMAQPC_RQTPHVAL_S 8
#define IRDMAQPC_RQTPHVAL_M (0xffULL << IRDMAQPC_RQTPHVAL_S) #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
#define IRDMAQPC_QSHANDLE_S 16 #define IRDMAQPC_QSHANDLE_S 16
#define IRDMAQPC_QSHANDLE_M (0x3ffULL << IRDMAQPC_QSHANDLE_S) #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
#define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32 #define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32
#define IRDMAQPC_EXCEPTION_LAN_QUEUE_M \ #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
(0xfffULL << IRDMAQPC_EXCEPTION_LAN_QUEUE_S)
#define IRDMAQPC_LOCAL_IPADDR3_S 0 #define IRDMAQPC_LOCAL_IPADDR3_S 0
#define IRDMAQPC_LOCAL_IPADDR3_M \ #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMAQPC_LOCAL_IPADDR3_S)
#define IRDMAQPC_LOCAL_IPADDR2_S 32 #define IRDMAQPC_LOCAL_IPADDR2_S 32
#define IRDMAQPC_LOCAL_IPADDR2_M \ #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPC_LOCAL_IPADDR2_S)
#define IRDMAQPC_LOCAL_IPADDR1_S 0 #define IRDMAQPC_LOCAL_IPADDR1_S 0
#define IRDMAQPC_LOCAL_IPADDR1_M \ #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
(0xffffffffULL << IRDMAQPC_LOCAL_IPADDR1_S)
#define IRDMAQPC_LOCAL_IPADDR0_S 32 #define IRDMAQPC_LOCAL_IPADDR0_S 32
#define IRDMAQPC_LOCAL_IPADDR0_M \ #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPC_LOCAL_IPADDR0_S)
#define IRDMA_FW_VER_MINOR_S 0 #define IRDMA_FW_VER_MINOR_S 0
#define IRDMA_FW_VER_MINOR_M \ #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
(0xffffULL << IRDMA_FW_VER_MINOR_S)
#define IRDMA_FW_VER_MAJOR_S 16 #define IRDMA_FW_VER_MAJOR_S 16
#define IRDMA_FW_VER_MAJOR_M \ #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
(0xffffULL << IRDMA_FW_VER_MAJOR_S)
#define IRDMA_FEATURE_INFO_S 0 #define IRDMA_FEATURE_INFO_S 0
#define IRDMA_FEATURE_INFO_M \ #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
(0xffffffffffffULL << IRDMA_FEATURE_INFO_S)
#define IRDMA_FEATURE_CNT_S 32 #define IRDMA_FEATURE_CNT_S 32
#define IRDMA_FEATURE_CNT_M \ #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
(0xffffULL << IRDMA_FEATURE_CNT_S)
#define IRDMA_FEATURE_TYPE_S 48 #define IRDMA_FEATURE_TYPE_S 48
#define IRDMA_FEATURE_TYPE_M \ #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
(0xffffULL << IRDMA_FEATURE_TYPE_S)
#define IRDMA_RSVD_S 41 #define IRDMA_RSVD_S 41
#define IRDMA_RSVD_M (0x7fffULL << IRDMA_RSVD_S) #define IRDMA_RSVD GENMASK_ULL(55, 41)
/* iwarp QP SQ WQE common fields */
#define IRDMAQPSQ_OPCODE_S 32 #define IRDMAQPSQ_OPCODE_S 32
#define IRDMAQPSQ_OPCODE_M (0x3fULL << IRDMAQPSQ_OPCODE_S) #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
#define IRDMAQPSQ_COPY_HOST_PBL_S 43 #define IRDMAQPSQ_COPY_HOST_PBL_S 43
#define IRDMAQPSQ_COPY_HOST_PBL_M BIT_ULL(IRDMAQPSQ_COPY_HOST_PBL_S) #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
#define IRDMAQPSQ_ADDFRAGCNT_S 38 #define IRDMAQPSQ_ADDFRAGCNT_S 38
#define IRDMAQPSQ_ADDFRAGCNT_M (0xfULL << IRDMAQPSQ_ADDFRAGCNT_S) #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
#define IRDMAQPSQ_PUSHWQE_S 56 #define IRDMAQPSQ_PUSHWQE_S 56
#define IRDMAQPSQ_PUSHWQE_M BIT_ULL(IRDMAQPSQ_PUSHWQE_S) #define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
#define IRDMAQPSQ_STREAMMODE_S 58 #define IRDMAQPSQ_STREAMMODE_S 58
#define IRDMAQPSQ_STREAMMODE_M BIT_ULL(IRDMAQPSQ_STREAMMODE_S) #define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
#define IRDMAQPSQ_WAITFORRCVPDU_S 59 #define IRDMAQPSQ_WAITFORRCVPDU_S 59
#define IRDMAQPSQ_WAITFORRCVPDU_M BIT_ULL(IRDMAQPSQ_WAITFORRCVPDU_S) #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
#define IRDMAQPSQ_READFENCE_S 60 #define IRDMAQPSQ_READFENCE_S 60
#define IRDMAQPSQ_READFENCE_M BIT_ULL(IRDMAQPSQ_READFENCE_S) #define IRDMAQPSQ_READFENCE BIT_ULL(60)
#define IRDMAQPSQ_LOCALFENCE_S 61 #define IRDMAQPSQ_LOCALFENCE_S 61
#define IRDMAQPSQ_LOCALFENCE_M BIT_ULL(IRDMAQPSQ_LOCALFENCE_S) #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
#define IRDMAQPSQ_UDPHEADER_S 61 #define IRDMAQPSQ_UDPHEADER_S 61
#define IRDMAQPSQ_UDPHEADER_M BIT_ULL(IRDMAQPSQ_UDPHEADER_S) #define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
#define IRDMAQPSQ_L4LEN_S 42 #define IRDMAQPSQ_L4LEN_S 42
#define IRDMAQPSQ_L4LEN_M ((u64)0xF << IRDMAQPSQ_L4LEN_S) #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
#define IRDMAQPSQ_SIGCOMPL_S 62 #define IRDMAQPSQ_SIGCOMPL_S 62
#define IRDMAQPSQ_SIGCOMPL_M BIT_ULL(IRDMAQPSQ_SIGCOMPL_S) #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
#define IRDMAQPSQ_VALID_S 63 #define IRDMAQPSQ_VALID_S 63
#define IRDMAQPSQ_VALID_M BIT_ULL(IRDMAQPSQ_VALID_S) #define IRDMAQPSQ_VALID BIT_ULL(63)
#define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPSQ_FRAG_TO_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX
#define IRDMAQPSQ_FRAG_VALID_S 63 #define IRDMAQPSQ_FRAG_VALID_S 63
#define IRDMAQPSQ_FRAG_VALID_M BIT_ULL(IRDMAQPSQ_FRAG_VALID_S) #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
#define IRDMAQPSQ_FRAG_LEN_S 32 #define IRDMAQPSQ_FRAG_LEN_S 32
#define IRDMAQPSQ_FRAG_LEN_M (0x7fffffffULL << IRDMAQPSQ_FRAG_LEN_S) #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
#define IRDMAQPSQ_FRAG_STAG_S 0 #define IRDMAQPSQ_FRAG_STAG_S 0
#define IRDMAQPSQ_FRAG_STAG_M (0xffffffffULL << IRDMAQPSQ_FRAG_STAG_S) #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
#define IRDMAQPSQ_GEN1_FRAG_LEN_S 0 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
#define IRDMAQPSQ_GEN1_FRAG_LEN_M (0xffffffffULL << IRDMAQPSQ_GEN1_FRAG_LEN_S) #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
#define IRDMAQPSQ_GEN1_FRAG_STAG_S 32 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
#define IRDMAQPSQ_GEN1_FRAG_STAG_M (0xffffffffULL << IRDMAQPSQ_GEN1_FRAG_STAG_S) #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
#define IRDMAQPSQ_REMSTAGINV_S 0 #define IRDMAQPSQ_REMSTAGINV_S 0
#define IRDMAQPSQ_REMSTAGINV_M (0xffffffffULL << IRDMAQPSQ_REMSTAGINV_S) #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
#define IRDMAQPSQ_DESTQKEY_S 0 #define IRDMAQPSQ_DESTQKEY_S 0
#define IRDMAQPSQ_DESTQKEY_M (0xffffffffULL << IRDMAQPSQ_DESTQKEY_S) #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
#define IRDMAQPSQ_DESTQPN_S 32 #define IRDMAQPSQ_DESTQPN_S 32
#define IRDMAQPSQ_DESTQPN_M (0x00ffffffULL << IRDMAQPSQ_DESTQPN_S) #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
#define IRDMAQPSQ_AHID_S 0 #define IRDMAQPSQ_AHID_S 0
#define IRDMAQPSQ_AHID_M (0x0001ffffULL << IRDMAQPSQ_AHID_S) #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
#define IRDMAQPSQ_INLINEDATAFLAG_S 57 #define IRDMAQPSQ_INLINEDATAFLAG_S 57
#define IRDMAQPSQ_INLINEDATAFLAG_M BIT_ULL(IRDMAQPSQ_INLINEDATAFLAG_S) #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
#define IRDMA_INLINE_VALID_S 7 #define IRDMA_INLINE_VALID_S 7
#define IRDMAQPSQ_INLINEDATALEN_S 48 #define IRDMAQPSQ_INLINEDATALEN_S 48
#define IRDMAQPSQ_INLINEDATALEN_M \ #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
(0xffULL << IRDMAQPSQ_INLINEDATALEN_S)
#define IRDMAQPSQ_IMMDATAFLAG_S 47 #define IRDMAQPSQ_IMMDATAFLAG_S 47
#define IRDMAQPSQ_IMMDATAFLAG_M \ #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
BIT_ULL(IRDMAQPSQ_IMMDATAFLAG_S)
#define IRDMAQPSQ_REPORTRTT_S 46 #define IRDMAQPSQ_REPORTRTT_S 46
#define IRDMAQPSQ_REPORTRTT_M \ #define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
BIT_ULL(IRDMAQPSQ_REPORTRTT_S)
#define IRDMAQPSQ_IMMDATA_S 0 #define IRDMAQPSQ_IMMDATA_S 0
#define IRDMAQPSQ_IMMDATA_M \ #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
(0xffffffffffffffffULL << IRDMAQPSQ_IMMDATA_S)
/* rdma write */
#define IRDMAQPSQ_REMSTAG_S 0 #define IRDMAQPSQ_REMSTAG_S 0
#define IRDMAQPSQ_REMSTAG_M (0xffffffffULL << IRDMAQPSQ_REMSTAG_S) #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
#define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPSQ_REMTO_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX
/* memory window */
#define IRDMAQPSQ_STAGRIGHTS_S 48 #define IRDMAQPSQ_STAGRIGHTS_S 48
#define IRDMAQPSQ_STAGRIGHTS_M (0x1fULL << IRDMAQPSQ_STAGRIGHTS_S) #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
#define IRDMAQPSQ_VABASEDTO_S 53 #define IRDMAQPSQ_VABASEDTO_S 53
#define IRDMAQPSQ_VABASEDTO_M BIT_ULL(IRDMAQPSQ_VABASEDTO_S) #define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
#define IRDMAQPSQ_MEMWINDOWTYPE_S 54 #define IRDMAQPSQ_MEMWINDOWTYPE_S 54
#define IRDMAQPSQ_MEMWINDOWTYPE_M BIT_ULL(IRDMAQPSQ_MEMWINDOWTYPE_S) #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
#define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPSQ_MWLEN_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX
#define IRDMAQPSQ_PARENTMRSTAG_S 32 #define IRDMAQPSQ_PARENTMRSTAG_S 32
#define IRDMAQPSQ_PARENTMRSTAG_M \ #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMAQPSQ_PARENTMRSTAG_S)
#define IRDMAQPSQ_MWSTAG_S 0 #define IRDMAQPSQ_MWSTAG_S 0
#define IRDMAQPSQ_MWSTAG_M (0xffffffffULL << IRDMAQPSQ_MWSTAG_S) #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
#define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPSQ_BASEVA_TO_FBO_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX
/* Local Invalidate */
#define IRDMAQPSQ_LOCSTAG_S 0 #define IRDMAQPSQ_LOCSTAG_S 0
#define IRDMAQPSQ_LOCSTAG_M (0xffffffffULL << IRDMAQPSQ_LOCSTAG_S) #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
/* Fast Register */
#define IRDMAQPSQ_STAGKEY_S 0 #define IRDMAQPSQ_STAGKEY_S 0
#define IRDMAQPSQ_STAGKEY_M (0xffULL << IRDMAQPSQ_STAGKEY_S) #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
#define IRDMAQPSQ_STAGINDEX_S 8 #define IRDMAQPSQ_STAGINDEX_S 8
#define IRDMAQPSQ_STAGINDEX_M (0xffffffULL << IRDMAQPSQ_STAGINDEX_S) #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
#define IRDMAQPSQ_COPYHOSTPBLS_S 43 #define IRDMAQPSQ_COPYHOSTPBLS_S 43
#define IRDMAQPSQ_COPYHOSTPBLS_M BIT_ULL(IRDMAQPSQ_COPYHOSTPBLS_S) #define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)
#define IRDMAQPSQ_LPBLSIZE_S 44 #define IRDMAQPSQ_LPBLSIZE_S 44
#define IRDMAQPSQ_LPBLSIZE_M (3ULL << IRDMAQPSQ_LPBLSIZE_S) #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
#define IRDMAQPSQ_HPAGESIZE_S 46 #define IRDMAQPSQ_HPAGESIZE_S 46
#define IRDMAQPSQ_HPAGESIZE_M (3ULL << IRDMAQPSQ_HPAGESIZE_S) #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
#define IRDMAQPSQ_STAGLEN_S 0 #define IRDMAQPSQ_STAGLEN_S 0
#define IRDMAQPSQ_STAGLEN_M (0x1ffffffffffULL << IRDMAQPSQ_STAGLEN_S) #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
#define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48 #define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48
#define IRDMAQPSQ_FIRSTPMPBLIDXLO_M \ #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
(0xffffULL << IRDMAQPSQ_FIRSTPMPBLIDXLO_S)
#define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0 #define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0
#define IRDMAQPSQ_FIRSTPMPBLIDXHI_M \ #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
(0xfffULL << IRDMAQPSQ_FIRSTPMPBLIDXHI_S)
#define IRDMAQPSQ_PBLADDR_S 12 #define IRDMAQPSQ_PBLADDR_S 12
#define IRDMAQPSQ_PBLADDR_M (0xfffffffffffffULL << IRDMAQPSQ_PBLADDR_S) #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
/* iwarp QP RQ WQE common fields */ /* iwarp QP RQ WQE common fields */
#define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S #define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S
#define IRDMAQPRQ_ADDFRAGCNT_M IRDMAQPSQ_ADDFRAGCNT_M #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT
#define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S #define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S
#define IRDMAQPRQ_VALID_M IRDMAQPSQ_VALID_M #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID
#define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S #define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S
#define IRDMAQPRQ_COMPLCTX_M IRDMA_CQPHC_QPCTX_M #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX
#define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S #define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S
#define IRDMAQPRQ_FRAG_LEN_M IRDMAQPSQ_FRAG_LEN_M #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN
#define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S #define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S
#define IRDMAQPRQ_STAG_M IRDMAQPSQ_FRAG_STAG_M #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG
#define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S #define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S
#define IRDMAQPRQ_TO_M IRDMAQPSQ_FRAG_TO_M #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO
#define IRDMAPFINT_OICR_HMC_ERR_M BIT(26) #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
#define IRDMAPFINT_OICR_PE_PUSH_M BIT(27) #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
#define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28) #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
/* Query FPM CQP buf */
#define IRDMA_QUERY_FPM_MAX_QPS_S 0 #define IRDMA_QUERY_FPM_MAX_QPS_S 0
#define IRDMA_QUERY_FPM_MAX_QPS_M \ #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
(0x7ffffULL << IRDMA_QUERY_FPM_MAX_QPS_S)
#define IRDMA_QUERY_FPM_MAX_CQS_S 0 #define IRDMA_QUERY_FPM_MAX_CQS_S 0
#define IRDMA_QUERY_FPM_MAX_CQS_M \ #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
(0xfffffULL << IRDMA_QUERY_FPM_MAX_CQS_S)
#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0
#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_M \ #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
(0x3fffULL << IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S)
#define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32 #define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32
#define IRDMA_QUERY_FPM_MAX_PE_SDS_M \ #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
(0x3fffULL << IRDMA_QUERY_FPM_MAX_PE_SDS_S)
#define IRDMA_QUERY_FPM_MAX_CEQS_S 0 #define IRDMA_QUERY_FPM_MAX_CEQS_S 0
#define IRDMA_QUERY_FPM_MAX_CEQS_M \ #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
(0x3ffULL << IRDMA_QUERY_FPM_MAX_CEQS_S)
#define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32 #define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32
#define IRDMA_QUERY_FPM_XFBLOCKSIZE_M \ #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_QUERY_FPM_XFBLOCKSIZE_S)
#define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32
#define IRDMA_QUERY_FPM_Q1BLOCKSIZE_M \ #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_QUERY_FPM_Q1BLOCKSIZE_S)
#define IRDMA_QUERY_FPM_HTMULTIPLIER_S 16 #define IRDMA_QUERY_FPM_HTMULTIPLIER_S 16
#define IRDMA_QUERY_FPM_HTMULTIPLIER_M \ #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
(0xfULL << IRDMA_QUERY_FPM_HTMULTIPLIER_S)
#define IRDMA_QUERY_FPM_TIMERBUCKET_S 32 #define IRDMA_QUERY_FPM_TIMERBUCKET_S 32
#define IRDMA_QUERY_FPM_TIMERBUCKET_M \ #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
(0xffFFULL << IRDMA_QUERY_FPM_TIMERBUCKET_S)
#define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32
#define IRDMA_QUERY_FPM_RRFBLOCKSIZE_M \ #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_QUERY_FPM_RRFBLOCKSIZE_S)
#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32
#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_M \ #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S)
#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32
#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_M \ #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
(0xffffffffULL << IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S)
/* Static HMC pages allocated buf */
#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0
#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_M \ #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0)
(0x3fULL << IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S)
#define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \ #define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \
( \ ( \
Context not available.
IRDMA_RING_MOVE_HEAD(_ring, _retcode); \ IRDMA_RING_MOVE_HEAD(_ring, _retcode); \
} }
enum irdma_protocol_used {
IRDMA_ANY_PROTOCOL = 0,
IRDMA_IWARP_PROTOCOL_ONLY = 1,
IRDMA_ROCE_PROTOCOL_ONLY = 2,
};
enum irdma_qp_wqe_size { enum irdma_qp_wqe_size {
IRDMA_WQE_SIZE_32 = 32, IRDMA_WQE_SIZE_32 = 32,
IRDMA_WQE_SIZE_64 = 64, IRDMA_WQE_SIZE_64 = 64,
Context not available.