Differential D36944 Diff 111679 sys/dev/irdma/irdma_ctrl.c

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sys/dev/irdma/irdma_ctrl.c

Context not available.
	irdma_change_l2params(struct irdma_sc_vsi *vsi,	irdma_change_l2params(struct irdma_sc_vsi *vsi,
	struct irdma_l2params *l2params)	struct irdma_l2params *l2params)
	{	{
		if (l2params->tc_changed) {
		vsi->tc_change_pending = false;
		irdma_set_qos_info(vsi, l2params);
		irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME);
		}
	if (l2params->mtu_changed) {	if (l2params->mtu_changed) {
	vsi->mtu = l2params->mtu;	vsi->mtu = l2params->mtu;
	if (vsi->ieq)	if (vsi->ieq)
	irdma_reinitialize_ieq(vsi);	irdma_reinitialize_ieq(vsi);
	}	}

	if (!l2params->tc_changed)
	return;

	vsi->tc_change_pending = false;
	irdma_set_qos_info(vsi, l2params);
	irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME);
	}	}

	/**	/**
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_16, temp);	set_64bit_val(wqe, IRDMA_BYTE_16, temp);

	hdr = info->arp_index \|	hdr = info->arp_index \|
	LS_64(IRDMA_CQP_OP_MANAGE_ARP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) \|
	LS_64((info->permanent ? 1 : 0), IRDMA_CQPSQ_MAT_PERMANENT) \|	FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, info->permanent) \|
	LS_64(1, IRDMA_CQPSQ_MAT_ENTRYVALID) \|	FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, true) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	hdr = arp_index \| LS_64(IRDMA_CQP_OP_MANAGE_ARP, IRDMA_CQPSQ_OPCODE) \|	hdr = arp_index \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.

	set_64bit_val(wqe, IRDMA_BYTE_16, info->port);	set_64bit_val(wqe, IRDMA_BYTE_16, info->port);

	hdr = LS_64(IRDMA_CQP_OP_MANAGE_APBVT, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) \|
	LS_64(info->add, IRDMA_CQPSQ_MAPT_ADDPORT) \|	FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	LS_64_1(info->mac_addr[1], 32) \| LS_64_1(info->mac_addr[0], 40);	LS_64_1(info->mac_addr[1], 32) \| LS_64_1(info->mac_addr[0], 40);
	set_64bit_val(wqe, IRDMA_BYTE_0, temp);	set_64bit_val(wqe, IRDMA_BYTE_0, temp);

	qw1 = LS_64(info->qp_num, IRDMA_CQPSQ_QHASH_QPN) \|	qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) \|
	LS_64(info->dest_port, IRDMA_CQPSQ_QHASH_DEST_PORT);	FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port);
	if (info->ipv4_valid) {	if (info->ipv4_valid) {
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	LS_64(info->dest_ip[0], IRDMA_CQPSQ_QHASH_ADDR3));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0]));
	} else {	} else {
	set_64bit_val(wqe, IRDMA_BYTE_56,	set_64bit_val(wqe, IRDMA_BYTE_56,
	LS_64(info->dest_ip[0], IRDMA_CQPSQ_QHASH_ADDR0) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) \|
	LS_64(info->dest_ip[1], IRDMA_CQPSQ_QHASH_ADDR1));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1]));

	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	LS_64(info->dest_ip[2], IRDMA_CQPSQ_QHASH_ADDR2) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) \|
	LS_64(info->dest_ip[3], IRDMA_CQPSQ_QHASH_ADDR3));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3]));
	}	}
	qw2 = LS_64(vsi->qos[info->user_pri].qs_handle,	qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE,
	IRDMA_CQPSQ_QHASH_QS_HANDLE);	vsi->qos[info->user_pri].qs_handle);
	if (info->vlan_valid)	if (info->vlan_valid)
	qw2 \|= LS_64(info->vlan_id, IRDMA_CQPSQ_QHASH_VLANID);	qw2 \|= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id);
	set_64bit_val(wqe, IRDMA_BYTE_16, qw2);	set_64bit_val(wqe, IRDMA_BYTE_16, qw2);
	if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) {	if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) {
	qw1 \|= LS_64(info->src_port, IRDMA_CQPSQ_QHASH_SRC_PORT);	qw1 \|= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port);
	if (!info->ipv4_valid) {	if (!info->ipv4_valid) {
	set_64bit_val(wqe, IRDMA_BYTE_40,	set_64bit_val(wqe, IRDMA_BYTE_40,
	LS_64(info->src_ip[0], IRDMA_CQPSQ_QHASH_ADDR0) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) \|
	LS_64(info->src_ip[1], IRDMA_CQPSQ_QHASH_ADDR1));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1]));
	set_64bit_val(wqe, IRDMA_BYTE_32,	set_64bit_val(wqe, IRDMA_BYTE_32,
	LS_64(info->src_ip[2], IRDMA_CQPSQ_QHASH_ADDR2) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) \|
	LS_64(info->src_ip[3], IRDMA_CQPSQ_QHASH_ADDR3));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3]));
	} else {	} else {
	set_64bit_val(wqe, IRDMA_BYTE_32,	set_64bit_val(wqe, IRDMA_BYTE_32,
	LS_64(info->src_ip[0], IRDMA_CQPSQ_QHASH_ADDR3));	FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0]));
	}	}
	}	}

	set_64bit_val(wqe, IRDMA_BYTE_8, qw1);	set_64bit_val(wqe, IRDMA_BYTE_8, qw1);
	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_QHASH_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) \|
	LS_64(IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY,	FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE,
	IRDMA_CQPSQ_QHASH_OPCODE) \|	IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) \|
	LS_64(info->manage, IRDMA_CQPSQ_QHASH_MANAGE) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) \|
	LS_64(info->ipv4_valid, IRDMA_CQPSQ_QHASH_IPV4VALID) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) \|
	LS_64(info->vlan_valid, IRDMA_CQPSQ_QHASH_VLANVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) \|
	LS_64(info->entry_type, IRDMA_CQPSQ_QHASH_ENTRYTYPE);	FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, temp);	set_64bit_val(wqe, IRDMA_BYTE_24, temp);
Context not available.
	return -EINVAL;	return -EINVAL;

	qp->llp_stream_handle = (void *)(-1);	qp->llp_stream_handle = (void *)(-1);
	qp->qp_uk.force_fence = true;
	qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,	qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
	IRDMA_QUEUE_TYPE_SQ_RQ);	IRDMA_QUEUE_TYPE_SQ_RQ);
	irdma_debug(qp->dev, IRDMA_DEBUG_WQE,	irdma_debug(qp->dev, IRDMA_DEBUG_WQE,
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);

	hdr = qp->qp_uk.qp_id \|	hdr = qp->qp_uk.qp_id \|
	LS_64(IRDMA_CQP_OP_CREATE_QP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) \|
	LS_64((info->ord_valid ? 1 : 0), IRDMA_CQPSQ_QP_ORDVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) \|
	LS_64(info->tcp_ctx_valid, IRDMA_CQPSQ_QP_TOECTXVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) \|
	LS_64(info->mac_valid, IRDMA_CQPSQ_QP_MACVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) \|
	LS_64(qp->qp_uk.qp_type, IRDMA_CQPSQ_QP_QPTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) \|
	LS_64(qp->virtual_map, IRDMA_CQPSQ_QP_VQ) \|	FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) \|
	LS_64(info->force_lpb, IRDMA_CQPSQ_QP_FORCELOOPBACK) \|	FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) \|
	LS_64(info->cq_num_valid, IRDMA_CQPSQ_QP_CQNUMVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) \|
	LS_64(info->arp_cache_idx_valid, IRDMA_CQPSQ_QP_ARPTABIDXVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
	LS_64(info->next_iwarp_state, IRDMA_CQPSQ_QP_NEXTIWSTATE) \|	info->arp_cache_idx_valid) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	}	}

	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(info->new_mss, IRDMA_CQPSQ_QP_NEWMSS) \|	FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) \|
	LS_64(term_len, IRDMA_CQPSQ_QP_TERMLEN));	FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len));
	set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa);	set_64bit_val(wqe, IRDMA_BYTE_16, qp->hw_host_ctx_pa);
	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);

	hdr = qp->qp_uk.qp_id \|	hdr = qp->qp_uk.qp_id \|
	LS_64(IRDMA_CQP_OP_MODIFY_QP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) \|
	LS_64(info->ord_valid, IRDMA_CQPSQ_QP_ORDVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) \|
	LS_64(info->tcp_ctx_valid, IRDMA_CQPSQ_QP_TOECTXVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) \|
	LS_64(info->cached_var_valid, IRDMA_CQPSQ_QP_CACHEDVARVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID,
	LS_64(qp->virtual_map, IRDMA_CQPSQ_QP_VQ) \|	info->cached_var_valid) \|
	LS_64(info->force_lpb, IRDMA_CQPSQ_QP_FORCELOOPBACK) \|	FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) \|
	LS_64(info->cq_num_valid, IRDMA_CQPSQ_QP_CQNUMVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) \|
	LS_64(info->mac_valid, IRDMA_CQPSQ_QP_MACVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) \|
	LS_64(qp->qp_uk.qp_type, IRDMA_CQPSQ_QP_QPTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) \|
	LS_64(info->mss_change, IRDMA_CQPSQ_QP_MSSCHANGE) \|	FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) \|
	LS_64(info->remove_hash_idx, IRDMA_CQPSQ_QP_REMOVEHASHENTRY) \|	FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) \|
	LS_64(term_actions, IRDMA_CQPSQ_QP_TERMACT) \|	FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY,
	LS_64(info->reset_tcp_conn, IRDMA_CQPSQ_QP_RESETCON) \|	info->remove_hash_idx) \|
	LS_64(info->arp_cache_idx_valid, IRDMA_CQPSQ_QP_ARPTABIDXVALID) \|	FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) \|
	LS_64(info->next_iwarp_state, IRDMA_CQPSQ_QP_NEXTIWSTATE) \|	FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID,
		info->arp_cache_idx_valid) \|
		FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);	set_64bit_val(wqe, IRDMA_BYTE_40, qp->shadow_area_pa);

	hdr = qp->qp_uk.qp_id \|	hdr = qp->qp_uk.qp_id \|
	LS_64(IRDMA_CQP_OP_DESTROY_QP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) \|
	LS_64(qp->qp_uk.qp_type, IRDMA_CQPSQ_QP_QPTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) \|
	LS_64(ignore_mw_bnd, IRDMA_CQPSQ_QP_IGNOREMWBOUND) \|	FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) \|
	LS_64(remove_hash_idx, IRDMA_CQPSQ_QP_REMOVEHASHENTRY) \|	FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	push_idx = qp->push_idx;	push_idx = qp->push_idx;
	}	}
	set_64bit_val(qp_ctx, IRDMA_BYTE_0,	set_64bit_val(qp_ctx, IRDMA_BYTE_0,
	LS_64(qp->qp_uk.rq_wqe_size, IRDMAQPC_RQWQESIZE) \|	FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) \|
	LS_64(qp->rcv_tph_en, IRDMAQPC_RCVTPHEN) \|	FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) \|
	LS_64(qp->xmit_tph_en, IRDMAQPC_XMITTPHEN) \|	FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) \|
	LS_64(qp->rq_tph_en, IRDMAQPC_RQTPHEN) \|	FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) \|
	LS_64(qp->sq_tph_en, IRDMAQPC_SQTPHEN) \|	FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) \|
	LS_64(push_idx, IRDMAQPC_PPIDX) \|	FIELD_PREP(IRDMAQPC_PPIDX, push_idx) \|
	LS_64(push_mode_en, IRDMAQPC_PMENA) \|	FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) \|
	LS_64(roce_info->pd_id >> 16, IRDMAQPC_PDIDXHI) \|	FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) \|
	LS_64(roce_info->dctcp_en, IRDMAQPC_DC_TCP_EN) \|	FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) \|
	LS_64(roce_info->err_rq_idx_valid, IRDMAQPC_ERR_RQ_IDX_VALID) \|	FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) \|
	LS_64(roce_info->is_qp1, IRDMAQPC_ISQP1) \|	FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) \|
	LS_64(roce_info->roce_tver, IRDMAQPC_ROCE_TVER) \|	FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) \|
	LS_64(udp->ipv4, IRDMAQPC_IPV4) \|	FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) \|
	LS_64(udp->insert_vlan_tag, IRDMAQPC_INSERTVLANTAG));	FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag));
	set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);	set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);
	set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);	set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);
	if (roce_info->dcqcn_en \|\| roce_info->dctcp_en) {	if (roce_info->dcqcn_en \|\| roce_info->dctcp_en) {
Context not available.
	}	}

	set_64bit_val(qp_ctx, IRDMA_BYTE_24,	set_64bit_val(qp_ctx, IRDMA_BYTE_24,
	LS_64(qp->hw_rq_size, IRDMAQPC_RQSIZE) \|	FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) \|
	LS_64(qp->hw_sq_size, IRDMAQPC_SQSIZE) \|	FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) \|
	LS_64(udp->ttl, IRDMAQPC_TTL) \| LS_64(udp->tos, IRDMAQPC_TOS) \|	FIELD_PREP(IRDMAQPC_TTL, udp->ttl) \| FIELD_PREP(IRDMAQPC_TOS, udp->tos) \|
	LS_64(udp->src_port, IRDMAQPC_SRCPORTNUM) \|	FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) \|
	LS_64(udp->dst_port, IRDMAQPC_DESTPORTNUM));	FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port));
	set_64bit_val(qp_ctx, IRDMA_BYTE_32,	set_64bit_val(qp_ctx, IRDMA_BYTE_32,
	LS_64(udp->dest_ip_addr[2], IRDMAQPC_DESTIPADDR2) \|	FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) \|
	LS_64(udp->dest_ip_addr[3], IRDMAQPC_DESTIPADDR3));	FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_40,	set_64bit_val(qp_ctx, IRDMA_BYTE_40,
	LS_64(udp->dest_ip_addr[0], IRDMAQPC_DESTIPADDR0) \|	FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) \|
	LS_64(udp->dest_ip_addr[1], IRDMAQPC_DESTIPADDR1));	FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_48,	set_64bit_val(qp_ctx, IRDMA_BYTE_48,
	LS_64(udp->snd_mss, IRDMAQPC_SNDMSS) \|	FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) \|
	LS_64(udp->vlan_tag, IRDMAQPC_VLANTAG) \|	FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) \|
	LS_64(udp->arp_idx, IRDMAQPC_ARPIDX));	FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx));
	set_64bit_val(qp_ctx, IRDMA_BYTE_56,	set_64bit_val(qp_ctx, IRDMA_BYTE_56,
	LS_64(roce_info->p_key, IRDMAQPC_PKEY) \|	FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) \|
	LS_64(roce_info->pd_id, IRDMAQPC_PDIDX) \|	FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) \|
	LS_64(roce_info->ack_credits, IRDMAQPC_ACKCREDITS) \|	FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) \|
	LS_64(udp->flow_label, IRDMAQPC_FLOWLABEL));	FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label));
	set_64bit_val(qp_ctx, IRDMA_BYTE_64,	set_64bit_val(qp_ctx, IRDMA_BYTE_64,
	LS_64(roce_info->qkey, IRDMAQPC_QKEY) \|	FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) \|
	LS_64(roce_info->dest_qp, IRDMAQPC_DESTQP));	FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp));
	set_64bit_val(qp_ctx, IRDMA_BYTE_80,	set_64bit_val(qp_ctx, IRDMA_BYTE_80,
	LS_64(udp->psn_nxt, IRDMAQPC_PSNNXT) \|	FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) \|
	LS_64(udp->lsn, IRDMAQPC_LSN));	FIELD_PREP(IRDMAQPC_LSN, udp->lsn));
	set_64bit_val(qp_ctx, IRDMA_BYTE_88, LS_64(udp->epsn, IRDMAQPC_EPSN));	set_64bit_val(qp_ctx, IRDMA_BYTE_88,
		FIELD_PREP(IRDMAQPC_EPSN, udp->epsn));
	set_64bit_val(qp_ctx, IRDMA_BYTE_96,	set_64bit_val(qp_ctx, IRDMA_BYTE_96,
	LS_64(udp->psn_max, IRDMAQPC_PSNMAX) \|	FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) \|
	LS_64(udp->psn_una, IRDMAQPC_PSNUNA));	FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una));
	set_64bit_val(qp_ctx, IRDMA_BYTE_112,	set_64bit_val(qp_ctx, IRDMA_BYTE_112,
	LS_64(udp->cwnd, IRDMAQPC_CWNDROCE));	FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd));
	set_64bit_val(qp_ctx, IRDMA_BYTE_128,	set_64bit_val(qp_ctx, IRDMA_BYTE_128,
	LS_64(roce_info->err_rq_idx, IRDMAQPC_ERR_RQ_IDX) \|	FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) \|
	LS_64(udp->rnr_nak_thresh, IRDMAQPC_RNRNAK_THRESH) \|	FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) \|
	LS_64(udp->rexmit_thresh, IRDMAQPC_REXMIT_THRESH) \|	FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) \|
	LS_64(roce_info->rtomin, IRDMAQPC_RTOMIN));	FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin));
	set_64bit_val(qp_ctx, IRDMA_BYTE_136,	set_64bit_val(qp_ctx, IRDMA_BYTE_136,
	LS_64(info->send_cq_num, IRDMAQPC_TXCQNUM) \|	FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) \|
	LS_64(info->rcv_cq_num, IRDMAQPC_RXCQNUM));	FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
	set_64bit_val(qp_ctx, IRDMA_BYTE_144,	set_64bit_val(qp_ctx, IRDMA_BYTE_144,
	LS_64(info->stats_idx, IRDMAQPC_STAT_INDEX));	FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));
	set_64bit_val(qp_ctx, IRDMA_BYTE_152, mac);	set_64bit_val(qp_ctx, IRDMA_BYTE_152, mac);
	set_64bit_val(qp_ctx, IRDMA_BYTE_160,	set_64bit_val(qp_ctx, IRDMA_BYTE_160,
	LS_64(roce_info->ord_size, IRDMAQPC_ORDSIZE) \|	FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) \|
	LS_64(irdma_sc_get_encoded_ird_size(roce_info->ird_size), IRDMAQPC_IRDSIZE) \|	FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) \|
	LS_64(roce_info->wr_rdresp_en, IRDMAQPC_WRRDRSPOK) \|	FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) \|
	LS_64(roce_info->rd_en, IRDMAQPC_RDOK) \|	FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) \|
	LS_64(info->stats_idx_valid, IRDMAQPC_USESTATSINSTANCE) \|	FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) \|
	LS_64(roce_info->bind_en, IRDMAQPC_BINDEN) \|	FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) \|
	LS_64(roce_info->fast_reg_en, IRDMAQPC_FASTREGEN) \|	FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) \|
	LS_64(roce_info->dcqcn_en, IRDMAQPC_DCQCNENABLE) \|	FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) \|
	LS_64(roce_info->rcv_no_icrc, IRDMAQPC_RCVNOICRC) \|	FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) \|
	LS_64(roce_info->fw_cc_enable, IRDMAQPC_FW_CC_ENABLE) \|	FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) \|
	LS_64(roce_info->udprivcq_en, IRDMAQPC_UDPRIVCQENABLE) \|	FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) \|
	LS_64(roce_info->priv_mode_en, IRDMAQPC_PRIVEN) \|	FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) \|
	LS_64(roce_info->timely_en, IRDMAQPC_TIMELYENABLE));	FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en));
	set_64bit_val(qp_ctx, IRDMA_BYTE_168,	set_64bit_val(qp_ctx, IRDMA_BYTE_168,
	LS_64(info->qp_compl_ctx, IRDMAQPC_QPCOMPCTX));	FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
	set_64bit_val(qp_ctx, IRDMA_BYTE_176,	set_64bit_val(qp_ctx, IRDMA_BYTE_176,
	LS_64(qp->sq_tph_val, IRDMAQPC_SQTPHVAL) \|	FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) \|
	LS_64(qp->rq_tph_val, IRDMAQPC_RQTPHVAL) \|	FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) \|
	LS_64(qp->qs_handle, IRDMAQPC_QSHANDLE));	FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle));
	set_64bit_val(qp_ctx, IRDMA_BYTE_184,	set_64bit_val(qp_ctx, IRDMA_BYTE_184,
	LS_64(udp->local_ipaddr[3], IRDMAQPC_LOCAL_IPADDR3) \|	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) \|
	LS_64(udp->local_ipaddr[2], IRDMAQPC_LOCAL_IPADDR2));	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_192,	set_64bit_val(qp_ctx, IRDMA_BYTE_192,
	LS_64(udp->local_ipaddr[1], IRDMAQPC_LOCAL_IPADDR1) \|	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) \|
	LS_64(udp->local_ipaddr[0], IRDMAQPC_LOCAL_IPADDR0));	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_200,	set_64bit_val(qp_ctx, IRDMA_BYTE_200,
	LS_64(roce_info->t_high, IRDMAQPC_THIGH) \|	FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) \|
	LS_64(roce_info->t_low, IRDMAQPC_TLOW));	FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low));
	set_64bit_val(qp_ctx, IRDMA_BYTE_208,	set_64bit_val(qp_ctx, IRDMA_BYTE_208,
	LS_64(info->rem_endpoint_idx, IRDMAQPC_REMENDPOINTIDX));	FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));

	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "QP_HOST CTX WQE", qp_ctx,	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "QP_HOST CTX WQE", qp_ctx,
	IRDMA_QP_CTX_SIZE);	IRDMA_QP_CTX_SIZE);
Context not available.
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	hdr = LS_64(IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY,	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	IRDMA_CQPSQ_OPCODE) \|	IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

Context not available.

	set_64bit_val(wqe, IRDMA_BYTE_32, temp);	set_64bit_val(wqe, IRDMA_BYTE_32, temp);

	header = LS_64(info->entry_idx, IRDMA_CQPSQ_MLM_TABLEIDX) \|	header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) \|
	LS_64(IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

Context not available.
	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);	wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;
	header = LS_64(entry_idx, IRDMA_CQPSQ_MLM_TABLEIDX) \|	header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) \|
	LS_64(IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	LS_64(1, IRDMA_CQPSQ_MLM_FREEENTRY) \|	IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID) \|	FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) \|
	LS_64(ignore_ref_count, IRDMA_CQPSQ_MLM_IGNORE_REF_CNT);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) \|
		FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

Context not available.
	push_mode_en = 1;	push_mode_en = 1;
	push_idx = qp->push_idx;	push_idx = qp->push_idx;
	}	}
	qw0 = LS_64(qp->qp_uk.rq_wqe_size, IRDMAQPC_RQWQESIZE) \|	qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) \|
	LS_64(qp->rcv_tph_en, IRDMAQPC_RCVTPHEN) \|	FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) \|
	LS_64(qp->xmit_tph_en, IRDMAQPC_XMITTPHEN) \|	FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) \|
	LS_64(qp->rq_tph_en, IRDMAQPC_RQTPHEN) \|	FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) \|
	LS_64(qp->sq_tph_en, IRDMAQPC_SQTPHEN) \|	FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) \|
	LS_64(push_idx, IRDMAQPC_PPIDX) \|	FIELD_PREP(IRDMAQPC_PPIDX, push_idx) \|
	LS_64(push_mode_en, IRDMAQPC_PMENA);	FIELD_PREP(IRDMAQPC_PMENA, push_mode_en);

	set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);	set_64bit_val(qp_ctx, IRDMA_BYTE_8, qp->sq_pa);
	set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);	set_64bit_val(qp_ctx, IRDMA_BYTE_16, qp->rq_pa);

	qw3 = LS_64(qp->hw_rq_size, IRDMAQPC_RQSIZE) \|	qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) \|
	LS_64(qp->hw_sq_size, IRDMAQPC_SQSIZE);	FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size);
	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
	qw3 \|= LS_64(qp->src_mac_addr_idx, IRDMAQPC_GEN1_SRCMACADDRIDX);	qw3 \|= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX,
		qp->src_mac_addr_idx);
	set_64bit_val(qp_ctx, IRDMA_BYTE_136,	set_64bit_val(qp_ctx, IRDMA_BYTE_136,
	LS_64(info->send_cq_num, IRDMAQPC_TXCQNUM) \|	FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) \|
	LS_64(info->rcv_cq_num, IRDMAQPC_RXCQNUM));	FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num));
	set_64bit_val(qp_ctx, IRDMA_BYTE_168,	set_64bit_val(qp_ctx, IRDMA_BYTE_168,
	LS_64(info->qp_compl_ctx, IRDMAQPC_QPCOMPCTX));	FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx));
	set_64bit_val(qp_ctx, IRDMA_BYTE_176,	set_64bit_val(qp_ctx, IRDMA_BYTE_176,
	LS_64(qp->sq_tph_val, IRDMAQPC_SQTPHVAL) \|	FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) \|
	LS_64(qp->rq_tph_val, IRDMAQPC_RQTPHVAL) \|	FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) \|
	LS_64(qp->qs_handle, IRDMAQPC_QSHANDLE) \|	FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) \|
	LS_64(qp->ieq_qp, IRDMAQPC_EXCEPTION_LAN_QUEUE));	FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp));
	if (info->iwarp_info_valid) {	if (info->iwarp_info_valid) {
	qw0 \|= LS_64(iw->ddp_ver, IRDMAQPC_DDP_VER) \|	qw0 \|= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) \|
	LS_64(iw->rdmap_ver, IRDMAQPC_RDMAP_VER) \|	FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) \|
	LS_64(iw->dctcp_en, IRDMAQPC_DC_TCP_EN) \|	FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) \|
	LS_64(iw->ecn_en, IRDMAQPC_ECN_EN) \|	FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) \|
	LS_64(iw->ib_rd_en, IRDMAQPC_IBRDENABLE) \|	FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) \|
	LS_64(iw->pd_id >> 16, IRDMAQPC_PDIDXHI) \|	FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) \|
	LS_64(iw->err_rq_idx_valid, IRDMAQPC_ERR_RQ_IDX_VALID);	FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID,
	qw7 \|= LS_64(iw->pd_id, IRDMAQPC_PDIDX);	iw->err_rq_idx_valid);
	qw16 \|= LS_64(iw->err_rq_idx, IRDMAQPC_ERR_RQ_IDX) \|	qw7 \|= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id);
	LS_64(iw->rtomin, IRDMAQPC_RTOMIN);	qw16 \|= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) \|
		FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin);
	set_64bit_val(qp_ctx, IRDMA_BYTE_144,	set_64bit_val(qp_ctx, IRDMA_BYTE_144,
	LS_64(qp->q2_pa >> 8, IRDMAQPC_Q2ADDR) \|	FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) \|
	LS_64(info->stats_idx, IRDMAQPC_STAT_INDEX));	FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx));

	if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {	if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
	mac = LS_64_1(iw->mac_addr[5], 16) \|	mac = LS_64_1(iw->mac_addr[5], 16) \|
Context not available.
	}	}

	set_64bit_val(qp_ctx, IRDMA_BYTE_152,	set_64bit_val(qp_ctx, IRDMA_BYTE_152,
	mac \| LS_64(iw->last_byte_sent, IRDMAQPC_LASTBYTESENT));	mac \| FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent));
	set_64bit_val(qp_ctx, IRDMA_BYTE_160,	set_64bit_val(qp_ctx, IRDMA_BYTE_160,
	LS_64(iw->ord_size, IRDMAQPC_ORDSIZE) \|	FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) \|
	LS_64(irdma_sc_get_encoded_ird_size(iw->ird_size), IRDMAQPC_IRDSIZE) \|	FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) \|
	LS_64(iw->wr_rdresp_en, IRDMAQPC_WRRDRSPOK) \|	FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) \|
	LS_64(iw->rd_en, IRDMAQPC_RDOK) \|	FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) \|
	LS_64(iw->snd_mark_en, IRDMAQPC_SNDMARKERS) \|	FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) \|
	LS_64(iw->bind_en, IRDMAQPC_BINDEN) \|	FIELD_PREP(IRDMAQPC_BINDEN, iw->bind_en) \|
	LS_64(iw->fast_reg_en, IRDMAQPC_FASTREGEN) \|	FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) \|
	LS_64(iw->priv_mode_en, IRDMAQPC_PRIVEN) \|	FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) \|
	LS_64(info->stats_idx_valid, IRDMAQPC_USESTATSINSTANCE) \|	FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) \|
	LS_64(1, IRDMAQPC_IWARPMODE) \|	FIELD_PREP(IRDMAQPC_IWARPMODE, 1) \|
	LS_64(iw->rcv_mark_en, IRDMAQPC_RCVMARKERS) \|	FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) \|
	LS_64(iw->align_hdrs, IRDMAQPC_ALIGNHDRS) \|	FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) \|
	LS_64(iw->rcv_no_mpa_crc, IRDMAQPC_RCVNOMPACRC) \|	FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) \|
	LS_64(iw->rcv_mark_offset, IRDMAQPC_RCVMARKOFFSET) \|	FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset) \|
	LS_64(iw->snd_mark_offset, IRDMAQPC_SNDMARKOFFSET) \|	FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset) \|
	LS_64(iw->timely_en, IRDMAQPC_TIMELYENABLE));	FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en));
	}	}
	if (info->tcp_info_valid) {	if (info->tcp_info_valid) {
	qw0 \|= LS_64(tcp->ipv4, IRDMAQPC_IPV4) \|	qw0 \|= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) \|
	LS_64(tcp->no_nagle, IRDMAQPC_NONAGLE) \|	FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) \|
	LS_64(tcp->insert_vlan_tag, IRDMAQPC_INSERTVLANTAG) \|	FIELD_PREP(IRDMAQPC_INSERTVLANTAG,
	LS_64(tcp->time_stamp, IRDMAQPC_TIMESTAMP) \|	tcp->insert_vlan_tag) \|
	LS_64(tcp->cwnd_inc_limit, IRDMAQPC_LIMIT) \|	FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) \|
	LS_64(tcp->drop_ooo_seg, IRDMAQPC_DROPOOOSEG) \|	FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) \|
	LS_64(tcp->dup_ack_thresh, IRDMAQPC_DUPACK_THRESH);	FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) \|
		FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh);

	if (iw->ecn_en \|\| iw->dctcp_en) {	if (iw->ecn_en \|\| iw->dctcp_en) {
	tcp->tos &= ~ECN_CODE_PT_MASK;	tcp->tos &= ~ECN_CODE_PT_MASK;
	tcp->tos \|= ECN_CODE_PT_VAL;	tcp->tos \|= ECN_CODE_PT_VAL;
	}	}

	qw3 \|= LS_64(tcp->ttl, IRDMAQPC_TTL) \|	qw3 \|= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) \|
	LS_64(tcp->avoid_stretch_ack, IRDMAQPC_AVOIDSTRETCHACK) \|	FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) \|
	LS_64(tcp->tos, IRDMAQPC_TOS) \|	FIELD_PREP(IRDMAQPC_TOS, tcp->tos) \|
	LS_64(tcp->src_port, IRDMAQPC_SRCPORTNUM) \|	FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) \|
	LS_64(tcp->dst_port, IRDMAQPC_DESTPORTNUM);	FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port);
	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) {
	qw3 \|= LS_64(tcp->src_mac_addr_idx,	qw3 \|= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx);
	IRDMAQPC_GEN1_SRCMACADDRIDX);

	qp->src_mac_addr_idx = tcp->src_mac_addr_idx;	qp->src_mac_addr_idx = tcp->src_mac_addr_idx;
	}	}
	set_64bit_val(qp_ctx, IRDMA_BYTE_32,	set_64bit_val(qp_ctx, IRDMA_BYTE_32,
	LS_64(tcp->dest_ip_addr[2], IRDMAQPC_DESTIPADDR2) \|	FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) \|
	LS_64(tcp->dest_ip_addr[3], IRDMAQPC_DESTIPADDR3));	FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_40,	set_64bit_val(qp_ctx, IRDMA_BYTE_40,
	LS_64(tcp->dest_ip_addr[0], IRDMAQPC_DESTIPADDR0) \|	FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) \|
	LS_64(tcp->dest_ip_addr[1], IRDMAQPC_DESTIPADDR1));	FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_48,	set_64bit_val(qp_ctx, IRDMA_BYTE_48,
	LS_64(tcp->snd_mss, IRDMAQPC_SNDMSS) \|	FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) \|
	LS_64(tcp->syn_rst_handling, IRDMAQPC_SYN_RST_HANDLING) \|	FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) \|
	LS_64(tcp->vlan_tag, IRDMAQPC_VLANTAG) \|	FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) \|
	LS_64(tcp->arp_idx, IRDMAQPC_ARPIDX));	FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx));
	qw7 \|= LS_64(tcp->flow_label, IRDMAQPC_FLOWLABEL) \|	qw7 \|= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) \|
	LS_64(tcp->wscale, IRDMAQPC_WSCALE) \|	FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) \|
	LS_64(tcp->ignore_tcp_opt, IRDMAQPC_IGNORE_TCP_OPT) \|	FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT,
	LS_64(tcp->ignore_tcp_uns_opt,	tcp->ignore_tcp_opt) \|
	IRDMAQPC_IGNORE_TCP_UNS_OPT) \|	FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT,
	LS_64(tcp->tcp_state, IRDMAQPC_TCPSTATE) \|	tcp->ignore_tcp_uns_opt) \|
	LS_64(tcp->rcv_wscale, IRDMAQPC_RCVSCALE) \|	FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) \|
	LS_64(tcp->snd_wscale, IRDMAQPC_SNDSCALE);	FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) \|
		FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale);
	set_64bit_val(qp_ctx, IRDMA_BYTE_72,	set_64bit_val(qp_ctx, IRDMA_BYTE_72,
	LS_64(tcp->time_stamp_recent, IRDMAQPC_TIMESTAMP_RECENT) \|	FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) \|
	LS_64(tcp->time_stamp_age, IRDMAQPC_TIMESTAMP_AGE));	FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age));
	set_64bit_val(qp_ctx, IRDMA_BYTE_80,	set_64bit_val(qp_ctx, IRDMA_BYTE_80,
	LS_64(tcp->snd_nxt, IRDMAQPC_SNDNXT) \|	FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) \|
	LS_64(tcp->snd_wnd, IRDMAQPC_SNDWND));	FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd));
	set_64bit_val(qp_ctx, IRDMA_BYTE_88,	set_64bit_val(qp_ctx, IRDMA_BYTE_88,
	LS_64(tcp->rcv_nxt, IRDMAQPC_RCVNXT) \|	FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) \|
	LS_64(tcp->rcv_wnd, IRDMAQPC_RCVWND));	FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd));
	set_64bit_val(qp_ctx, IRDMA_BYTE_96,	set_64bit_val(qp_ctx, IRDMA_BYTE_96,
	LS_64(tcp->snd_max, IRDMAQPC_SNDMAX) \|	FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) \|
	LS_64(tcp->snd_una, IRDMAQPC_SNDUNA));	FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una));
	set_64bit_val(qp_ctx, IRDMA_BYTE_104,	set_64bit_val(qp_ctx, IRDMA_BYTE_104,
	LS_64(tcp->srtt, IRDMAQPC_SRTT) \|	FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) \|
	LS_64(tcp->rtt_var, IRDMAQPC_RTTVAR));	FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var));
	set_64bit_val(qp_ctx, IRDMA_BYTE_112,	set_64bit_val(qp_ctx, IRDMA_BYTE_112,
	LS_64(tcp->ss_thresh, IRDMAQPC_SSTHRESH) \|	FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) \|
	LS_64(tcp->cwnd, IRDMAQPC_CWND));	FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd));
	set_64bit_val(qp_ctx, IRDMA_BYTE_120,	set_64bit_val(qp_ctx, IRDMA_BYTE_120,
	LS_64(tcp->snd_wl1, IRDMAQPC_SNDWL1) \|	FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) \|
	LS_64(tcp->snd_wl2, IRDMAQPC_SNDWL2));	FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2));
	qw16 \|= LS_64(tcp->max_snd_window, IRDMAQPC_MAXSNDWND) \|	qw16 \|= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) \|
	LS_64(tcp->rexmit_thresh, IRDMAQPC_REXMIT_THRESH);	FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh);
	set_64bit_val(qp_ctx, IRDMA_BYTE_184,	set_64bit_val(qp_ctx, IRDMA_BYTE_184,
	LS_64(tcp->local_ipaddr[3], IRDMAQPC_LOCAL_IPADDR3) \|	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) \|
	LS_64(tcp->local_ipaddr[2], IRDMAQPC_LOCAL_IPADDR2));	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_192,	set_64bit_val(qp_ctx, IRDMA_BYTE_192,
	LS_64(tcp->local_ipaddr[1], IRDMAQPC_LOCAL_IPADDR1) \|	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) \|
	LS_64(tcp->local_ipaddr[0], IRDMAQPC_LOCAL_IPADDR0));	FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0]));
	set_64bit_val(qp_ctx, IRDMA_BYTE_200,	set_64bit_val(qp_ctx, IRDMA_BYTE_200,
	LS_64(iw->t_high, IRDMAQPC_THIGH) \|	FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) \|
	LS_64(iw->t_low, IRDMAQPC_TLOW));	FIELD_PREP(IRDMAQPC_TLOW, iw->t_low));
	set_64bit_val(qp_ctx, IRDMA_BYTE_208,	set_64bit_val(qp_ctx, IRDMA_BYTE_208,
	LS_64(info->rem_endpoint_idx, IRDMAQPC_REMENDPOINTIDX));	FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx));
	}	}

	set_64bit_val(qp_ctx, IRDMA_BYTE_0, qw0);	set_64bit_val(qp_ctx, IRDMA_BYTE_0, qw0);
Context not available.
	u64 hdr;	u64 hdr;
	enum irdma_page_size page_size;	enum irdma_page_size page_size;

		if (!info->total_len && !info->all_memory)
		return -EINVAL;

	if (info->page_size == 0x40000000)	if (info->page_size == 0x40000000)
	page_size = IRDMA_PAGE_SIZE_1G;	page_size = IRDMA_PAGE_SIZE_1G;
	else if (info->page_size == 0x200000)	else if (info->page_size == 0x200000)
Context not available.

	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) \|	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) \|
	LS_64(info->total_len, IRDMA_CQPSQ_STAG_STAGLEN));	FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(info->stag_idx, IRDMA_CQPSQ_STAG_IDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
	set_64bit_val(wqe, IRDMA_BYTE_40,	set_64bit_val(wqe, IRDMA_BYTE_40,
	LS_64(info->hmc_fcn_index, IRDMA_CQPSQ_STAG_HMCFNIDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index));

	if (info->chunk_size)	if (info->chunk_size)
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	LS_64(info->first_pm_pbl_idx, IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx));

	hdr = LS_64(IRDMA_CQP_OP_ALLOC_STAG, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) \|
	LS_64(1, IRDMA_CQPSQ_STAG_MR) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) \|
	LS_64(info->access_rights, IRDMA_CQPSQ_STAG_ARIGHTS) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) \|
	LS_64(info->chunk_size, IRDMA_CQPSQ_STAG_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) \|
	LS_64(page_size, IRDMA_CQPSQ_STAG_HPAGESIZE) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) \|
	LS_64(info->remote_access, IRDMA_CQPSQ_STAG_REMACCENABLED) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) \|
	LS_64(info->use_hmc_fcn_index, IRDMA_CQPSQ_STAG_USEHMCFNIDX) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) \|
	LS_64(info->use_pf_rid, IRDMA_CQPSQ_STAG_USEPFRID) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	u8 addr_type;	u8 addr_type;
	enum irdma_page_size page_size;	enum irdma_page_size page_size;

		if (!info->total_len && !info->all_memory)
		return -EINVAL;

	if (info->page_size == 0x40000000)	if (info->page_size == 0x40000000)
	page_size = IRDMA_PAGE_SIZE_1G;	page_size = IRDMA_PAGE_SIZE_1G;
	else if (info->page_size == 0x200000)	else if (info->page_size == 0x200000)
Context not available.
	(info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ?	(info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ?
	info->va : fbo));	info->va : fbo));
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(info->total_len, IRDMA_CQPSQ_STAG_STAGLEN) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) \|
	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(info->stag_key, IRDMA_CQPSQ_STAG_KEY) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) \|
	LS_64(info->stag_idx, IRDMA_CQPSQ_STAG_IDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));
	if (!info->chunk_size)	if (!info->chunk_size)
	set_64bit_val(wqe, IRDMA_BYTE_32, info->reg_addr_pa);	set_64bit_val(wqe, IRDMA_BYTE_32, info->reg_addr_pa);
	else	else
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	LS_64(info->first_pm_pbl_index, IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index));

	set_64bit_val(wqe, IRDMA_BYTE_40, info->hmc_fcn_index);	set_64bit_val(wqe, IRDMA_BYTE_40, info->hmc_fcn_index);

	addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0;	addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0;
	hdr = LS_64(IRDMA_CQP_OP_REG_MR, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) \|
	LS_64(1, IRDMA_CQPSQ_STAG_MR) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) \|
	LS_64(info->chunk_size, IRDMA_CQPSQ_STAG_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) \|
	LS_64(page_size, IRDMA_CQPSQ_STAG_HPAGESIZE) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) \|
	LS_64(info->access_rights, IRDMA_CQPSQ_STAG_ARIGHTS) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) \|
	LS_64(remote_access, IRDMA_CQPSQ_STAG_REMACCENABLED) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) \|
	LS_64(addr_type, IRDMA_CQPSQ_STAG_VABASEDTO) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) \|
	LS_64(info->use_hmc_fcn_index, IRDMA_CQPSQ_STAG_USEHMCFNIDX) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) \|
	LS_64(info->use_pf_rid, IRDMA_CQPSQ_STAG_USEPFRID) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(info->stag_idx, IRDMA_CQPSQ_STAG_IDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx));

	hdr = LS_64(IRDMA_CQP_OP_DEALLOC_STAG, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) \|
	LS_64(info->mr, IRDMA_CQPSQ_STAG_MR) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));	FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(info->mw_stag_index, IRDMA_CQPSQ_STAG_IDX));	FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index));

	hdr = LS_64(IRDMA_CQP_OP_ALLOC_STAG, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) \|
	LS_64(info->mw_wide, IRDMA_CQPSQ_STAG_MWTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) \|
	LS_64(info->mw1_bind_dont_vldt_key,	FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY,
	IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY) \|	info->mw1_bind_dont_vldt_key) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	u64 temp, hdr;	u64 temp, hdr;
	__le64 *wqe;	__le64 *wqe;
	u32 wqe_idx;	u32 wqe_idx;
		u16 quanta = IRDMA_QP_WQE_MIN_QUANTA;
	enum irdma_page_size page_size;	enum irdma_page_size page_size;
	struct irdma_post_sq_info sq_info = {0};	struct irdma_post_sq_info sq_info = {0};

Context not available.
	sq_info.signaled = info->signaled;	sq_info.signaled = info->signaled;
	sq_info.push_wqe = info->push_wqe;	sq_info.push_wqe = info->push_wqe;

	wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx,	wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, &quanta, 0, &sq_info);
	IRDMA_QP_WQE_MIN_QUANTA, 0, &sq_info);
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	irdma_clr_wqes(&qp->qp_uk, wqe_idx);

	qp->qp_uk.sq_wrtrk_array[wqe_idx].signaled = info->signaled;	qp->qp_uk.sq_wrtrk_array[wqe_idx].signaled = info->signaled;
	irdma_debug(qp->dev, IRDMA_DEBUG_MR,	irdma_debug(qp->dev, IRDMA_DEBUG_MR,
	"wr_id[%llxh] wqe_idx[%04d] location[%p]\n", (unsigned long long)info->wr_id,	"wr_id[%llxh] wqe_idx[%04d] location[%p]\n", (unsigned long long)info->wr_id,
Context not available.
	(uintptr_t)info->va : info->fbo;	(uintptr_t)info->va : info->fbo;
	set_64bit_val(wqe, IRDMA_BYTE_0, temp);	set_64bit_val(wqe, IRDMA_BYTE_0, temp);

	temp = RS_64(info->first_pm_pbl_index >> 16, IRDMAQPSQ_FIRSTPMPBLIDXHI);	temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI,
		info->first_pm_pbl_index >> 16);
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(temp, IRDMAQPSQ_FIRSTPMPBLIDXHI) \|	FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) \|
	LS_64(info->reg_addr_pa >> IRDMAQPSQ_PBLADDR_S, IRDMAQPSQ_PBLADDR));	FIELD_PREP(IRDMAQPSQ_PBLADDR, info->reg_addr_pa >> IRDMA_HW_PAGE_SHIFT));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	info->total_len \|	info->total_len \|
	LS_64(info->first_pm_pbl_index, IRDMAQPSQ_FIRSTPMPBLIDXLO));	FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index));

	hdr = LS_64(info->stag_key, IRDMAQPSQ_STAGKEY) \|	hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) \|
	LS_64(info->stag_idx, IRDMAQPSQ_STAGINDEX) \|	FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) \|
	LS_64(IRDMAQP_OP_FAST_REGISTER, IRDMAQPSQ_OPCODE) \|	FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) \|
	LS_64(info->chunk_size, IRDMAQPSQ_LPBLSIZE) \|	FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) \|
	LS_64(page_size, IRDMAQPSQ_HPAGESIZE) \|	FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) \|
	LS_64(info->access_rights, IRDMAQPSQ_STAGRIGHTS) \|	FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) \|
	LS_64(info->addr_type, IRDMAQPSQ_VABASEDTO) \|	FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) \|
	LS_64((sq_info.push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) \|	FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) \|
	LS_64(info->read_fence, IRDMAQPSQ_READFENCE) \|	FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) \|
	LS_64(info->local_fence, IRDMAQPSQ_LOCALFENCE) \|	FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) \|
	LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) \|	FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);

	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "FAST_REG WQE", wqe,	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "FAST_REG WQE", wqe,
	IRDMA_QP_WQE_MIN_SIZE);	IRDMA_QP_WQE_MIN_SIZE);
	if (sq_info.push_wqe) {	if (sq_info.push_wqe)
	irdma_qp_push_wqe(&qp->qp_uk, wqe, IRDMA_QP_WQE_MIN_QUANTA,	irdma_qp_push_wqe(&qp->qp_uk, wqe, quanta, wqe_idx, post_sq);
	wqe_idx, post_sq);	else if (post_sq)
	} else {	irdma_uk_qp_post_wr(&qp->qp_uk);
	if (post_sq)
	irdma_uk_qp_post_wr(&qp->qp_uk);
	}

	return 0;	return 0;
	}	}
Context not available.

	wqe = qp_uk->sq_base[1].elem;	wqe = qp_uk->sq_base[1].elem;

	hdr = LS_64(IRDMAQP_OP_NOP, IRDMAQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) \|
	LS_64(1, IRDMAQPSQ_LOCALFENCE) \|	FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	IRDMA_QP_WQE_MIN_SIZE);	IRDMA_QP_WQE_MIN_SIZE);

	wqe = qp_uk->sq_base[2].elem;	wqe = qp_uk->sq_base[2].elem;
	hdr = LS_64(IRDMAQP_OP_GEN_RTS_AE, IRDMAQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	* @size: size of lsmm buffer	* @size: size of lsmm buffer
	* @stag: stag of lsmm buffer	* @stag: stag of lsmm buffer
	*/	*/
	int	void
	irdma_sc_send_lsmm(struct irdma_sc_qp qp, void lsmm_buf, u32 size,	irdma_sc_send_lsmm(struct irdma_sc_qp qp, void lsmm_buf, u32 size,
	irdma_stag stag)	irdma_stag stag)
	{	{
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)lsmm_buf);	set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)lsmm_buf);
	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(size, IRDMAQPSQ_GEN1_FRAG_LEN) \|	FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) \|
	LS_64(stag, IRDMAQPSQ_GEN1_FRAG_STAG));	FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag));
	} else {	} else {
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(size, IRDMAQPSQ_FRAG_LEN) \|	FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) \|
	LS_64(stag, IRDMAQPSQ_FRAG_STAG) \|	FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID));	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
	}	}
	set_64bit_val(wqe, IRDMA_BYTE_16, 0);	set_64bit_val(wqe, IRDMA_BYTE_16, 0);

	hdr = LS_64(IRDMAQP_OP_RDMA_SEND, IRDMAQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) \|
	LS_64(1, IRDMAQPSQ_STREAMMODE) \|	FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) \|
	LS_64(1, IRDMAQPSQ_WAITFORRCVPDU) \|	FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.

	if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)	if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
	irdma_sc_gen_rts_ae(qp);	irdma_sc_gen_rts_ae(qp);

	return 0;
	}	}

	/**	/**
Context not available.
	* @lsmm_buf: buffer with lsmm message	* @lsmm_buf: buffer with lsmm message
	* @size: size of lsmm buffer	* @size: size of lsmm buffer
	*/	*/
	int	void
	irdma_sc_send_lsmm_nostag(struct irdma_sc_qp qp, void lsmm_buf, u32 size)	irdma_sc_send_lsmm_nostag(struct irdma_sc_qp qp, void lsmm_buf, u32 size)
	{	{
	__le64 *wqe;	__le64 *wqe;
Context not available.

	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1)	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1)
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(size, IRDMAQPSQ_GEN1_FRAG_LEN));	FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size));
	else	else
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(size, IRDMAQPSQ_FRAG_LEN) \|	FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID));	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
	set_64bit_val(wqe, IRDMA_BYTE_16, 0);	set_64bit_val(wqe, IRDMA_BYTE_16, 0);

	hdr = LS_64(IRDMAQP_OP_RDMA_SEND, IRDMAQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) \|
	LS_64(1, IRDMAQPSQ_STREAMMODE) \|	FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) \|
	LS_64(1, IRDMAQPSQ_WAITFORRCVPDU) \|	FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);

	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE", wqe,	irdma_debug_buf(qp->dev, IRDMA_DEBUG_WQE, "SEND_LSMM_NOSTAG WQE", wqe,
	IRDMA_QP_WQE_MIN_SIZE);	IRDMA_QP_WQE_MIN_SIZE);

	return 0;
	}	}

	/**	/**
Context not available.
	* @qp: sc qp struct	* @qp: sc qp struct
	* @read: Do read0 or write0	* @read: Do read0 or write0
	*/	*/
	int	void
	irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read)	irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read)
	{	{
	__le64 *wqe;	__le64 *wqe;
Context not available.
	if (read) {	if (read) {
	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(0xabcd, IRDMAQPSQ_GEN1_FRAG_STAG));	FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd));
	} else {	} else {
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	(u64)0xabcd \| LS_64(qp->qp_uk.swqe_polarity,	(u64)0xabcd \| FIELD_PREP(IRDMAQPSQ_VALID,
	IRDMAQPSQ_VALID));	qp->qp_uk.swqe_polarity));
	}	}
	hdr = LS_64(0x1234, IRDMAQPSQ_REMSTAG) \|	hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) \|
	LS_64(IRDMAQP_OP_RDMA_READ, IRDMAQPSQ_OPCODE) \|	FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);

	} else {	} else {
	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {	if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) {
	set_64bit_val(wqe, IRDMA_BYTE_8, 0);	set_64bit_val(wqe, IRDMA_BYTE_8, 0);
	} else {	} else {
	set_64bit_val(wqe, IRDMA_BYTE_8,	set_64bit_val(wqe, IRDMA_BYTE_8,
	LS_64(qp->qp_uk.swqe_polarity,	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity));
	IRDMAQPSQ_VALID));
	}	}
	hdr = LS_64(IRDMAQP_OP_RDMA_WRITE, IRDMAQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) \|
	LS_64(qp->qp_uk.swqe_polarity, IRDMAQPSQ_VALID);	FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity);
	}	}

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */
Context not available.

	if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)	if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE)
	irdma_sc_gen_rts_ae(qp);	irdma_sc_gen_rts_ae(qp);

	return 0;
	}	}

	/**	/**
Context not available.
	vsi->mtu = info->params->mtu;	vsi->mtu = info->params->mtu;
	vsi->exception_lan_q = info->exception_lan_q;	vsi->exception_lan_q = info->exception_lan_q;
	vsi->vsi_idx = info->pf_data_vsi_num;	vsi->vsi_idx = info->pf_data_vsi_num;
	if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
	vsi->fcn_id = info->dev->hmc_fn_id;

	irdma_set_qos_info(vsi, info->params);	irdma_set_qos_info(vsi, info->params);
	for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {	for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) {
Context not available.
	}	}

	/**	/**
	* irdma_get_fcn_id - Return the function id	* irdma_get_stats_idx - Return stats index
	* @vsi: pointer to the vsi	* @vsi: pointer to the vsi
	*/	*/
	static u8 irdma_get_fcn_id(struct irdma_sc_vsi *vsi){	static u8 irdma_get_stats_idx(struct irdma_sc_vsi *vsi){
	struct irdma_stats_inst_info stats_info = {0};	struct irdma_stats_inst_info stats_info = {0};
	struct irdma_sc_dev *dev = vsi->dev;	struct irdma_sc_dev *dev = vsi->dev;
	u8 fcn_id = IRDMA_INVALID_FCN_ID;
	u8 start_idx, max_stats, i;

	if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {	if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
	if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE,	if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE,
	&stats_info))	&stats_info))
	return stats_info.stats_idx;	return stats_info.stats_idx;
	}	}

	start_idx = 1;	return IRDMA_INVALID_STATS_IDX;
	max_stats = 16;
	for (i = start_idx; i < max_stats; i++)
	if (!dev->fcn_id_array[i]) {
	fcn_id = i;
	dev->fcn_id_array[i] = true;
	break;
	}

	return fcn_id;
	}	}

	/**	/**
Context not available.
	irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,	irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,
	struct irdma_vsi_stats_info *info)	struct irdma_vsi_stats_info *info)
	{	{
	u8 fcn_id = info->fcn_id;
	struct irdma_dma_mem *stats_buff_mem;	struct irdma_dma_mem *stats_buff_mem;

	vsi->pestat = info->pestat;	vsi->pestat = info->pestat;
	vsi->pestat->hw = vsi->dev->hw;	vsi->pestat->hw = vsi->dev->hw;
	vsi->pestat->vsi = vsi;	vsi->pestat->vsi = vsi;

	stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem;	stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem;
	stats_buff_mem->size = IRDMA_GATHER_STATS_BUF_SIZE * 2;	stats_buff_mem->size = IRDMA_GATHER_STATS_BUF_SIZE * 2;
	stats_buff_mem->va = irdma_allocate_dma_mem(vsi->pestat->hw,	stats_buff_mem->va = irdma_allocate_dma_mem(vsi->pestat->hw,
Context not available.
	IRDMA_GATHER_STATS_BUF_SIZE);	IRDMA_GATHER_STATS_BUF_SIZE);

	irdma_hw_stats_start_timer(vsi);	irdma_hw_stats_start_timer(vsi);
	if (info->alloc_fcn_id)
	fcn_id = irdma_get_fcn_id(vsi);
	if (fcn_id == IRDMA_INVALID_FCN_ID)
	goto stats_error;

	vsi->stats_fcn_id_alloc = info->alloc_fcn_id;
	vsi->fcn_id = fcn_id;
	if (info->alloc_fcn_id) {
	vsi->pestat->gather_info.use_stats_inst = true;
	vsi->pestat->gather_info.stats_inst_index = fcn_id;
	}

	return 0;	/* when stat allocation is not required default to fcn_id. */
		vsi->stats_idx = info->fcn_id;
		if (info->alloc_stats_inst) {
		u8 stats_idx = irdma_get_stats_idx(vsi);

	stats_error:	if (stats_idx != IRDMA_INVALID_STATS_IDX) {
	irdma_free_dma_mem(vsi->pestat->hw, stats_buff_mem);	vsi->stats_inst_alloc = true;
		vsi->stats_idx = stats_idx;
		vsi->pestat->gather_info.use_stats_inst = true;
		vsi->pestat->gather_info.stats_inst_index = stats_idx;
		}
		}

	return -EIO;	return 0;
	}	}

	/**	/**
Context not available.
	irdma_vsi_stats_free(struct irdma_sc_vsi *vsi)	irdma_vsi_stats_free(struct irdma_sc_vsi *vsi)
	{	{
	struct irdma_stats_inst_info stats_info = {0};	struct irdma_stats_inst_info stats_info = {0};
	u8 fcn_id = vsi->fcn_id;
	struct irdma_sc_dev *dev = vsi->dev;	struct irdma_sc_dev *dev = vsi->dev;

	if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) {	if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) {
	if (vsi->stats_fcn_id_alloc) {	if (vsi->stats_inst_alloc) {
	stats_info.stats_idx = vsi->fcn_id;	stats_info.stats_idx = vsi->stats_idx;
	irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE,	irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE,
	&stats_info);	&stats_info);
	}	}
	} else {
	if (vsi->stats_fcn_id_alloc &&
	fcn_id < vsi->dev->hw_attrs.max_stat_inst)
	vsi->dev->fcn_id_array[fcn_id] = false;
	}	}

	if (!vsi->pestat)	if (!vsi->pestat)
	return;	return;

	irdma_hw_stats_stop_timer(vsi);	irdma_hw_stats_stop_timer(vsi);
	irdma_free_dma_mem(vsi->pestat->hw,	irdma_free_dma_mem(vsi->pestat->hw,
	&vsi->pestat->gather_info.stats_buff_mem);	&vsi->pestat->gather_info.stats_buff_mem);
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_40,	set_64bit_val(wqe, IRDMA_BYTE_40,
	LS_64(info->hmc_fcn_index, IRDMA_CQPSQ_STATS_HMC_FCN_INDEX));	FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index));
	set_64bit_val(wqe, IRDMA_BYTE_32, info->stats_buff_mem.pa);	set_64bit_val(wqe, IRDMA_BYTE_32, info->stats_buff_mem.pa);

	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_STATS_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) \|
	LS_64(info->use_stats_inst, IRDMA_CQPSQ_STATS_USE_INST) \|	FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) \|
	LS_64(info->stats_inst_index, IRDMA_CQPSQ_STATS_INST_INDEX) \|	FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX,
	LS_64(info->use_hmc_fcn_index,	info->stats_inst_index) \|
	IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX) \|	FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
	LS_64(IRDMA_CQP_OP_GATHER_STATS, IRDMA_CQPSQ_STATS_OP);	info->use_hmc_fcn_index) \|
		FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, temp);	set_64bit_val(wqe, IRDMA_BYTE_24, temp);
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_40,	set_64bit_val(wqe, IRDMA_BYTE_40,
	LS_64(info->hmc_fn_id, IRDMA_CQPSQ_STATS_HMC_FCN_INDEX));	FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id));
	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_STATS_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) \|
	LS_64(alloc, IRDMA_CQPSQ_STATS_ALLOC_INST) \|	FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) \|
	LS_64(info->use_hmc_fcn_index, IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX) \|	FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX,
	LS_64(info->stats_idx, IRDMA_CQPSQ_STATS_INST_INDEX) \|	info->use_hmc_fcn_index) \|
	LS_64(IRDMA_CQP_OP_MANAGE_STATS, IRDMA_CQPSQ_STATS_OP);	FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) \|
		FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

Context not available.

	set_64bit_val(wqe, IRDMA_BYTE_0, temp);	set_64bit_val(wqe, IRDMA_BYTE_0, temp);
	set_64bit_val(wqe, IRDMA_BYTE_40,	set_64bit_val(wqe, IRDMA_BYTE_40,
	LS_64(info->cnp_up_override, IRDMA_CQPSQ_UP_CNPOVERRIDE) \|	FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) \|
	LS_64(info->hmc_fcn_idx, IRDMA_CQPSQ_UP_HMCFCNIDX));	FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx));

	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_UP_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) \|
	LS_64(info->use_vlan, IRDMA_CQPSQ_UP_USEVLAN) \|	FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) \|
	LS_64(info->use_cnp_up_override, IRDMA_CQPSQ_UP_USEOVERRIDE) \|	FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE,
	LS_64(IRDMA_CQP_OP_UP_MAP, IRDMA_CQPSQ_UP_OP);	info->use_cnp_up_override) \|
		FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, temp);	set_64bit_val(wqe, IRDMA_BYTE_24, temp);
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_32,	set_64bit_val(wqe, IRDMA_BYTE_32,
	LS_64(info->vsi, IRDMA_CQPSQ_WS_VSI) \|	FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) \|
	LS_64(info->weight, IRDMA_CQPSQ_WS_WEIGHT));	FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight));

	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_WS_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) \|
	LS_64(node_op, IRDMA_CQPSQ_WS_NODEOP) \|	FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) \|
	LS_64(info->enable, IRDMA_CQPSQ_WS_ENABLENODE) \|	FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) \|
	LS_64(info->type_leaf, IRDMA_CQPSQ_WS_NODETYPE) \|	FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) \|
	LS_64(info->prio_type, IRDMA_CQPSQ_WS_PRIOTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) \|
	LS_64(info->tc, IRDMA_CQPSQ_WS_TC) \|	FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) \|
	LS_64(IRDMA_CQP_OP_WORK_SCHED_NODE, IRDMA_CQPSQ_WS_OP) \|	FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) \|
	LS_64(info->parent_id, IRDMA_CQPSQ_WS_PARENTID) \|	FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) \|
	LS_64(info->id, IRDMA_CQPSQ_WS_NODEID);	FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, temp);	set_64bit_val(wqe, IRDMA_BYTE_24, temp);
Context not available.

	if (info->userflushcode) {	if (info->userflushcode) {
	if (flush_rq)	if (flush_rq)
	temp \|= LS_64(info->rq_minor_code, IRDMA_CQPSQ_FWQE_RQMNERR) \|	temp \|= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR,
	LS_64(info->rq_major_code, IRDMA_CQPSQ_FWQE_RQMJERR);	info->rq_minor_code) \|
		FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR,
		info->rq_major_code);
	if (flush_sq)	if (flush_sq)
	temp \|= LS_64(info->sq_minor_code, IRDMA_CQPSQ_FWQE_SQMNERR) \|	temp \|= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR,
	LS_64(info->sq_major_code, IRDMA_CQPSQ_FWQE_SQMJERR);	info->sq_minor_code) \|
		FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR,
		info->sq_major_code);
	}	}
	set_64bit_val(wqe, IRDMA_BYTE_16, temp);	set_64bit_val(wqe, IRDMA_BYTE_16, temp);

	temp = (info->generate_ae) ?	temp = (info->generate_ae) ?
	info->ae_code \| LS_64(info->ae_src, IRDMA_CQPSQ_FWQE_AESOURCE) : 0;	info->ae_code \| FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
		info->ae_src) : 0;
	set_64bit_val(wqe, IRDMA_BYTE_8, temp);	set_64bit_val(wqe, IRDMA_BYTE_8, temp);

	hdr = qp->qp_uk.qp_id \|	hdr = qp->qp_uk.qp_id \|
	LS_64(IRDMA_CQP_OP_FLUSH_WQES, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) \|
	LS_64(info->generate_ae, IRDMA_CQPSQ_FWQE_GENERATE_AE) \|	FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) \|
	LS_64(info->userflushcode, IRDMA_CQPSQ_FWQE_USERFLCODE) \|	FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) \|
	LS_64(flush_sq, IRDMA_CQPSQ_FWQE_FLUSHSQ) \|	FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) \|
	LS_64(flush_rq, IRDMA_CQPSQ_FWQE_FLUSHRQ) \|	FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	temp = info->ae_code \| LS_64(info->ae_src, IRDMA_CQPSQ_FWQE_AESOURCE);	temp = info->ae_code \| FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE,
		info->ae_src);
	set_64bit_val(wqe, IRDMA_BYTE_8, temp);	set_64bit_val(wqe, IRDMA_BYTE_8, temp);

	hdr = qp->qp_uk.qp_id \| LS_64(IRDMA_CQP_OP_GEN_AE, IRDMA_CQPSQ_OPCODE) \|	hdr = qp->qp_uk.qp_id \| FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	LS_64(1, IRDMA_CQPSQ_FWQE_GENERATE_AE) \|	IRDMA_CQP_OP_GEN_AE) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.

	set_64bit_val(wqe, IRDMA_BYTE_16, info->buf_pa);	set_64bit_val(wqe, IRDMA_BYTE_16, info->buf_pa);

	hdr = LS_64(info->qp_id, IRDMA_CQPSQ_UCTX_QPID) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) \|
	LS_64(IRDMA_CQP_OP_UPLOAD_CONTEXT, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) \|
	LS_64(info->qp_type, IRDMA_CQPSQ_UCTX_QPTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) \|
	LS_64(info->raw_format, IRDMA_CQPSQ_UCTX_RAWFORMAT) \|	FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) \|
	LS_64(info->freeze_qp, IRDMA_CQPSQ_UCTX_FREEZEQP) \|	FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_16, info->qs_handle);	set_64bit_val(wqe, IRDMA_BYTE_16, info->qs_handle);
	hdr = LS_64(info->push_idx, IRDMA_CQPSQ_MPP_PPIDX) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) \|
	LS_64(info->push_page_type, IRDMA_CQPSQ_MPP_PPTYPE) \|	FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) \|
	LS_64(IRDMA_CQP_OP_MANAGE_PUSH_PAGES, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID) \|	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) \|
	LS_64(info->free_page, IRDMA_CQPSQ_MPP_FREE_PAGE);	FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	hdr = LS_64(qp->qp_uk.qp_id, IRDMA_CQPSQ_SUSPENDQP_QPID) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) \|
	LS_64(IRDMA_CQP_OP_SUSPEND_QP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(qp->qs_handle, IRDMA_CQPSQ_RESUMEQP_QSHANDLE));	FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle));

	hdr = LS_64(qp->qp_uk.qp_id, IRDMA_CQPSQ_RESUMEQP_QPID) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) \|
	LS_64(IRDMA_CQP_OP_RESUME_QP, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size);	set_64bit_val(wqe, IRDMA_BYTE_0, cq->cq_uk.cq_size);
	set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));	set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(cq->shadow_read_threshold,	FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold));
	IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
	set_64bit_val(wqe, IRDMA_BYTE_32, (cq->virtual_map ? 0 : cq->cq_pa));	set_64bit_val(wqe, IRDMA_BYTE_32, (cq->virtual_map ? 0 : cq->cq_pa));
	set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);	set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	LS_64((cq->virtual_map ? cq->first_pm_pbl_idx : 0),	FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, (cq->virtual_map ? cq->first_pm_pbl_idx : 0)));
	IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX));
	set_64bit_val(wqe, IRDMA_BYTE_56,	set_64bit_val(wqe, IRDMA_BYTE_56,
	LS_64(cq->tph_val, IRDMA_CQPSQ_TPHVAL) \|	FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) \|
	LS_64(cq->vsi->vsi_idx, IRDMA_CQPSQ_VSIIDX));	FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));

	hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) \|	hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) \|
	FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),	FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),
	IRDMA_CQPSQ_CQ_CEQID) \|	IRDMA_CQPSQ_CQ_CEQID) \|
	LS_64(IRDMA_CQP_OP_CREATE_CQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) \|
	LS_64(cq->pbl_chunk_size, IRDMA_CQPSQ_CQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) \|
	LS_64(check_overflow, IRDMA_CQPSQ_CQ_CHKOVERFLOW) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) \|
	LS_64(cq->virtual_map, IRDMA_CQPSQ_CQ_VIRTMAP) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) \|
	LS_64(cq->ceqe_mask, IRDMA_CQPSQ_CQ_ENCEQEMASK) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) \|
	LS_64(cq->ceq_id_valid, IRDMA_CQPSQ_CQ_CEQIDVALID) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) \|
	LS_64(cq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) \|
	LS_64(cq->cq_uk.avoid_mem_cflct, IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	cq->cq_uk.avoid_mem_cflct) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	hdr = cq->cq_uk.cq_id \|	hdr = cq->cq_uk.cq_id \|
	FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),	FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0),
	IRDMA_CQPSQ_CQ_CEQID) \|	IRDMA_CQPSQ_CQ_CEQID) \|
	LS_64(IRDMA_CQP_OP_DESTROY_CQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) \|
	LS_64(cq->pbl_chunk_size, IRDMA_CQPSQ_CQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) \|
	LS_64(cq->virtual_map, IRDMA_CQPSQ_CQ_VIRTMAP) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) \|
	LS_64(cq->ceqe_mask, IRDMA_CQPSQ_CQ_ENCEQEMASK) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) \|
	LS_64(cq->ceq_id_valid, IRDMA_CQPSQ_CQ_CEQIDVALID) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) \|
	LS_64(cq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) \|
	LS_64(cq->cq_uk.avoid_mem_cflct, IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_0, info->cq_size);	set_64bit_val(wqe, IRDMA_BYTE_0, info->cq_size);
	set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));	set_64bit_val(wqe, IRDMA_BYTE_8, RS_64_1(cq, 1));
	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(info->shadow_read_threshold,	FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold));
	IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
	set_64bit_val(wqe, IRDMA_BYTE_32, info->cq_pa);	set_64bit_val(wqe, IRDMA_BYTE_32, info->cq_pa);
	set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);	set_64bit_val(wqe, IRDMA_BYTE_40, cq->shadow_area_pa);
	set_64bit_val(wqe, IRDMA_BYTE_48, info->first_pm_pbl_idx);	set_64bit_val(wqe, IRDMA_BYTE_48, info->first_pm_pbl_idx);
	set_64bit_val(wqe, IRDMA_BYTE_56,	set_64bit_val(wqe, IRDMA_BYTE_56,
	LS_64(cq->tph_val, IRDMA_CQPSQ_TPHVAL) \|	FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) \|
	LS_64(cq->vsi->vsi_idx, IRDMA_CQPSQ_VSIIDX));	FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx));

	hdr = cq->cq_uk.cq_id \|	hdr = cq->cq_uk.cq_id \|
	LS_64(IRDMA_CQP_OP_MODIFY_CQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) \|
	LS_64(info->cq_resize, IRDMA_CQPSQ_CQ_CQRESIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) \|
	LS_64(info->pbl_chunk_size, IRDMA_CQPSQ_CQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) \|
	LS_64(info->check_overflow, IRDMA_CQPSQ_CQ_CHKOVERFLOW) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) \|
	LS_64(info->virtual_map, IRDMA_CQPSQ_CQ_VIRTMAP) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) \|
	LS_64(cq->ceqe_mask, IRDMA_CQPSQ_CQ_ENCEQEMASK) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) \|
	LS_64(cq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) \|
	LS_64(cq->cq_uk.avoid_mem_cflct, IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT,
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	cq->cq_uk.avoid_mem_cflct) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	* @dev: sc device struct	* @dev: sc device struct
	*/	*/
	void	void
	irdma_check_cqp_progress(struct irdma_cqp_timeout timeout, struct irdma_sc_dev dev)	irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout,
		struct irdma_sc_dev *dev)
	{	{
	if (timeout->compl_cqp_cmds != dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]) {	if (timeout->compl_cqp_cmds != dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS]) {
	timeout->compl_cqp_cmds = dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS];	timeout->compl_cqp_cmds = dev->cqp_cmd_stats[IRDMA_OP_CMPL_CMDS];
	timeout->count = 0;	timeout->count = 0;
	} else {	} else if (timeout->compl_cqp_cmds !=
	if (dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS] !=	dev->cqp_cmd_stats[IRDMA_OP_REQ_CMDS]) {
	timeout->compl_cqp_cmds)	timeout->count++;
	timeout->count++;
	}	}
	}	}

Context not available.
	u32 tail, u32 error)	u32 tail, u32 error)
	{	{
	*val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]);	*val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]);
	tail = RS_32(val, IRDMA_CQPTAIL_WQTAIL);	tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, val);
	error = RS_32(val, IRDMA_CQPTAIL_CQP_OP_ERR);	error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, val);
	}	}

	/**	/**
Context not available.

	switch (rsrc_idx) {	switch (rsrc_idx) {
	case IRDMA_HMC_IW_QP:	case IRDMA_HMC_IW_QP:
	obj_info[rsrc_idx].cnt = (u32)RS_64(temp, IRDMA_COMMIT_FPM_QPCNT);	obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp);
	break;	break;
	case IRDMA_HMC_IW_CQ:	case IRDMA_HMC_IW_CQ:
	obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT);	obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT);
	break;	break;
	case IRDMA_HMC_IW_APBVT_ENTRY:	case IRDMA_HMC_IW_APBVT_ENTRY:
	obj_info[rsrc_idx].cnt = 1;	if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2)
		obj_info[rsrc_idx].cnt = 1;
		else
		obj_info[rsrc_idx].cnt = 0;
	break;	break;
	default:	default:
	obj_info[rsrc_idx].cnt = (u32)temp;	obj_info[rsrc_idx].cnt = (u32)temp;
Context not available.
	obj_info = hmc_info->hmc_obj;	obj_info = hmc_info->hmc_obj;

	get_64bit_val(buf, IRDMA_BYTE_0, &temp);	get_64bit_val(buf, IRDMA_BYTE_0, &temp);
	hmc_info->first_sd_index = (u16)RS_64(temp, IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX);	hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp);
	max_pe_sds = (u16)RS_64(temp, IRDMA_QUERY_FPM_MAX_PE_SDS);	max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp);

	hmc_fpm_misc->max_sds = max_pe_sds;	hmc_fpm_misc->max_sds = max_pe_sds;
	hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;	hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
	get_64bit_val(buf, 8, &temp);	get_64bit_val(buf, 8, &temp);
	obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)RS_64(temp, IRDMA_QUERY_FPM_MAX_QPS);	obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp);
	size = (u32)RS_64_1(temp, 32);	size = (u32)RS_64_1(temp, 32);
	obj_info[IRDMA_HMC_IW_QP].size = LS_64_1(1, size);	obj_info[IRDMA_HMC_IW_QP].size = LS_64_1(1, size);

	get_64bit_val(buf, 16, &temp);	get_64bit_val(buf, 16, &temp);
	obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, IRDMA_QUERY_FPM_MAX_CQS);	obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp);
	size = (u32)RS_64_1(temp, 32);	size = (u32)RS_64_1(temp, 32);
	obj_info[IRDMA_HMC_IW_CQ].size = LS_64_1(1, size);	obj_info[IRDMA_HMC_IW_CQ].size = LS_64_1(1, size);

Context not available.
	get_64bit_val(buf, 64, &temp);	get_64bit_val(buf, 64, &temp);
	obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp;	obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp;
	obj_info[IRDMA_HMC_IW_XFFL].size = 4;	obj_info[IRDMA_HMC_IW_XFFL].size = 4;
	hmc_fpm_misc->xf_block_size = RS_64(temp, IRDMA_QUERY_FPM_XFBLOCKSIZE);	hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp);
	if (!hmc_fpm_misc->xf_block_size)	if (!hmc_fpm_misc->xf_block_size)
	return -EINVAL;	return -EINVAL;

Context not available.
	obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp;	obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp;
	obj_info[IRDMA_HMC_IW_Q1FL].size = 4;	obj_info[IRDMA_HMC_IW_Q1FL].size = 4;

	hmc_fpm_misc->q1_block_size = RS_64(temp, IRDMA_QUERY_FPM_Q1BLOCKSIZE);	hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp);
	if (!hmc_fpm_misc->q1_block_size)	if (!hmc_fpm_misc->q1_block_size)
	return -EINVAL;	return -EINVAL;

Context not available.
	obj_info[IRDMA_HMC_IW_PBLE].size = 8;	obj_info[IRDMA_HMC_IW_PBLE].size = 8;

	get_64bit_val(buf, 120, &temp);	get_64bit_val(buf, 120, &temp);
	hmc_fpm_misc->max_ceqs = RS_64(temp, IRDMA_QUERY_FPM_MAX_CEQS);	hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp);
	hmc_fpm_misc->ht_multiplier = RS_64(temp, IRDMA_QUERY_FPM_HTMULTIPLIER);	hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp);
	hmc_fpm_misc->timer_bucket = RS_64(temp, IRDMA_QUERY_FPM_TIMERBUCKET);	hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp);
	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)	if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
	return 0;	return 0;
	irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC);	irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC);
Context not available.
	get_64bit_val(buf, IRDMA_BYTE_136, &temp);	get_64bit_val(buf, IRDMA_BYTE_136, &temp);
	obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp;	obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp;
	obj_info[IRDMA_HMC_IW_RRFFL].size = 4;	obj_info[IRDMA_HMC_IW_RRFFL].size = 4;
	hmc_fpm_misc->rrf_block_size = RS_64(temp, IRDMA_QUERY_FPM_RRFBLOCKSIZE);	hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp);
	if (!hmc_fpm_misc->rrf_block_size &&	if (!hmc_fpm_misc->rrf_block_size &&
	obj_info[IRDMA_HMC_IW_RRFFL].max_cnt)	obj_info[IRDMA_HMC_IW_RRFFL].max_cnt)
	return -EINVAL;	return -EINVAL;
Context not available.
	get_64bit_val(buf, IRDMA_BYTE_168, &temp);	get_64bit_val(buf, IRDMA_BYTE_168, &temp);
	obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp;	obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp;
	obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4;	obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4;
	hmc_fpm_misc->ooiscf_block_size = RS_64(temp, IRDMA_QUERY_FPM_OOISCFBLOCKSIZE);	hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp);
	if (!hmc_fpm_misc->ooiscf_block_size &&	if (!hmc_fpm_misc->ooiscf_block_size &&
	obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt)	obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt)
	return -EINVAL;	return -EINVAL;
Context not available.

	spin_lock_init(&cqp->dev->cqp_lock);	spin_lock_init(&cqp->dev->cqp_lock);

	temp = LS_64(cqp->hw_sq_size, IRDMA_CQPHC_SQSIZE) \|	temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) \|
	LS_64(cqp->struct_ver, IRDMA_CQPHC_SVER) \|	FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) \|
	LS_64(cqp->disable_packed, IRDMA_CQPHC_DISABLE_PFPDUS) \|	FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) \|
	LS_64(cqp->ceqs_per_vf, IRDMA_CQPHC_CEQPERVF);	FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf);
	if (hw_rev >= IRDMA_GEN_2) {	if (hw_rev >= IRDMA_GEN_2) {
	temp \|= LS_64(cqp->rocev2_rto_policy, IRDMA_CQPHC_ROCEV2_RTO_POLICY) \|	temp \|= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY,
	LS_64(cqp->protocol_used, IRDMA_CQPHC_PROTOCOL_USED);	cqp->rocev2_rto_policy) \|
		FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED,
		cqp->protocol_used);
	}	}

	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_0, temp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_0, temp);
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_8, cqp->sq_pa);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_8, cqp->sq_pa);

	temp = LS_64(cqp->ena_vf_count, IRDMA_CQPHC_ENABLED_VFS) \|	temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) \|
	LS_64(cqp->hmc_profile, IRDMA_CQPHC_HMC_PROFILE);	FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile);
	if (hw_rev >= IRDMA_GEN_2)	if (hw_rev >= IRDMA_GEN_2)
	temp \|= LS_64(cqp->en_rem_endpoint_trk, IRDMA_CQPHC_EN_REM_ENDPOINT_TRK);	temp \|= FIELD_PREP(IRDMA_CQPHC_EN_REM_ENDPOINT_TRK,
		cqp->en_rem_endpoint_trk);
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_16, temp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_16, temp);
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_24, (uintptr_t)cqp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_24, (uintptr_t)cqp);
	temp = LS_64(cqp->hw_maj_ver, IRDMA_CQPHC_HW_MAJVER) \|	temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) \|
	LS_64(cqp->hw_min_ver, IRDMA_CQPHC_HW_MINVER);	FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver);
	if (hw_rev >= IRDMA_GEN_2) {	if (hw_rev >= IRDMA_GEN_2) {
	temp \|= LS_64(cqp->dcqcn_params.min_rate, IRDMA_CQPHC_MIN_RATE) \|	temp \|= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) \|
	LS_64(cqp->dcqcn_params.min_dec_factor, IRDMA_CQPHC_MIN_DEC_FACTOR);	FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor);
	}	}
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_32, temp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_32, temp);
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_40, 0);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_40, 0);
	temp = 0;	temp = 0;
	if (hw_rev >= IRDMA_GEN_2) {	if (hw_rev >= IRDMA_GEN_2) {
	temp \|= LS_64(cqp->dcqcn_params.dcqcn_t, IRDMA_CQPHC_DCQCN_T) \|	temp \|= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) \|
	LS_64(cqp->dcqcn_params.rai_factor, IRDMA_CQPHC_RAI_FACTOR) \|	FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) \|
	LS_64(cqp->dcqcn_params.hai_factor, IRDMA_CQPHC_HAI_FACTOR);	FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor);
	}	}
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_48, temp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_48, temp);
	temp = 0;	temp = 0;
	if (hw_rev >= IRDMA_GEN_2) {	if (hw_rev >= IRDMA_GEN_2) {
	temp \|= LS_64(cqp->dcqcn_params.dcqcn_b, IRDMA_CQPHC_DCQCN_B) \|	temp \|= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) \|
	LS_64(cqp->dcqcn_params.dcqcn_f, IRDMA_CQPHC_DCQCN_F) \|	FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) \|
	LS_64(cqp->dcqcn_params.cc_cfg_valid, IRDMA_CQPHC_CC_CFG_VALID) \|	FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) \|
	LS_64(cqp->dcqcn_params.rreduce_mperiod, IRDMA_CQPHC_RREDUCE_MPERIOD);	FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod);
	}	}
	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_56, temp);	set_64bit_val(cqp->host_ctx, IRDMA_BYTE_56, temp);
	irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQP_HOST_CTX WQE",	irdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, "CQP_HOST_CTX WQE",
Context not available.
	spin_lock_destroy(&cqp->dev->cqp_lock);	spin_lock_destroy(&cqp->dev->cqp_lock);
	irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);	irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
	err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);	err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
	*min_err = RS_32(err_code, IRDMA_CQPERRCODES_CQP_MINOR_CODE);	*min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code);
	*maj_err = RS_32(err_code, IRDMA_CQPERRCODES_CQP_MAJOR_CODE);	*maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code);
	return ret_code;	return ret_code;
	}	}

Context not available.
	/**	/**
	* irdma_sc_cqp_destroy - destroy cqp during close	* irdma_sc_cqp_destroy - destroy cqp during close
	* @cqp: struct for cqp hw	* @cqp: struct for cqp hw
		* @free_hwcqp: true for regular cqp destroy; false for reset path
	*/	*/
	int	int
	irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp)	irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp, bool free_hwcqp)
	{	{
	u32 cnt = 0, val;	u32 cnt = 0, val;
	int ret_code = 0;	int ret_code = 0;

	writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);	if (free_hwcqp) {
	writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);	writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]);
	do {	writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]);
	if (cnt++ > cqp->dev->hw_attrs.max_done_count) {	do {
	ret_code = -ETIMEDOUT;	if (cnt++ > cqp->dev->hw_attrs.max_done_count) {
	break;	ret_code = -ETIMEDOUT;
	}	break;
	irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);	}
	val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);	irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
	} while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE));	val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]);
		} while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE));
		}
	irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);	irdma_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
	spin_lock_destroy(&cqp->dev->cqp_lock);	spin_lock_destroy(&cqp->dev->cqp_lock);
	return ret_code;	return ret_code;
Context not available.
	u8 arm_seq_num;	u8 arm_seq_num;

	get_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, &temp_val);	get_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, &temp_val);
	sw_cq_sel = (u16)RS_64(temp_val, IRDMA_CQ_DBSA_SW_CQ_SELECT);	sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val);
	arm_next_se = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_NEXT_SE);	arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val);
	arm_seq_num = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_SEQ_NUM);	arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val);
	arm_seq_num++;	arm_seq_num++;
	temp_val = LS_64(arm_seq_num, IRDMA_CQ_DBSA_ARM_SEQ_NUM) \|	temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) \|
	LS_64(sw_cq_sel, IRDMA_CQ_DBSA_SW_CQ_SELECT) \|	FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) \|
	LS_64(arm_next_se, IRDMA_CQ_DBSA_ARM_NEXT_SE) \|	FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) \|
	LS_64(1, IRDMA_CQ_DBSA_ARM_NEXT);	FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1);
	set_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, temp_val);	set_64bit_val(ccq->cq_uk.shadow_area, IRDMA_BYTE_32, temp_val);

	irdma_wmb(); /* make sure shadow area is updated before arming */	irdma_wmb(); /* make sure shadow area is updated before arming */
Context not available.
	cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk);	cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk);

	get_64bit_val(cqe, IRDMA_BYTE_24, &temp);	get_64bit_val(cqe, IRDMA_BYTE_24, &temp);
	polarity = (u8)RS_64(temp, IRDMA_CQ_VALID);	polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp);
	if (polarity != ccq->cq_uk.polarity)	if (polarity != ccq->cq_uk.polarity)
	return -ENOENT;	return -ENOENT;

	get_64bit_val(cqe, IRDMA_BYTE_8, &qp_ctx);	get_64bit_val(cqe, IRDMA_BYTE_8, &qp_ctx);
	cqp = (struct irdma_sc_cqp *)(irdma_uintptr) qp_ctx;	cqp = (struct irdma_sc_cqp *)(irdma_uintptr) qp_ctx;
	info->error = (bool)RS_64(temp, IRDMA_CQ_ERROR);	info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp);
	info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR;	info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR;
	info->min_err_code = (u16)RS_64(temp, IRDMA_CQ_MINERR);	info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp);
	if (info->error) {	if (info->error) {
	info->maj_err_code = (u16)RS_64(temp, IRDMA_CQ_MAJERR);	info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp);
	error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);	error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]);
	irdma_debug(cqp->dev, IRDMA_DEBUG_CQP,	irdma_debug(cqp->dev, IRDMA_DEBUG_CQP,
	"CQPERRCODES error_code[x%08X]\n", error);	"CQPERRCODES error_code[x%08X]\n", error);
	}	}

	wqe_idx = (u32)RS_64(temp, IRDMA_CQ_WQEIDX);	wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp);
	info->scratch = cqp->scratch_array[wqe_idx];	info->scratch = cqp->scratch_array[wqe_idx];

	get_64bit_val(cqe, IRDMA_BYTE_16, &temp1);	get_64bit_val(cqe, IRDMA_BYTE_16, &temp1);
	info->op_ret_val = (u32)RS_64(temp1, IRDMA_CCQ_OPRETVAL);	info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1);

	get_64bit_val(cqp->sq_base[wqe_idx].elem, IRDMA_BYTE_24, &temp1);	get_64bit_val(cqp->sq_base[wqe_idx].elem, IRDMA_BYTE_24, &temp1);
	info->op_code = (u8)RS_64(temp1, IRDMA_CQPSQ_OPCODE);	info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1);
	info->cqp = cqp;	info->cqp = cqp;

	/* move the head for cq */	/* move the head for cq */
Context not available.
	if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count)	if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count)
	return -ETIMEDOUT;	return -ETIMEDOUT;

	if (cqp->dev->no_cqp)
	return -ETIMEDOUT;

	if (irdma_sc_ccq_get_cqe_info(ccq, &info)) {	if (irdma_sc_ccq_get_cqe_info(ccq, &info)) {
	irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);	irdma_usec_delay(cqp->dev->hw_attrs.max_sleep_count);
	continue;	continue;
Context not available.
	if (!wqe)	if (!wqe)
	return -ENOSPC;	return -ENOSPC;

	hdr = LS_64(info->vf_id, IRDMA_CQPSQ_MHMC_VFIDX) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) \|
	LS_64(IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE,	FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	IRDMA_CQPSQ_OPCODE) \|	IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) \|
	LS_64(info->free_fcn, IRDMA_CQPSQ_MHMC_FREEPMFN) \|	FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	*/	*/
	static int	static int
	irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,	irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
	u8 hmc_fn_id,	u16 hmc_fn_id,
	struct irdma_dma_mem *commit_fpm_mem,	struct irdma_dma_mem *commit_fpm_mem,
	bool post_sq, u8 wait_type)	bool post_sq, u8 wait_type)
	{	{
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);	set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);
	set_64bit_val(wqe, IRDMA_BYTE_32, commit_fpm_mem->pa);	set_64bit_val(wqe, IRDMA_BYTE_32, commit_fpm_mem->pa);

	hdr = LS_64(IRDMA_COMMIT_FPM_BUF_SIZE, IRDMA_CQPSQ_BUFSIZE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) \|
	LS_64(IRDMA_CQP_OP_COMMIT_FPM_VAL, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);

	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

Context not available.
	*/	*/
	static int	static int
	irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,	irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch,
	u8 hmc_fn_id,	u16 hmc_fn_id,
	struct irdma_dma_mem *query_fpm_mem,	struct irdma_dma_mem *query_fpm_mem,
	bool post_sq, u8 wait_type)	bool post_sq, u8 wait_type)
	{	{
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);	set_64bit_val(wqe, IRDMA_BYTE_16, hmc_fn_id);
	set_64bit_val(wqe, IRDMA_BYTE_32, query_fpm_mem->pa);	set_64bit_val(wqe, IRDMA_BYTE_32, query_fpm_mem->pa);

	hdr = LS_64(IRDMA_CQP_OP_QUERY_FPM_VAL, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	* @scratch: u64 saved to be used during cqp completion	* @scratch: u64 saved to be used during cqp completion
	* @post_sq: flag for cqp db to ring	* @post_sq: flag for cqp db to ring
	*/	*/

	static int	static int
	irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,	irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch,
	bool post_sq)	bool post_sq)
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	(ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));	(ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
	set_64bit_val(wqe, IRDMA_BYTE_56,	set_64bit_val(wqe, IRDMA_BYTE_56,
	LS_64(ceq->tph_val, IRDMA_CQPSQ_TPHVAL) \|	FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) \|
	LS_64(ceq->vsi->vsi_idx, IRDMA_CQPSQ_VSIIDX));	FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx));
	hdr = LS_64(ceq->ceq_id, IRDMA_CQPSQ_CEQ_CEQID) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) \|
	LS_64(IRDMA_CQP_OP_CREATE_CEQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) \|
	LS_64(ceq->pbl_chunk_size, IRDMA_CQPSQ_CEQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) \|
	LS_64(ceq->virtual_map, IRDMA_CQPSQ_CEQ_VMAP) \|	FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) \|
	LS_64(ceq->itr_no_expire, IRDMA_CQPSQ_CEQ_ITRNOEXPIRE) \|	FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) \|
	LS_64(ceq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_16, ceq->elem_cnt);	set_64bit_val(wqe, IRDMA_BYTE_16, ceq->elem_cnt);
	set_64bit_val(wqe, IRDMA_BYTE_48, ceq->first_pm_pbl_idx);	set_64bit_val(wqe, IRDMA_BYTE_48, ceq->first_pm_pbl_idx);
	hdr = ceq->ceq_id \|	hdr = ceq->ceq_id \|
	LS_64(IRDMA_CQP_OP_DESTROY_CEQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) \|
	LS_64(ceq->pbl_chunk_size, IRDMA_CQPSQ_CEQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) \|
	LS_64(ceq->virtual_map, IRDMA_CQPSQ_CEQ_VMAP) \|	FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) \|
	LS_64(ceq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	cq_idx = 0;	cq_idx = 0;
	ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq);	ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq);
	get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);	get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);
	polarity = (u8)RS_64(temp, IRDMA_CEQE_VALID);	polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
	if (polarity != ceq->polarity)	if (polarity != ceq->polarity)
	return NULL;	return NULL;

Context not available.
	ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next);	ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next);

	get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);	get_64bit_val(ceqe, IRDMA_BYTE_0, &temp);
	polarity = (u8)RS_64(temp, IRDMA_CEQE_VALID);	polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);
	if (polarity != ceq_polarity)	if (polarity != ceq_polarity)
	return;	return;

	next_cq = (struct irdma_sc_cq *)(irdma_uintptr) LS_64_1(temp, 1);	next_cq = (struct irdma_sc_cq *)(irdma_uintptr) LS_64_1(temp, 1);
	if (cq == next_cq)	if (cq == next_cq)
	set_64bit_val(ceqe, IRDMA_BYTE_0, temp & IRDMA_CEQE_VALID_M);	set_64bit_val(ceqe, IRDMA_BYTE_0, temp & IRDMA_CEQE_VALID);

	next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i);	next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i);
	if (!next)	if (!next)
Context not available.
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	(aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));	(aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));

	hdr = LS_64(IRDMA_CQP_OP_CREATE_AEQ, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) \|
	LS_64(aeq->pbl_chunk_size, IRDMA_CQPSQ_AEQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) \|
	LS_64(aeq->virtual_map, IRDMA_CQPSQ_AEQ_VMAP) \|	FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	* @scratch: u64 saved to be used during cqp completion	* @scratch: u64 saved to be used during cqp completion
	* @post_sq: flag for cqp db to ring	* @post_sq: flag for cqp db to ring
	*/	*/
	static int	int
	irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch,	irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, bool post_sq)
	bool post_sq)
	{	{
	__le64 *wqe;	__le64 *wqe;
	struct irdma_sc_cqp *cqp;	struct irdma_sc_cqp *cqp;
Context not available.
	return -ENOSPC;	return -ENOSPC;
	set_64bit_val(wqe, IRDMA_BYTE_16, aeq->elem_cnt);	set_64bit_val(wqe, IRDMA_BYTE_16, aeq->elem_cnt);
	set_64bit_val(wqe, IRDMA_BYTE_48, aeq->first_pm_pbl_idx);	set_64bit_val(wqe, IRDMA_BYTE_48, aeq->first_pm_pbl_idx);
	hdr = LS_64(IRDMA_CQP_OP_DESTROY_AEQ, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) \|
	LS_64(aeq->pbl_chunk_size, IRDMA_CQPSQ_AEQ_LPBLSIZE) \|	FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) \|
	LS_64(aeq->virtual_map, IRDMA_CQPSQ_AEQ_VMAP) \|	FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	{	{
	u64 temp, compl_ctx;	u64 temp, compl_ctx;
	__le64 *aeqe;	__le64 *aeqe;
	u16 wqe_idx;
	u8 ae_src;	u8 ae_src;
	u8 polarity;	u8 polarity;

	aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq);	aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq);
	get_64bit_val(aeqe, IRDMA_BYTE_0, &compl_ctx);	get_64bit_val(aeqe, IRDMA_BYTE_0, &compl_ctx);
	get_64bit_val(aeqe, IRDMA_BYTE_8, &temp);	get_64bit_val(aeqe, IRDMA_BYTE_8, &temp);
	polarity = (u8)RS_64(temp, IRDMA_AEQE_VALID);	polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp);

	if (aeq->polarity != polarity)	if (aeq->polarity != polarity)
	return -ENOENT;	return -ENOENT;

	irdma_debug_buf(aeq->dev, IRDMA_DEBUG_WQE, "AEQ_ENTRY WQE", aeqe, 16);	irdma_debug_buf(aeq->dev, IRDMA_DEBUG_WQE, "AEQ_ENTRY WQE", aeqe, 16);

	ae_src = (u8)RS_64(temp, IRDMA_AEQE_AESRC);	ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp);
	wqe_idx = (u16)RS_64(temp, IRDMA_AEQE_WQDESCIDX);	info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp);
	info->qp_cq_id = (u32)RS_64(temp, IRDMA_AEQE_QPCQID_LOW) \|	info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) \|
	((u32)RS_64(temp, IRDMA_AEQE_QPCQID_HI) << 18);	((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18);
	info->ae_id = (u16)RS_64(temp, IRDMA_AEQE_AECODE);	info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp);
	info->tcp_state = (u8)RS_64(temp, IRDMA_AEQE_TCPSTATE);	info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp);
	info->iwarp_state = (u8)RS_64(temp, IRDMA_AEQE_IWSTATE);	info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp);
	info->q2_data_written = (u8)RS_64(temp, IRDMA_AEQE_Q2DATA);	info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp);
	info->aeqe_overflow = (bool)RS_64(temp, IRDMA_AEQE_OVERFLOW);	info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, temp);

	info->ae_src = ae_src;	info->ae_src = ae_src;
	switch (info->ae_id) {	switch (info->ae_id) {
Context not available.
	case IRDMA_AE_SOURCE_RQ_0011:	case IRDMA_AE_SOURCE_RQ_0011:
	info->qp = true;	info->qp = true;
	info->rq = true;	info->rq = true;
	info->wqe_idx = wqe_idx;
	info->compl_ctx = compl_ctx;	info->compl_ctx = compl_ctx;
	break;	break;
	case IRDMA_AE_SOURCE_CQ:	case IRDMA_AE_SOURCE_CQ:
Context not available.
	case IRDMA_AE_SOURCE_SQ_0111:	case IRDMA_AE_SOURCE_SQ_0111:
	info->qp = true;	info->qp = true;
	info->sq = true;	info->sq = true;
	info->wqe_idx = wqe_idx;
	info->compl_ctx = compl_ctx;	info->compl_ctx = compl_ctx;
	break;	break;
	case IRDMA_AE_SOURCE_IN_WR:	case IRDMA_AE_SOURCE_IN_WR:
Context not available.
	int	int
	irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)	irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count)
	{	{
	writel(count, dev->hw_regs[IRDMA_AEQALLOC]);	db_wr32(count, dev->aeq_alloc_db);

	return 0;	return 0;
	}	}
Context not available.
	hdr = ccq->cq_uk.cq_id \|	hdr = ccq->cq_uk.cq_id \|
	FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0),	FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0),
	IRDMA_CQPSQ_CQ_CEQID) \|	IRDMA_CQPSQ_CQ_CEQID) \|
	LS_64(IRDMA_CQP_OP_DESTROY_CQ, IRDMA_CQPSQ_OPCODE) \|	FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) \|
	LS_64(ccq->ceqe_mask, IRDMA_CQPSQ_CQ_ENCEQEMASK) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) \|
	LS_64(ccq->ceq_id_valid, IRDMA_CQPSQ_CQ_CEQIDVALID) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) \|
	LS_64(ccq->tph_en, IRDMA_CQPSQ_TPHEN) \|	FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) \|
	LS_64(ccq->cq_uk.avoid_mem_cflct, IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT) \|	FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	* @hmc_fn_id: hmc function id	* @hmc_fn_id: hmc function id
	*/	*/
	int	int
	irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u8 hmc_fn_id)	irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u16 hmc_fn_id)
	{	{
	struct irdma_hmc_info *hmc_info;	struct irdma_hmc_info *hmc_info;
	struct irdma_hmc_fpm_misc *hmc_fpm_misc;	struct irdma_hmc_fpm_misc *hmc_fpm_misc;
Context not available.
	* @hmc_fn_id: hmc function id	* @hmc_fn_id: hmc function id
	*/	*/
	static int	static int
	irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u8 hmc_fn_id)	irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u16 hmc_fn_id)
	{	{
	struct irdma_hmc_obj_info *obj_info;	struct irdma_hmc_obj_info *obj_info;
	__le64 *buf;	__le64 *buf;
Context not available.
	} else {	} else {
	data = 0;	data = 0;
	}	}
	data \|= LS_64(info->hmc_fn_id, IRDMA_CQPSQ_UPESD_HMCFNID);	data \|= FLD_LS_64(cqp->dev, info->hmc_fn_id, IRDMA_CQPSQ_UPESD_HMCFNID);
	set_64bit_val(wqe, IRDMA_BYTE_16, data);	set_64bit_val(wqe, IRDMA_BYTE_16, data);

	switch (wqe_entries) {	switch (wqe_entries) {
	case 3:	case 3:
	set_64bit_val(wqe, IRDMA_BYTE_48,	set_64bit_val(wqe, IRDMA_BYTE_48,
	(LS_64(info->entry[2].cmd, IRDMA_CQPSQ_UPESD_SDCMD) \|	(FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) \|
	LS_64(1, IRDMA_CQPSQ_UPESD_ENTRY_VALID)));	FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));

	set_64bit_val(wqe, IRDMA_BYTE_56, info->entry[2].data);	set_64bit_val(wqe, IRDMA_BYTE_56, info->entry[2].data);
	/* fallthrough */	/* fallthrough */
	case 2:	case 2:
	set_64bit_val(wqe, IRDMA_BYTE_32,	set_64bit_val(wqe, IRDMA_BYTE_32,
	(LS_64(info->entry[1].cmd, IRDMA_CQPSQ_UPESD_SDCMD) \|	(FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) \|
	LS_64(1, IRDMA_CQPSQ_UPESD_ENTRY_VALID)));	FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1)));

	set_64bit_val(wqe, IRDMA_BYTE_40, info->entry[1].data);	set_64bit_val(wqe, IRDMA_BYTE_40, info->entry[1].data);
	/* fallthrough */	/* fallthrough */
	case 1:	case 1:
	set_64bit_val(wqe, IRDMA_BYTE_0,	set_64bit_val(wqe, IRDMA_BYTE_0,
	LS_64(info->entry[0].cmd, IRDMA_CQPSQ_UPESD_SDCMD));	FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd));

	set_64bit_val(wqe, IRDMA_BYTE_8, info->entry[0].data);	set_64bit_val(wqe, IRDMA_BYTE_8, info->entry[0].data);
	break;	break;
Context not available.
	break;	break;
	}	}

	hdr = LS_64(IRDMA_CQP_OP_UPDATE_PE_SDS, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) \|
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID) \|	FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) \|
	LS_64(mem_entries, IRDMA_CQPSQ_UPESD_ENTRY_COUNT);	FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	*/	*/
	int	int
	irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,	irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,
	u8 hmc_fn_id, bool post_sq,	u16 hmc_fn_id, bool post_sq,
	bool poll_registers)	bool poll_registers)
	{	{
	u64 hdr;	u64 hdr;
Context not available.
	return -ENOSPC;	return -ENOSPC;

	set_64bit_val(wqe, IRDMA_BYTE_16,	set_64bit_val(wqe, IRDMA_BYTE_16,
	LS_64(hmc_fn_id, IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID));	FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id));

	hdr = LS_64(IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, IRDMA_CQPSQ_OPCODE) \|	hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE,
	LS_64(cqp->polarity, IRDMA_CQPSQ_WQEVALID);	IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) \|
		FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
Context not available.
	temp = buf->pa;	temp = buf->pa;
	set_64bit_val(wqe, IRDMA_BYTE_32, temp);	set_64bit_val(wqe, IRDMA_BYTE_32, temp);

	temp = LS_64(cqp->polarity, IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID) \|	temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID,
	LS_64(buf->size, IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN) \|	cqp->polarity) \|
	LS_64(IRDMA_CQP_OP_QUERY_RDMA_FEATURES, IRDMA_CQPSQ_UP_OP);	FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) \|
		FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES);
	irdma_wmb(); /* make sure WQE is written before valid bit is set */	irdma_wmb(); /* make sure WQE is written before valid bit is set */

	set_64bit_val(wqe, IRDMA_BYTE_24, temp);	set_64bit_val(wqe, IRDMA_BYTE_24, temp);
Context not available.
	goto exit;	goto exit;

	get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);	get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);
	feat_cnt = (u16)RS_64(temp, IRDMA_FEATURE_CNT);	feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
	if (feat_cnt < IRDMA_MIN_FEATURES) {	if (feat_cnt < IRDMA_MIN_FEATURES) {
	ret_code = -EINVAL;	ret_code = -EINVAL;
	goto exit;	goto exit;
Context not available.
	goto exit;	goto exit;

	get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);	get_64bit_val(feat_buf.va, IRDMA_BYTE_0, &temp);
	feat_cnt = (u16)RS_64(temp, IRDMA_FEATURE_CNT);	feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp);
	if (feat_cnt < IRDMA_MIN_FEATURES) {	if (feat_cnt < IRDMA_MIN_FEATURES) {
	ret_code = -EINVAL;	ret_code = -EINVAL;
	goto exit;	goto exit;
Context not available.
	for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES);	for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, (u16)IRDMA_MAX_FEATURES);
	feat_idx++, byte_idx += 8) {	feat_idx++, byte_idx += 8) {
	get_64bit_val(feat_buf.va, byte_idx, &temp);	get_64bit_val(feat_buf.va, byte_idx, &temp);
	feat_type = RS_64(temp, IRDMA_FEATURE_TYPE);	feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp);
	dev->feature_info[feat_type] = temp;	dev->feature_info[feat_type] = temp;
	}	}
	exit:	exit:
Context not available.
	hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt;	hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt;
	hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt =	hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt =
	hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt;	hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt;
		if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2)
	hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1;	hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1;

	while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt)	while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt)
	qpwanted /= 2;	qpwanted /= 2;
Context not available.
	mem_size = sizeof(struct irdma_hmc_sd_entry) *	mem_size = sizeof(struct irdma_hmc_sd_entry) *
	(hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);	(hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index + 1);
	virt_mem.size = mem_size;	virt_mem.size = mem_size;
	virt_mem.va = kzalloc(virt_mem.size, GFP_ATOMIC);	virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL);
	if (!virt_mem.va) {	if (!virt_mem.va) {
	irdma_debug(dev, IRDMA_DEBUG_HMC,	irdma_debug(dev, IRDMA_DEBUG_HMC,
	"failed to allocate memory for sd_entry buffer\n");	"failed to allocate memory for sd_entry buffer\n");
Context not available.
	status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,	status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq,
	pcmdinfo->in.u.aeq_destroy.scratch,	pcmdinfo->in.u.aeq_destroy.scratch,
	pcmdinfo->post_sq);	pcmdinfo->post_sq);

	break;	break;
	case IRDMA_OP_CEQ_CREATE:	case IRDMA_OP_CEQ_CREATE:
	status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,	status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq,
Context not available.
	int status = 0;	int status = 0;
	unsigned long flags;	unsigned long flags;

	if (dev->no_cqp)
	return -EFAULT;

	spin_lock_irqsave(&dev->cqp_lock, flags);	spin_lock_irqsave(&dev->cqp_lock, flags);
	if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp))	if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp))
	status = irdma_exec_cqp_cmd(dev, pcmdinfo);	status = irdma_exec_cqp_cmd(dev, pcmdinfo);
Context not available.
	irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable)	irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable)
	{	{
	u32 reg_val;	u32 reg_val;
	reg_val = enable ? IRDMA_PFINT_AEQCTL_CAUSE_ENA_M : 0;	reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) \|
	reg_val \|= (idx << IRDMA_PFINT_AEQCTL_MSIX_INDX_S) \|	FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) \|
	IRDMA_PFINT_AEQCTL_ITR_INDX_M;	FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, IRDMA_IDX_NOITR);

	writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);	writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]);
	}	}

Context not available.

	/**	/**
	* irdma_sc_dev_init - Initialize control part of device	* irdma_sc_dev_init - Initialize control part of device
	* @ver: version
	* @dev: Device pointer	* @dev: Device pointer
	* @info: Device init info	* @info: Device init info
	*/	*/
	int	int
	irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev,	irdma_sc_dev_init(struct irdma_sc_dev dev, struct irdma_device_init_info info)
	struct irdma_device_init_info *info)
	{	{
	u32 val;	u32 val;
	int ret_code = 0;	int ret_code = 0;
Context not available.
	dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT;	dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT;
	dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS;	dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS;

	dev->hw_attrs.uk_attrs.hw_rev = ver;
	irdma_sc_init_hw(dev);	irdma_sc_init_hw(dev);

	if (irdma_wait_pe_ready(dev))	if (irdma_wait_pe_ready(dev))
	return -ETIMEDOUT;	return -ETIMEDOUT;

	val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);	val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]);
	db_size = (u8)RS_32(val, IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE);	db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val);
	if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {	if (db_size != IRDMA_PE_DB_SIZE_4M && db_size != IRDMA_PE_DB_SIZE_8M) {
	irdma_debug(dev, IRDMA_DEBUG_DEV,	irdma_debug(dev, IRDMA_DEBUG_DEV,
	"RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",	"RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n",
Context not available.