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sys/dev/irdma/icrdma_hw.c
| /*- | /*- | ||||
| * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB | * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB | ||||
| * | * | ||||
| * Copyright (c) 2017 - 2021 Intel Corporation | * Copyright (c) 2017 - 2022 Intel Corporation | ||||
| * | * | ||||
| * This software is available to you under a choice of one of two | * This software is available to you under a choice of one of two | ||||
| * licenses. You may choose to be licensed under the terms of the GNU | * licenses. You may choose to be licensed under the terms of the GNU | ||||
| Context not available. | |||||
| }; | }; | ||||
| static u64 icrdma_masks[IRDMA_MAX_MASKS] = { | static u64 icrdma_masks[IRDMA_MAX_MASKS] = { | ||||
| ICRDMA_CCQPSTATUS_CCQP_DONE_M, | ICRDMA_CCQPSTATUS_CCQP_DONE, | ||||
| ICRDMA_CCQPSTATUS_CCQP_ERR_M, | ICRDMA_CCQPSTATUS_CCQP_ERR, | ||||
| ICRDMA_CQPSQ_STAG_PDID_M, | ICRDMA_CQPSQ_STAG_PDID, | ||||
| ICRDMA_CQPSQ_CQ_CEQID_M, | ICRDMA_CQPSQ_CQ_CEQID, | ||||
| ICRDMA_CQPSQ_CQ_CQID_M, | ICRDMA_CQPSQ_CQ_CQID, | ||||
| ICRDMA_COMMIT_FPM_CQCNT_M, | ICRDMA_COMMIT_FPM_CQCNT, | ||||
| ICRDMA_CQPSQ_UPESD_HMCFNID | |||||
| }; | }; | ||||
| static u64 icrdma_shifts[IRDMA_MAX_SHIFTS] = { | static u8 icrdma_shifts[IRDMA_MAX_SHIFTS] = { | ||||
| ICRDMA_CCQPSTATUS_CCQP_DONE_S, | ICRDMA_CCQPSTATUS_CCQP_DONE_S, | ||||
| ICRDMA_CCQPSTATUS_CCQP_ERR_S, | ICRDMA_CCQPSTATUS_CCQP_ERR_S, | ||||
| ICRDMA_CQPSQ_STAG_PDID_S, | ICRDMA_CQPSQ_STAG_PDID_S, | ||||
| ICRDMA_CQPSQ_CQ_CEQID_S, | ICRDMA_CQPSQ_CQ_CEQID_S, | ||||
| ICRDMA_CQPSQ_CQ_CQID_S, | ICRDMA_CQPSQ_CQ_CQID_S, | ||||
| ICRDMA_COMMIT_FPM_CQCNT_S, | ICRDMA_COMMIT_FPM_CQCNT_S, | ||||
| ICRDMA_CQPSQ_UPESD_HMCFNID_S | |||||
| }; | }; | ||||
| /** | /** | ||||
| Context not available. | |||||
| if (dev->ceq_itr && dev->aeq->msix_idx != idx) | if (dev->ceq_itr && dev->aeq->msix_idx != idx) | ||||
| interval = dev->ceq_itr >> 1; /* 2 usec units */ | interval = dev->ceq_itr >> 1; /* 2 usec units */ | ||||
| val = LS_64(0, IRDMA_GLINT_DYN_CTL_ITR_INDX) | | val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, IRDMA_IDX_ITR0) | | ||||
| LS_64(interval, IRDMA_GLINT_DYN_CTL_INTERVAL) | | FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTERVAL, interval) | | ||||
| IRDMA_GLINT_DYN_CTL_INTENA_M | IRDMA_GLINT_DYN_CTL_CLEARPBA_M; | FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, true) | | ||||
| FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, true); | |||||
| writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); | writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); | ||||
| } | } | ||||
| Context not available. | |||||
| { | { | ||||
| u32 reg_val; | u32 reg_val; | ||||
| reg_val = enable ? IRDMA_GLINT_CEQCTL_CAUSE_ENA_M : 0; | reg_val = enable ? IRDMA_GLINT_CEQCTL_CAUSE_ENA : 0; | ||||
| reg_val |= (idx << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) | | reg_val |= (idx << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) | | ||||
| IRDMA_GLINT_CEQCTL_ITR_INDX_M; | IRDMA_GLINT_CEQCTL_ITR_INDX; | ||||
| writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id); | writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id); | ||||
| } | } | ||||
| Context not available. | |||||
| dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; | dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; | ||||
| dev->irq_ops = &icrdma_irq_ops; | dev->irq_ops = &icrdma_irq_ops; | ||||
| dev->hw_stats_map = icrdma_hw_stat_map; | dev->hw_stats_map = icrdma_hw_stat_map; | ||||
| dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G; | |||||
| dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE; | dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE; | ||||
| dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE; | dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE; | ||||
| dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT; | dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT; | ||||
| Context not available. | |||||
| dev->hw_attrs.uk_attrs.max_hw_wq_frags = ICRDMA_MAX_WQ_FRAGMENT_COUNT; | dev->hw_attrs.uk_attrs.max_hw_wq_frags = ICRDMA_MAX_WQ_FRAGMENT_COUNT; | ||||
| dev->hw_attrs.uk_attrs.max_hw_read_sges = ICRDMA_MAX_SGE_RD; | dev->hw_attrs.uk_attrs.max_hw_read_sges = ICRDMA_MAX_SGE_RD; | ||||
| dev->hw_attrs.uk_attrs.max_hw_wq_size = IRDMA_QP_WQE_MAX_SIZE; | dev->hw_attrs.uk_attrs.min_hw_wq_size = ICRDMA_MIN_WQ_SIZE; | ||||
| dev->hw_attrs.uk_attrs.min_sw_wq_size = IRDMA_QP_SW_MIN_WQSIZE; | |||||
| dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR; | dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR; | ||||
| disable_tx_spad(dev->hw); | disable_tx_spad(dev->hw); | ||||
| disable_prefetch(dev->hw); | disable_prefetch(dev->hw); | ||||
| Context not available. | |||||
| #define IRDMA_CWND_NO_FC 0x1 | #define IRDMA_CWND_NO_FC 0x1 | ||||
| #define IRDMA_CWND_FC 0x18 | #define IRDMA_CWND_FC 0x18 | ||||
| #define IRDMA_RTOMIN_NO_FC 0x5 | |||||
| #define IRDMA_RTOMIN_FC 0x32 | |||||
| #define IRDMA_ACKCREDS_NO_FC 0x02 | #define IRDMA_ACKCREDS_NO_FC 0x02 | ||||
| #define IRDMA_ACKCREDS_FC 0x06 | #define IRDMA_ACKCREDS_FC 0x06 | ||||
| Context not available. | |||||
| wr32(hw, GLPE_WQMTXIDXDATA, wqm_data); | wr32(hw, GLPE_WQMTXIDXDATA, wqm_data); | ||||
| } | } | ||||
| #define GL_RDPU_CNTRL 0x52054 | #define GL_RDPU_CNTRL 0x52054 | ||||
| void | void | ||||
| rdpu_ackreqpmthresh(struct irdma_hw *hw) | rdpu_ackreqpmthresh(struct irdma_hw *hw) | ||||
| { | { | ||||
| Context not available. | |||||