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sys/amd64/amd64/pmap.c
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* pages in the user page table are skipped. | * pages in the user page table are skipped. | ||||
* | * | ||||
* * Local invalidation, all modes. If the requested invalidation is | * * Local invalidation, all modes. If the requested invalidation is | ||||
* for a specific address or the total invalidation of a currently | * for a specific address or the total invalidation of a currently | ||||
* active pmap, then the TLB is flushed using INVLPG for a kernel | * active pmap, then the TLB is flushed using INVLPG for a kernel | ||||
* page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a | * page table, and INVPCID(INVPCID_CTXGLOB)/invltlb_glob() for a | ||||
* user space page table(s). | * user space page table(s). | ||||
* | * | ||||
* If the INVPCID instruction is available, it is used to flush entries | * If the INVPCID instruction is available, it is used to flush user | ||||
* from the kernel page table. | * entries from the kernel page table. | ||||
* | |||||
* When PCID is enabled, the INVLPG instruction invalidates all TLB | |||||
* entries for the given page for the current PCID, and all global | |||||
* TLB entries. This means that TLB entries for other PCIDs would | |||||
* be left stale. We avoid the problem by creating all kernel PTEs | |||||
* with the global flag (PG_G) set, when PTI is disabled. | |||||
alc: I would suggest:
"When PCID is enabled, the INVLPG instruction invalidates all TLB entries for… | |||||
* | * | ||||
* * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its | * * mode: PTI disabled, PCID present. The kernel reserves PCID 0 for its | ||||
* address space, all other 4095 PCIDs are used for user mode spaces | * address space, all other 4095 PCIDs are used for user mode spaces | ||||
* as described above. A context switch allocates a new PCID if | * as described above. A context switch allocates a new PCID if | ||||
* the recorded PCID is zero or the recorded generation does not match | * the recorded PCID is zero or the recorded generation does not match | ||||
* the CPU's generation, effectively flushing the TLB for this address space. | * the CPU's generation, effectively flushing the TLB for this address space. | ||||
* Total remote invalidation is performed by zeroing pm_gen for all CPUs. | * Total remote invalidation is performed by zeroing pm_gen for all CPUs. | ||||
* local user page: INVLPG | * local user page: INVLPG | ||||
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I would suggest:
"When PCID is enabled, the INVLPG instruction invalidates all TLB entries for the given page that either match the current PCID or are global. Since TLB entries for the same page under different PCIDs are unaffected, kernel pages which reside in all address spaces could be problematic. We avoid ...