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Differential D5078 Diff 12714 sys/mips/include/cpuregs.h

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sys/mips/include/cpuregs.h

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/* /*
* Cache Coherency Attributes: * Cache Coherency Attributes:
* UC: Uncached. * UC: Uncached.
* UA: Uncached accelerated. * UA: Uncached accelerated.
* C: Cacheable, coherency unspecified. * C: Cacheable, coherency unspecified.
* CNC: Cacheable non-coherent. * CNC: Cacheable non-coherent.
* CC: Cacheable coherent. * CC: Cacheable coherent.
* CCS: Cacheable coherent, shared read.
* CCE: Cacheable coherent, exclusive read. * CCE: Cacheable coherent, exclusive read.
* CCEW: Cacheable coherent, exclusive write. * CCEW: Cacheable coherent, exclusive write.
* CCUOW: Cacheable coherent, update on write. * CCUOW: Cacheable coherent, update on write.
* *
* Note that some bits vary in meaning across implementations (and that the * Note that some bits vary in meaning across implementations (and that the
* listing here is no doubt incomplete) and that the optimal cached mode varies * listing here is no doubt incomplete) and that the optimal cached mode varies
* between implementations. 0x02 is required to be UC and 0x03 is required to * between implementations. 0x02 is required to be UC and 0x03 is required to
* be a least C. * be a least C.
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#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
#endif #endif
#if defined(CPU_MIPS74K) #if defined(CPU_MIPS74K)
#define MIPS_CCA_UNCACHED 0x02 #define MIPS_CCA_UNCACHED 0x02
#define MIPS_CCA_CACHED 0x03 #define MIPS_CCA_CACHED 0x03
#endif #endif
#if defined(CPU_MIPS1004K) /*
#define MIPS_CCA_UNCACHED 0x02 * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
#define MIPS_CCA_CACHED 0x05 * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
* CCA 0x03 and Uncached Accelerated CCA 0x07
*/
#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
#define MIPS_CCA_CNC 0x03
#define MIPS_CCA_CCE 0x04
#define MIPS_CCA_CCS 0x05
#define MIPS_CCA_UA 0x07
/* We use shared read CCA for CACHED CCA */
#define MIPS_CCA_CACHED MIPS_CCA_CCS
#endif #endif
#ifndef MIPS_CCA_UNCACHED #ifndef MIPS_CCA_UNCACHED
#define MIPS_CCA_UNCACHED MIPS_CCA_UC #define MIPS_CCA_UNCACHED MIPS_CCA_UC
#endif #endif
/* /*
* If we don't know which cached mode to use and there is a cache coherent * If we don't know which cached mode to use and there is a cache coherent
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/* CPU dependent mtc0 hazard hook */ /* CPU dependent mtc0 hazard hook */
#if defined(CPU_CNMIPS) || defined(CPU_RMI) #if defined(CPU_CNMIPS) || defined(CPU_RMI)
#define COP0_SYNC #define COP0_SYNC
#elif defined(CPU_NLM) #elif defined(CPU_NLM)
#define COP0_SYNC .word 0xc0 /* ehb */ #define COP0_SYNC .word 0xc0 /* ehb */
#elif defined(CPU_SB1) #elif defined(CPU_SB1)
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) #elif defined(CPU_MIPS24K) || defined(CPU_MIPS24KE) || \
defined(CPU_MIPS34K) || defined(CPU_MIPS74K) || \
defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
/*
* According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
* "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
* removed, leaving only the EHB".
* Also, all MIPS32 Release 2 implementations have the EHB instruction, which
* resolves all execution hazards. The same goes for MIPS32 Release 3.
*/
#define COP0_SYNC .word 0xc0 /* ehb */ #define COP0_SYNC .word 0xc0 /* ehb */
#else #else
/* /*
* Pick a reasonable default based on the "typical" spacing described in the * Pick a reasonable default based on the "typical" spacing described in the
* "CP0 Hazards" chapter of MIPS Architecture Book Vol III. * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
*/ */
#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0; #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
#endif #endif
#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
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