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	#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)			#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
	#define MV_WIN_SATA_MAX 4			#define MV_WIN_SATA_MAX 4

	#if defined(SOC_MV_ARMADA38X)			#if defined(SOC_MV_ARMADA38X)
	#define MV_BOOTROM_MEM_ADDR 0xFFF00000			#define MV_BOOTROM_MEM_ADDR 0xFFF00000
	#define MV_BOOTROM_WIN_SIZE 0xF			#define MV_BOOTROM_WIN_SIZE 0xF
	#define MV_CPU_SUBSYS_REGS_LEN 0x100			#define MV_CPU_SUBSYS_REGS_LEN 0x100

				/* IO Window Control Register fields */
				#define IO_WIN_SIZE_SHIFT 16
				#define IO_WIN_SIZE_MASK 0xFFFF
				#define IO_WIN_ATTR_SHIFT 8
				#define IO_WIN_ATTR_MASK 0xFF
				#define IO_WIN_TGT_SHIFT 4
				#define IO_WIN_TGT_MASK 0xF
				#define IO_WIN_SYNC_SHIFT 1
				#define IO_WIN_SYNC_MASK 0x1
				#define IO_WIN_ENA_SHIFT 0
				#define IO_WIN_ENA_MASK 0x1

				#define IO_WIN_9_CTRL_OFFSET 0x98
				#define IO_WIN_9_BASE_OFFSET 0x9C

				/* Mbus decoding unit IDs and attributes */
				#define MBUS_BOOTROM_TGT_ID 0x1
				#define MBUS_BOOTROM_ATTR 0x1D

	/* Internal Units Sync Barrier Control Register */			/* Internal Units Sync Barrier Control Register */
	#define MV_SYNC_BARRIER_CTRL 0x84			#define MV_SYNC_BARRIER_CTRL 0x84
	#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF			#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
	#endif			#endif

	#define WIN_REG_IDX_RD(pre,reg,off,base) \			#define WIN_REG_IDX_RD(pre,reg,off,base) \
	static __inline uint32_t \			static __inline uint32_t \
	pre ## _ ## reg ## _read(int i) \			pre ## _ ## reg ## _read(int i) \
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