Differential D4425 Diff 12516 head/sys/arm/mv/armada38x/armada38x.c

Changeset View

Standalone View

head/sys/arm/mv/armada38x/armada38x.c

Show All 32 Lines
#include <sys/bus.h>		#include <sys/bus.h>

#include <machine/fdt.h>		#include <machine/fdt.h>

#include <arm/mv/mvwin.h>		#include <arm/mv/mvwin.h>
#include <arm/mv/mvreg.h>		#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>		#include <arm/mv/mvvar.h>

int armada38x_win_set_iosync_barrier(void);		int armada38x_open_bootrom_win(void);
int armada38x_scu_enable(void);		int armada38x_scu_enable(void);
		int armada38x_win_set_iosync_barrier(void);

uint32_t		uint32_t
get_tclk(void)		get_tclk(void)
{		{
uint32_t sar;		uint32_t sar;

/*		/*
* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.		* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
Show All 19 Lines	if (rv != 0)
return (rv);		return (rv);

/* Set Sync Barrier flags for all Mbus internal units */		/* Set Sync Barrier flags for all Mbus internal units */
bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,		bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,
MV_SYNC_BARRIER_CTRL_ALL);		MV_SYNC_BARRIER_CTRL_ALL);

bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,		bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,
MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);		MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);
		bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);

		return (rv);
		}

		int
		armada38x_open_bootrom_win(void)
		{
		bus_space_handle_t vaddr_iowind;
		uint32_t val;
		int rv;

		rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
		MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
		if (rv != 0)
		return (rv);

		val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT;
		val \|= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT;
		val \|= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT;
		/* Enable window and Sync Barrier */
		val \|= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT;
		val \|= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT;

		/* Configure IO Window Control Register */
		bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET,
		val);
		/* Configure IO Window Base Register */
		bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET,
		MV_BOOTROM_MEM_ADDR);

		bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN,
		BUS_SPACE_BARRIER_WRITE);
bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);		bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);

return (rv);		return (rv);
}		}

int		int
armada38x_scu_enable(void)		armada38x_scu_enable(void)
{		{
Show All 18 Lines