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Differential D4544 Diff 12001 sys/mips/nlm/xlp_simplebus.c

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sys/mips/nlm/xlp_simplebus.c

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#define PCI_ECFG_BASE XLP_DEFAULT_IO_BASE #define PCI_ECFG_BASE XLP_DEFAULT_IO_BASE
#define PCI_ECFG_LIMIT (XLP_DEFAULT_IO_BASE + 0x0fffffff) #define PCI_ECFG_LIMIT (XLP_DEFAULT_IO_BASE + 0x0fffffff)
/* /*
* Bus interface. * Bus interface.
*/ */
static int xlp_simplebus_probe(device_t dev); static int xlp_simplebus_probe(device_t dev);
static struct resource *xlp_simplebus_alloc_resource(device_t, device_t, int, static struct resource *xlp_simplebus_alloc_resource(device_t, device_t, int,
int *, u_long, u_long, u_long, u_int); int *, rman_res_t, rman_res_t, rman_res_t, u_int);
static int xlp_simplebus_activate_resource(device_t, device_t, int, static int xlp_simplebus_activate_resource(device_t, device_t, int,
int, struct resource *); int, struct resource *);
static int xlp_simplebus_setup_intr(device_t, device_t, static int xlp_simplebus_setup_intr(device_t, device_t,
struct resource *, int, driver_filter_t *, driver_intr_t *, void *, void **); struct resource *, int, driver_filter_t *, driver_intr_t *, void *, void **);
/* /*
* ofw_bus interface * ofw_bus interface
*/ */
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irq_rman.rm_end = 255; irq_rman.rm_end = 255;
irq_rman.rm_type = RMAN_ARRAY; irq_rman.rm_type = RMAN_ARRAY;
irq_rman.rm_descr = "PCI Mapped Interrupts"; irq_rman.rm_descr = "PCI Mapped Interrupts";
if (rman_init(&irq_rman) if (rman_init(&irq_rman)
|| rman_manage_region(&irq_rman, 0, 255)) || rman_manage_region(&irq_rman, 0, 255))
panic("xlp_simplebus_init_resources irq_rman"); panic("xlp_simplebus_init_resources irq_rman");
port_rman.rm_start = 0; port_rman.rm_start = 0;
port_rman.rm_end = ~0ul; port_rman.rm_end = ~0;
port_rman.rm_type = RMAN_ARRAY; port_rman.rm_type = RMAN_ARRAY;
port_rman.rm_descr = "I/O ports"; port_rman.rm_descr = "I/O ports";
if (rman_init(&port_rman) if (rman_init(&port_rman)
|| rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT)) || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT))
panic("xlp_simplebus_init_resources port_rman"); panic("xlp_simplebus_init_resources port_rman");
mem_rman.rm_start = 0; mem_rman.rm_start = 0;
mem_rman.rm_end = ~0ul; mem_rman.rm_end = ~0;
mem_rman.rm_type = RMAN_ARRAY; mem_rman.rm_type = RMAN_ARRAY;
mem_rman.rm_descr = "I/O memory"; mem_rman.rm_descr = "I/O memory";
if (rman_init(&mem_rman) if (rman_init(&mem_rman)
|| rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT)) || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT))
panic("xlp_simplebus_init_resources mem_rman"); panic("xlp_simplebus_init_resources mem_rman");
pci_ecfg_rman.rm_start = 0; pci_ecfg_rman.rm_start = 0;
pci_ecfg_rman.rm_end = ~0ul; pci_ecfg_rman.rm_end = ~0;
pci_ecfg_rman.rm_type = RMAN_ARRAY; pci_ecfg_rman.rm_type = RMAN_ARRAY;
pci_ecfg_rman.rm_descr = "PCI ECFG IO"; pci_ecfg_rman.rm_descr = "PCI ECFG IO";
if (rman_init(&pci_ecfg_rman) || rman_manage_region(&pci_ecfg_rman, if (rman_init(&pci_ecfg_rman) || rman_manage_region(&pci_ecfg_rman,
PCI_ECFG_BASE, PCI_ECFG_LIMIT)) PCI_ECFG_BASE, PCI_ECFG_LIMIT))
panic("xlp_simplebus_init_resources pci_ecfg_rman"); panic("xlp_simplebus_init_resources pci_ecfg_rman");
gbu_rman.rm_start = 0; gbu_rman.rm_start = 0;
gbu_rman.rm_end = ~0ul; gbu_rman.rm_end = ~0;
gbu_rman.rm_type = RMAN_ARRAY; gbu_rman.rm_type = RMAN_ARRAY;
gbu_rman.rm_descr = "Flash region"; gbu_rman.rm_descr = "Flash region";
if (rman_init(&gbu_rman) if (rman_init(&gbu_rman)
|| rman_manage_region(&gbu_rman, GBU_MEM_BASE, GBU_MEM_LIMIT)) || rman_manage_region(&gbu_rman, GBU_MEM_BASE, GBU_MEM_LIMIT))
panic("xlp_simplebus_init_resources gbu_rman"); panic("xlp_simplebus_init_resources gbu_rman");
} }
static int static int
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xlp_simplebus_init_resources(); xlp_simplebus_init_resources();
device_set_desc(dev, "XLP SoC bus"); device_set_desc(dev, "XLP SoC bus");
return (BUS_PROBE_SPECIFIC); return (BUS_PROBE_SPECIFIC);
} }
static struct resource * static struct resource *
xlp_simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid, xlp_simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags) rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{ {
struct rman *rm; struct rman *rm;
struct resource *rv; struct resource *rv;
struct resource_list_entry *rle; struct resource_list_entry *rle;
struct simplebus_softc *sc; struct simplebus_softc *sc;
struct simplebus_devinfo *di; struct simplebus_devinfo *di;
bus_space_tag_t bustag; bus_space_tag_t bustag;
int j, isdefault, passthrough, needsactivate; int j, isdefault, passthrough, needsactivate;
passthrough = (device_get_parent(child) != bus); passthrough = (device_get_parent(child) != bus);
needsactivate = flags & RF_ACTIVE; needsactivate = flags & RF_ACTIVE;
sc = device_get_softc(bus); sc = device_get_softc(bus);
di = device_get_ivars(child); di = device_get_ivars(child);
rle = NULL; rle = NULL;
bustag = NULL; bustag = NULL;
if (!passthrough) { if (!passthrough) {
isdefault = (start == 0UL && end == ~0UL); isdefault = (start == 0 && end == ~0);
if (isdefault) { if (isdefault) {
rle = resource_list_find(&di->rl, type, *rid); rle = resource_list_find(&di->rl, type, *rid);
if (rle == NULL) if (rle == NULL)
return (NULL); return (NULL);
if (rle->res != NULL) if (rle->res != NULL)
panic("%s: resource entry is busy", __func__); panic("%s: resource entry is busy", __func__);
start = rle->start; start = rle->start;
count = ulmax(count, rle->count); count = ulmax(count, rle->count);
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end -= sc->ranges[j].bus; end -= sc->ranges[j].bus;
end += sc->ranges[j].host; end += sc->ranges[j].host;
break; break;
} }
} }
if (j == sc->nranges && sc->nranges != 0) { if (j == sc->nranges && sc->nranges != 0) {
if (bootverbose) if (bootverbose)
device_printf(bus, "Could not map resource " device_printf(bus, "Could not map resource "
"%#lx-%#lx\n", start, end); "%#jx-%#jx\n", start, end);
return (NULL); return (NULL);
} }
} }
} }
switch (type) { switch (type) {
case SYS_RES_IRQ: case SYS_RES_IRQ:
rm = &irq_rman; rm = &irq_rman;
break; break;
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rm = &pci_ecfg_rman; rm = &pci_ecfg_rman;
bustag = rmi_uart_bus_space; bustag = rmi_uart_bus_space;
} else if (start >= PCIE_MEM_BASE && end <= PCIE_MEM_LIMIT) { } else if (start >= PCIE_MEM_BASE && end <= PCIE_MEM_LIMIT) {
rm = &mem_rman; rm = &mem_rman;
bustag = rmi_bus_space; bustag = rmi_bus_space;
} else { } else {
if (bootverbose) if (bootverbose)
device_printf(bus, "Invalid MEM range" device_printf(bus, "Invalid MEM range"
"%#lx-%#lx\n", start, end); "%#jx-%#jx\n", start, end);
return (NULL); return (NULL);
} }
break; break;
default: default:
return (NULL); return (NULL);
} }
rv = rman_reserve_resource(rm, start, end, count, flags, child); rv = rman_reserve_resource(rm, start, end, count, flags, child);
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