diff --git a/cad/qflow/Makefile b/cad/qflow/Makefile
index 8e3af7e328a5..aca8ba23305b 100644
--- a/cad/qflow/Makefile
+++ b/cad/qflow/Makefile
@@ -1,36 +1,36 @@
 PORTNAME=	qflow
-DISTVERSION=	1.4.103
+DISTVERSION=	1.4.104
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	End-to-end digital synthesis flow for ASIC designs
 WWW=		http://opencircuitdesign.com/qflow/
 
 LICENSE=	GPLv2
 
 APP_DEPENDS=	abc:cad/abc \
 		graywolf:cad/graywolf \
 		magic>0:cad/magic \
 		netgen-lvs>0:cad/netgen-lvs \
 		qrouter>0:cad/qrouter \
 		sta:cad/openroad \
 		yosys>0:cad/yosys
 BUILD_DEPENDS=	${APP_DEPENDS}
 RUN_DEPENDS=	${APP_DEPENDS}
 
 USES=		gmake python tar:tgz tcl tk
 USE_GITHUB=	yes
 GH_ACCOUNT=	RTimothyEdwards
 
 GNU_CONFIGURE=	yes
 
 post-patch:
 	@${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in
 	@${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in
 
 post-install:
 	@cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \
 		${STRIP_CMD} vlog2Spice vlog2Verilog vlog2Def vlog2Cel vlogFanout DEF2Verilog addspacers vesta spice2delay rc2dly blif2BSpice blif2Verilog blifFanout && \
 		${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6
 
 .include <bsd.port.mk>
diff --git a/cad/qflow/distinfo b/cad/qflow/distinfo
index 451648c41b30..075274938a79 100644
--- a/cad/qflow/distinfo
+++ b/cad/qflow/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1714976162
-SHA256 (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 8d04b14c94ae57e41efa4cdaa014150f57cd2f4fdccd48fb8bc50bac3ce06bea
-SIZE (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 946044
+TIMESTAMP = 1731246856
+SHA256 (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 48297322780cc2552a49f662b245809e8cb5fb286aac4b43734c36ff75f83c21
+SIZE (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 946203
diff --git a/cad/qflow/pkg-descr b/cad/qflow/pkg-descr
index a655ef084658..807bd2b6e372 100644
--- a/cad/qflow/pkg-descr
+++ b/cad/qflow/pkg-descr
@@ -1,9 +1,9 @@
 A digital synthesis flow is a set of tools and methods used to turn a circuit
-design written in a high-level behavioral language like verilog or VHDL into a
+design written in a high-level behavioral language like Verilog or VHDL into a
 physical circuit, which can either be configuration code for an FPGA target like
 a Xilinx or Altera chip, or a layout in a specific fabrication process
 technology, that would become part of a fabricated circuit chip. Several digital
 synthesis flows targeting FPGAs are available, usually from the FPGA
 manufacturers, and while they are typically not open source, they are generally
 distributed for free (presumably on the sensible assumption that more people
 will be buying more FPGA hardware).