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Do not expose to scheduler caches of single CPU.

Description

Do not expose to scheduler caches of single CPU.

Before this change my dual-Xeon(R) Gold 6242R always reported 3 levels
or topology (root, package/L3 and core/L2). But with SMT disabled
core/L2 matches thread, so additional topology level only causes more
traversal work. With this change SMT case is reported same as before,
while non-SMT is reported with only 2 much more simple levels.

MFC after: 2 weeks

(cherry picked from commit 5a49f1914178c5275105f2ab0d23a98118cd585f)

Details

Provenance
mavAuthored on Jul 28 2021, 8:15 PM
Parents
R10:42cb78bdd49c: pf: bound DIOCGETSTATES memory use
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