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diff --git a/sys/dev/bnxt/bnxt_en/bnxt.h b/sys/dev/bnxt/bnxt_en/bnxt.h
index 2faea00e4266..cf4f99077b58 100644
--- a/sys/dev/bnxt/bnxt_en/bnxt.h
+++ b/sys/dev/bnxt/bnxt_en/bnxt.h
@@ -1,1314 +1,1314 @@
/*-
* Broadcom NetXtreme-C/E network driver.
*
* Copyright (c) 2016 Broadcom, All Rights Reserved.
* The term Broadcom refers to Broadcom Limited and/or its subsidiaries
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
#ifndef _BNXT_H
#define _BNXT_H
#include <sys/param.h>
#include <sys/socket.h>
#include <sys/sysctl.h>
#include <sys/taskqueue.h>
#include <sys/bitstring.h>
#include <machine/bus.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_var.h>
#include <net/iflib.h>
#include <linux/types.h>
#include "hsi_struct_def.h"
#include "bnxt_dcb.h"
#include "bnxt_auxbus_compat.h"
#define DFLT_HWRM_CMD_TIMEOUT 500
/* PCI IDs */
#define BROADCOM_VENDOR_ID 0x14E4
#define BCM57301 0x16c8
#define BCM57302 0x16c9
#define BCM57304 0x16ca
#define BCM57311 0x16ce
#define BCM57312 0x16cf
#define BCM57314 0x16df
#define BCM57402 0x16d0
#define BCM57402_NPAR 0x16d4
#define BCM57404 0x16d1
#define BCM57404_NPAR 0x16e7
#define BCM57406 0x16d2
#define BCM57406_NPAR 0x16e8
#define BCM57407 0x16d5
#define BCM57407_NPAR 0x16ea
#define BCM57407_SFP 0x16e9
#define BCM57412 0x16d6
#define BCM57412_NPAR1 0x16de
#define BCM57412_NPAR2 0x16eb
#define BCM57414 0x16d7
#define BCM57414_NPAR1 0x16ec
#define BCM57414_NPAR2 0x16ed
#define BCM57416 0x16d8
#define BCM57416_NPAR1 0x16ee
#define BCM57416_NPAR2 0x16ef
#define BCM57416_SFP 0x16e3
#define BCM57417 0x16d9
#define BCM57417_NPAR1 0x16c0
#define BCM57417_NPAR2 0x16cc
#define BCM57417_SFP 0x16e2
#define BCM57454 0x1614
#define BCM58700 0x16cd
#define BCM57508 0x1750
#define BCM57504 0x1751
#define BCM57502 0x1752
#define NETXTREME_C_VF1 0x16cb
#define NETXTREME_C_VF2 0x16e1
#define NETXTREME_C_VF3 0x16e5
#define NETXTREME_E_VF1 0x16c1
#define NETXTREME_E_VF2 0x16d3
#define NETXTREME_E_VF3 0x16dc
#define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
#define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
#define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \
(((data2) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
#define BNXT_EVENT_DBR_EPOCH(data) \
(((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT)
#define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \
(((data2) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT)
#define EVENT_DATA2_NVM_ERR_ADDR(data2) \
(((data2) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT)
#define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING)
#define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE)
#define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \
HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE)
#define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \
((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK)
#define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \
((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK)
#define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \
(((data1) & \
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
#define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \
((data2) & \
HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
#define EVENT_DATA1_RECOVERY_ENABLED(data1) \
!!((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
#define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \
!!((data1) & \
HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
#define INVALID_STATS_CTX_ID -1
/* Maximum numbers of RX and TX descriptors. iflib requires this to be a power
* of two. The hardware has no particular limitation. */
#define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1)
#define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1)
#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
#define BNXT_MAX_MTU 9600
#define BNXT_RSS_HASH_TYPE_TCPV4 0
#define BNXT_RSS_HASH_TYPE_UDPV4 1
#define BNXT_RSS_HASH_TYPE_IPV4 2
#define BNXT_RSS_HASH_TYPE_TCPV6 3
#define BNXT_RSS_HASH_TYPE_UDPV6 4
#define BNXT_RSS_HASH_TYPE_IPV6 5
#define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F)
#define BNXT_NO_MORE_WOL_FILTERS 0xFFFF
#define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \
((softc)->flags & BNXT_FLAG_WOL_CAP ))
/* 64-bit doorbell */
#define DBR_INDEX_MASK 0x0000000000ffffffULL
#define DBR_PI_LO_MASK 0xff000000UL
#define DBR_PI_LO_SFT 24
#define DBR_XID_MASK 0x000fffff00000000ULL
#define DBR_XID_SFT 32
#define DBR_PI_HI_MASK 0xf0000000000000ULL
#define DBR_PI_HI_SFT 52
#define DBR_PATH_L2 (0x1ULL << 56)
#define DBR_VALID (0x1ULL << 58)
#define DBR_TYPE_SQ (0x0ULL << 60)
#define DBR_TYPE_RQ (0x1ULL << 60)
#define DBR_TYPE_SRQ (0x2ULL << 60)
#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
#define DBR_TYPE_CQ (0x4ULL << 60)
#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
#define DBR_TYPE_NQ (0xaULL << 60)
#define DBR_TYPE_NQ_ARM (0xbULL << 60)
#define DBR_TYPE_PUSH_START (0xcULL << 60)
#define DBR_TYPE_PUSH_END (0xdULL << 60)
#define DBR_TYPE_NULL (0xfULL << 60)
#define BNXT_MAX_L2_QUEUES 128
#define BNXT_ROCE_IRQ_COUNT 9
#define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT)
/* Completion related defines */
#define CMP_VALID(cmp, v_bit) \
((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) )
/* Chip class phase 5 */
#define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5))
#define DB_PF_OFFSET_P5 0x10000
#define DB_VF_OFFSET_P5 0x4000
#define NQ_VALID(cmp, v_bit) \
((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) )
#ifndef DIV_ROUND_UP
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif
#ifndef roundup
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#endif
#define NEXT_CP_CONS_V(ring, cons, v_bit) do { \
if (__predict_false(++(cons) == (ring)->ring_size)) \
((cons) = 0, (v_bit) = !v_bit); \
} while (0)
#define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \
0 : idx + 1)
#define CMPL_PREFETCH_NEXT(cpr, idx) \
__builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\
(CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \
((cpr)->ring.ring_size - 1)])
/* Lock macros */
#define BNXT_HWRM_LOCK_INIT(_softc, _name) \
mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF)
#define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock)
#define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock)
#define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock)
#define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \
MA_OWNED)
#define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \
((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \
(link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \
(link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg))
/* Chip info */
#define BNXT_TSO_SIZE UINT16_MAX
#define min_t(type, x, y) ({ \
type __min1 = (x); \
type __min2 = (y); \
__min1 < __min2 ? __min1 : __min2; })
#define max_t(type, x, y) ({ \
type __max1 = (x); \
type __max2 = (y); \
__max1 > __max2 ? __max1 : __max2; })
#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
#define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \
if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \
ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \
} while(0)
#define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */
#define BNXT_RX_STATS_EXT_OFFSET(counter) \
(offsetof(struct rx_port_stats_ext, counter) / 8)
#define BNXT_RX_STATS_EXT_NUM_LEGACY \
BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
#define BNXT_TX_STATS_EXT_OFFSET(counter) \
(offsetof(struct tx_port_stats_ext, counter) / 8)
extern const char bnxt_driver_version[];
typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx);
typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx);
typedef void (*bnxt_doorbell_rx_cq)(void *, bool);
typedef void (*bnxt_doorbell_tx_cq)(void *, bool);
typedef void (*bnxt_doorbell_nq)(void *, bool);
typedef struct bnxt_doorbell_ops {
bnxt_doorbell_tx bnxt_db_tx;
bnxt_doorbell_rx bnxt_db_rx;
bnxt_doorbell_rx_cq bnxt_db_rx_cq;
bnxt_doorbell_tx_cq bnxt_db_tx_cq;
bnxt_doorbell_nq bnxt_db_nq;
} bnxt_dooorbell_ops_t;
/* NVRAM access */
enum bnxt_nvm_directory_type {
BNX_DIR_TYPE_UNUSED = 0,
BNX_DIR_TYPE_PKG_LOG = 1,
BNX_DIR_TYPE_UPDATE = 2,
BNX_DIR_TYPE_CHIMP_PATCH = 3,
BNX_DIR_TYPE_BOOTCODE = 4,
BNX_DIR_TYPE_VPD = 5,
BNX_DIR_TYPE_EXP_ROM_MBA = 6,
BNX_DIR_TYPE_AVS = 7,
BNX_DIR_TYPE_PCIE = 8,
BNX_DIR_TYPE_PORT_MACRO = 9,
BNX_DIR_TYPE_APE_FW = 10,
BNX_DIR_TYPE_APE_PATCH = 11,
BNX_DIR_TYPE_KONG_FW = 12,
BNX_DIR_TYPE_KONG_PATCH = 13,
BNX_DIR_TYPE_BONO_FW = 14,
BNX_DIR_TYPE_BONO_PATCH = 15,
BNX_DIR_TYPE_TANG_FW = 16,
BNX_DIR_TYPE_TANG_PATCH = 17,
BNX_DIR_TYPE_BOOTCODE_2 = 18,
BNX_DIR_TYPE_CCM = 19,
BNX_DIR_TYPE_PCI_CFG = 20,
BNX_DIR_TYPE_TSCF_UCODE = 21,
BNX_DIR_TYPE_ISCSI_BOOT = 22,
BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26,
BNX_DIR_TYPE_EXT_PHY = 27,
BNX_DIR_TYPE_SHARED_CFG = 40,
BNX_DIR_TYPE_PORT_CFG = 41,
BNX_DIR_TYPE_FUNC_CFG = 42,
BNX_DIR_TYPE_MGMT_CFG = 48,
BNX_DIR_TYPE_MGMT_DATA = 49,
BNX_DIR_TYPE_MGMT_WEB_DATA = 50,
BNX_DIR_TYPE_MGMT_WEB_META = 51,
BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
};
enum bnxnvm_pkglog_field_index {
BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0,
BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1,
BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2,
BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3,
BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4,
BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
};
#define BNX_DIR_ORDINAL_FIRST 0
#define BNX_DIR_EXT_NONE 0
struct bnxt_bar_info {
struct resource *res;
bus_space_tag_t tag;
bus_space_handle_t handle;
bus_size_t size;
int rid;
};
struct bnxt_flow_ctrl {
bool rx;
bool tx;
bool autoneg;
};
struct bnxt_link_info {
uint8_t media_type;
uint8_t transceiver;
uint8_t phy_addr;
uint8_t phy_link_status;
uint8_t wire_speed;
uint8_t loop_back;
uint8_t link_up;
uint8_t last_link_up;
uint8_t duplex;
uint8_t last_duplex;
uint8_t last_phy_type;
struct bnxt_flow_ctrl flow_ctrl;
struct bnxt_flow_ctrl last_flow_ctrl;
uint8_t duplex_setting;
uint8_t auto_mode;
#define PHY_VER_LEN 3
uint8_t phy_ver[PHY_VER_LEN];
uint8_t phy_type;
#define BNXT_PHY_STATE_ENABLED 0
#define BNXT_PHY_STATE_DISABLED 1
uint8_t phy_state;
uint16_t link_speed;
uint16_t support_speeds;
uint16_t support_pam4_speeds;
uint16_t auto_link_speeds;
uint16_t auto_pam4_link_speeds;
uint16_t force_link_speed;
uint16_t force_pam4_link_speed;
bool force_pam4_speed_set_by_user;
uint16_t advertising;
uint16_t advertising_pam4;
uint32_t preemphasis;
uint16_t support_auto_speeds;
uint16_t support_force_speeds;
uint16_t support_pam4_auto_speeds;
uint16_t support_pam4_force_speeds;
#define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ
#define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4
uint8_t req_signal_mode;
uint8_t active_fec_sig_mode;
uint8_t sig_mode;
/* copy of requested setting */
uint8_t autoneg;
#define BNXT_AUTONEG_SPEED 1
#define BNXT_AUTONEG_FLOW_CTRL 2
uint8_t req_duplex;
uint16_t req_link_speed;
uint8_t module_status;
struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
};
enum bnxt_phy_type {
BNXT_MEDIA_CR = 0,
BNXT_MEDIA_LR,
BNXT_MEDIA_SR,
BNXT_MEDIA_KR,
BNXT_MEDIA_END
};
enum bnxt_cp_type {
BNXT_DEFAULT,
BNXT_TX,
BNXT_RX,
BNXT_SHARED
};
struct bnxt_queue_info {
uint8_t queue_id;
uint8_t queue_profile;
};
struct bnxt_func_info {
uint32_t fw_fid;
uint8_t mac_addr[ETHER_ADDR_LEN];
uint16_t max_rsscos_ctxs;
uint16_t max_cp_rings;
uint16_t max_tx_rings;
uint16_t max_rx_rings;
uint16_t max_hw_ring_grps;
uint16_t max_irqs;
uint16_t max_l2_ctxs;
uint16_t max_vnics;
uint16_t max_stat_ctxs;
};
struct bnxt_pf_info {
#define BNXT_FIRST_PF_FID 1
#define BNXT_FIRST_VF_FID 128
uint8_t port_id;
uint32_t first_vf_id;
uint16_t active_vfs;
uint16_t max_vfs;
uint32_t max_encap_records;
uint32_t max_decap_records;
uint32_t max_tx_em_flows;
uint32_t max_tx_wm_flows;
uint32_t max_rx_em_flows;
uint32_t max_rx_wm_flows;
unsigned long *vf_event_bmap;
uint16_t hwrm_cmd_req_pages;
void *hwrm_cmd_req_addr[4];
bus_addr_t hwrm_cmd_req_dma_addr[4];
};
struct bnxt_vf_info {
uint16_t fw_fid;
uint8_t mac_addr[ETHER_ADDR_LEN];
uint16_t max_rsscos_ctxs;
uint16_t max_cp_rings;
uint16_t max_tx_rings;
uint16_t max_rx_rings;
uint16_t max_hw_ring_grps;
uint16_t max_l2_ctxs;
uint16_t max_irqs;
uint16_t max_vnics;
uint16_t max_stat_ctxs;
uint32_t vlan;
#define BNXT_VF_QOS 0x1
#define BNXT_VF_SPOOFCHK 0x2
#define BNXT_VF_LINK_FORCED 0x4
#define BNXT_VF_LINK_UP 0x8
uint32_t flags;
uint32_t func_flags; /* func cfg flags */
uint32_t min_tx_rate;
uint32_t max_tx_rate;
void *hwrm_cmd_req_addr;
bus_addr_t hwrm_cmd_req_dma_addr;
};
#define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF))
#define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF)
struct bnxt_vlan_tag {
SLIST_ENTRY(bnxt_vlan_tag) next;
uint64_t filter_id;
uint16_t tag;
};
struct bnxt_vnic_info {
uint16_t id;
uint16_t def_ring_grp;
uint16_t cos_rule;
uint16_t lb_rule;
uint16_t mru;
uint32_t rx_mask;
struct iflib_dma_info mc_list;
int mc_list_count;
#define BNXT_MAX_MC_ADDRS 16
uint32_t flags;
#define BNXT_VNIC_FLAG_DEFAULT 0x01
#define BNXT_VNIC_FLAG_BD_STALL 0x02
#define BNXT_VNIC_FLAG_VLAN_STRIP 0x04
uint64_t filter_id;
uint16_t rss_id;
uint32_t rss_hash_type;
uint8_t rss_hash_key[HW_HASH_KEY_SIZE];
struct iflib_dma_info rss_hash_key_tbl;
struct iflib_dma_info rss_grp_tbl;
SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags;
struct iflib_dma_info vlan_tag_list;
};
struct bnxt_grp_info {
uint16_t stats_ctx;
uint16_t grp_id;
uint16_t rx_ring_id;
uint16_t cp_ring_id;
uint16_t ag_ring_id;
};
struct bnxt_ring {
uint64_t paddr;
vm_offset_t doorbell;
caddr_t vaddr;
struct bnxt_softc *softc;
uint32_t ring_size; /* Must be a power of two */
uint16_t id; /* Logical ID */
uint16_t phys_id;
uint16_t idx;
struct bnxt_full_tpa_start *tpa_start;
};
struct bnxt_cp_ring {
struct bnxt_ring ring;
struct if_irq irq;
uint32_t cons;
bool v_bit; /* Value of valid bit */
struct ctx_hw_stats *stats;
uint32_t stats_ctx_id;
uint32_t last_idx; /* Used by RX rings only
* set to the last read pidx
*/
uint64_t int_count;
};
struct bnxt_full_tpa_start {
struct rx_tpa_start_cmpl low;
struct rx_tpa_start_cmpl_hi high;
};
/* All the version information for the part */
#define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */
#define BNXT_NAME_SIZE 17
#define FW_VER_STR_LEN 32
#define BC_HWRM_STR_LEN 21
struct bnxt_ver_info {
uint8_t hwrm_if_major;
uint8_t hwrm_if_minor;
uint8_t hwrm_if_update;
char hwrm_if_ver[BNXT_VERSTR_SIZE];
char driver_hwrm_if_ver[BNXT_VERSTR_SIZE];
char mgmt_fw_ver[FW_VER_STR_LEN];
char netctrl_fw_ver[FW_VER_STR_LEN];
char roce_fw_ver[FW_VER_STR_LEN];
char fw_ver_str[FW_VER_STR_LEN];
char phy_ver[BNXT_VERSTR_SIZE];
char pkg_ver[64];
char hwrm_fw_name[BNXT_NAME_SIZE];
char mgmt_fw_name[BNXT_NAME_SIZE];
char netctrl_fw_name[BNXT_NAME_SIZE];
char roce_fw_name[BNXT_NAME_SIZE];
char phy_vendor[BNXT_NAME_SIZE];
char phy_partnumber[BNXT_NAME_SIZE];
uint16_t chip_num;
uint8_t chip_rev;
uint8_t chip_metal;
uint8_t chip_bond_id;
uint8_t chip_type;
uint8_t hwrm_min_major;
uint8_t hwrm_min_minor;
uint8_t hwrm_min_update;
uint64_t fw_ver_code;
#define BNXT_FW_VER_CODE(maj, min, bld, rsv) \
((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv))
#define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48)
#define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff)
#define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff)
#define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff)
struct sysctl_ctx_list ver_ctx;
struct sysctl_oid *ver_oid;
};
struct bnxt_nvram_info {
uint16_t mfg_id;
uint16_t device_id;
uint32_t sector_size;
uint32_t size;
uint32_t reserved_size;
uint32_t available_size;
struct sysctl_ctx_list nvm_ctx;
struct sysctl_oid *nvm_oid;
};
struct bnxt_func_qcfg {
uint16_t alloc_completion_rings;
uint16_t alloc_tx_rings;
uint16_t alloc_rx_rings;
uint16_t alloc_vnics;
};
struct bnxt_hw_lro {
uint16_t enable;
uint16_t is_mode_gro;
uint16_t max_agg_segs;
uint16_t max_aggs;
uint32_t min_agg_len;
};
/* The hardware supports certain page sizes. Use the supported page sizes
* to allocate the rings.
*/
#if (PAGE_SHIFT < 12)
#define BNXT_PAGE_SHIFT 12
#elif (PAGE_SHIFT <= 13)
#define BNXT_PAGE_SHIFT PAGE_SHIFT
#elif (PAGE_SHIFT < 16)
#define BNXT_PAGE_SHIFT 13
#else
#define BNXT_PAGE_SHIFT 16
#endif
#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
struct bnxt_ring_mem_info {
int nr_pages;
int page_size;
uint16_t flags;
#define BNXT_RMEM_VALID_PTE_FLAG 1
#define BNXT_RMEM_RING_PTE_FLAG 2
#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
uint16_t depth;
struct bnxt_ctx_mem_type *ctx_mem;
struct iflib_dma_info *pg_arr;
struct iflib_dma_info pg_tbl;
int vmem_size;
void **vmem;
};
struct bnxt_ctx_pg_info {
uint32_t entries;
uint32_t nr_pages;
struct iflib_dma_info ctx_arr[MAX_CTX_PAGES];
struct bnxt_ring_mem_info ring_mem;
struct bnxt_ctx_pg_info **ctx_pg_tbl;
};
#define BNXT_MAX_TQM_SP_RINGS 1
#define BNXT_MAX_TQM_FP_LEGACY_RINGS 8
#define BNXT_MAX_TQM_FP_RINGS 9
#define BNXT_MAX_TQM_LEGACY_RINGS \
(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS)
#define BNXT_MAX_TQM_RINGS \
(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
#define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256
#define BNXT_BACKING_STORE_CFG_LEN \
sizeof(struct hwrm_func_backing_store_cfg_input)
#define BNXT_SET_CTX_PAGE_ATTR(attr) \
do { \
if (BNXT_PAGE_SIZE == 0x2000) \
attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_SRQ_PG_SIZE_PG_8K; \
else if (BNXT_PAGE_SIZE == 0x10000) \
attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_64K; \
else \
attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_4K; \
} while (0)
struct bnxt_ctx_mem_type {
u16 type;
u16 entry_size;
u32 flags;
#define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID
u32 instance_bmap;
u8 init_value;
u8 entry_multiple;
u16 init_offset;
#define BNXT_CTX_INIT_INVALID_OFFSET 0xffff
u32 max_entries;
u32 min_entries;
u8 split_entry_cnt;
#define BNXT_MAX_SPLIT_ENTRY 4
union {
struct {
u32 qp_l2_entries;
u32 qp_qp1_entries;
};
u32 srq_l2_entries;
u32 cq_l2_entries;
u32 vnic_entries;
struct {
u32 mrav_av_entries;
u32 mrav_num_entries_units;
};
u32 split[BNXT_MAX_SPLIT_ENTRY];
};
struct bnxt_ctx_pg_info *pg_info;
};
#define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP
#define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ
#define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ
#define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC
#define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT
#define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING
#define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING
#define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV
#define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM
#define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC
#define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC
#define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING
#define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW
#define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW
#define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW
#define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW
#define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC
#define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC
-#define BNXT_CTX_MAX (BNXT_CTX_QRKC + 1)
+#define BNXT_CTX_MAX (BNXT_CTX_TIM + 1)
struct bnxt_ctx_mem_info {
u8 tqm_fp_rings_count;
u32 flags;
#define BNXT_CTX_FLAG_INITED 0x01
struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_MAX];
};
struct bnxt_hw_resc {
uint16_t min_rsscos_ctxs;
uint16_t max_rsscos_ctxs;
uint16_t min_cp_rings;
uint16_t max_cp_rings;
uint16_t resv_cp_rings;
uint16_t min_tx_rings;
uint16_t max_tx_rings;
uint16_t resv_tx_rings;
uint16_t max_tx_sch_inputs;
uint16_t min_rx_rings;
uint16_t max_rx_rings;
uint16_t resv_rx_rings;
uint16_t min_hw_ring_grps;
uint16_t max_hw_ring_grps;
uint16_t resv_hw_ring_grps;
uint16_t min_l2_ctxs;
uint16_t max_l2_ctxs;
uint16_t min_vnics;
uint16_t max_vnics;
uint16_t resv_vnics;
uint16_t min_stat_ctxs;
uint16_t max_stat_ctxs;
uint16_t resv_stat_ctxs;
uint16_t max_nqs;
uint16_t max_irqs;
uint16_t resv_irqs;
};
enum bnxt_type_ets {
BNXT_TYPE_ETS_TSA = 0,
BNXT_TYPE_ETS_PRI2TC,
BNXT_TYPE_ETS_TCBW,
BNXT_TYPE_ETS_MAX
};
static const char *const BNXT_ETS_TYPE_STR[] = {
"tsa",
"pri2tc",
"tcbw",
};
static const char *const BNXT_ETS_HELP_STR[] = {
"X is 1 (strict), 0 (ets)",
"TC values for pri 0 to 7",
"TC BW values for pri 0 to 7, Sum should be 100",
};
#define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len)
struct bnxt_softc_list {
SLIST_ENTRY(bnxt_softc_list) next;
struct bnxt_softc *softc;
};
#ifndef BIT_ULL
#define BIT_ULL(nr) (1ULL << (nr))
#endif
struct bnxt_aux_dev {
struct auxiliary_device aux_dev;
struct bnxt_en_dev *edev;
int id;
};
struct bnxt_msix_tbl {
uint32_t entry;
uint32_t vector;
};
enum bnxt_health_severity {
SEVERITY_NORMAL = 0,
SEVERITY_WARNING,
SEVERITY_RECOVERABLE,
SEVERITY_FATAL,
};
enum bnxt_health_remedy {
REMEDY_DEVLINK_RECOVER,
REMEDY_POWER_CYCLE_DEVICE,
REMEDY_POWER_CYCLE_HOST,
REMEDY_FW_UPDATE,
REMEDY_HW_REPLACE,
};
struct bnxt_fw_health {
u32 flags;
u32 polling_dsecs;
u32 master_func_wait_dsecs;
u32 normal_func_wait_dsecs;
u32 post_reset_wait_dsecs;
u32 post_reset_max_wait_dsecs;
u32 regs[4];
u32 mapped_regs[4];
#define BNXT_FW_HEALTH_REG 0
#define BNXT_FW_HEARTBEAT_REG 1
#define BNXT_FW_RESET_CNT_REG 2
#define BNXT_FW_RESET_INPROG_REG 3
u32 fw_reset_inprog_reg_mask;
u32 last_fw_heartbeat;
u32 last_fw_reset_cnt;
u8 enabled:1;
u8 primary:1;
u8 status_reliable:1;
u8 resets_reliable:1;
u8 tmr_multiplier;
u8 tmr_counter;
u8 fw_reset_seq_cnt;
u32 fw_reset_seq_regs[16];
u32 fw_reset_seq_vals[16];
u32 fw_reset_seq_delay_msec[16];
u32 echo_req_data1;
u32 echo_req_data2;
struct devlink_health_reporter *fw_reporter;
struct mutex lock;
enum bnxt_health_severity severity;
enum bnxt_health_remedy remedy;
u32 arrests;
u32 discoveries;
u32 survivals;
u32 fatalities;
u32 diagnoses;
};
#define BNXT_FW_HEALTH_REG_TYPE_MASK 3
#define BNXT_FW_HEALTH_REG_TYPE_CFG 0
#define BNXT_FW_HEALTH_REG_TYPE_GRC 1
#define BNXT_FW_HEALTH_REG_TYPE_BAR0 2
#define BNXT_FW_HEALTH_REG_TYPE_BAR1 3
#define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
#define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
#define BNXT_FW_HEALTH_WIN_BASE 0x3000
#define BNXT_FW_HEALTH_WIN_MAP_OFF 8
#define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \
((reg) & BNXT_GRC_OFFSET_MASK))
#define BNXT_FW_STATUS_HEALTH_MSK 0xffff
#define BNXT_FW_STATUS_HEALTHY 0x8000
#define BNXT_FW_STATUS_SHUTDOWN 0x100000
#define BNXT_FW_STATUS_RECOVERING 0x400000
#define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
BNXT_FW_STATUS_HEALTHY)
#define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
BNXT_FW_STATUS_HEALTHY)
#define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
BNXT_FW_STATUS_HEALTHY)
#define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \
((sts) & BNXT_FW_STATUS_RECOVERING))
#define BNXT_FW_RETRY 5
#define BNXT_FW_IF_RETRY 10
#define BNXT_FW_SLOT_RESET_RETRY 4
#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
#define BNXT_GRCPF_REG_SYNC_TIME 0x480
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ 0x488
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK 0xffffffUL
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT 0
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK 0x1f000000UL
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT 24
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK 0x20000000UL
#define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT 29
#define BNXT_GRC_REG_STATUS_P5 0x520
#define BNXT_GRCPF_REG_KONG_COMM 0xA00
#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
#define BNXT_CAG_REG_BASE 0x300000
#define BNXT_GRC_REG_CHIP_NUM 0x48
#define BNXT_GRC_REG_BASE 0x260000
#define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c
#define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810
#define BNXT_GRC_BASE_MASK 0xfffff000
#define BNXT_GRC_OFFSET_MASK 0x00000ffc
struct bnxt_softc {
device_t dev;
if_ctx_t ctx;
if_softc_ctx_t scctx;
if_shared_ctx_t sctx;
if_t ifp;
uint32_t domain;
uint32_t bus;
uint32_t slot;
uint32_t function;
uint32_t dev_fn;
struct ifmedia *media;
struct bnxt_ctx_mem_info *ctx_mem;
struct bnxt_hw_resc hw_resc;
struct bnxt_softc_list list;
struct bnxt_bar_info hwrm_bar;
struct bnxt_bar_info doorbell_bar;
struct bnxt_link_info link_info;
#define BNXT_FLAG_VF 0x0001
#define BNXT_FLAG_NPAR 0x0002
#define BNXT_FLAG_WOL_CAP 0x0004
#define BNXT_FLAG_SHORT_CMD 0x0008
#define BNXT_FLAG_FW_CAP_NEW_RM 0x0010
#define BNXT_FLAG_CHIP_P5 0x0020
#define BNXT_FLAG_TPA 0x0040
#define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080
#define BNXT_FLAG_MULTI_HOST 0x0100
#define BNXT_FLAG_MULTI_ROOT 0x0200
#define BNXT_FLAG_ROCEV1_CAP 0x0400
#define BNXT_FLAG_ROCEV2_CAP 0x0800
#define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP)
uint32_t flags;
#define BNXT_STATE_LINK_CHANGE (0)
#define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1)
bitstr_t *state_bv;
uint32_t total_irqs;
struct bnxt_msix_tbl *irq_tbl;
struct bnxt_func_info func;
struct bnxt_func_qcfg fn_qcfg;
struct bnxt_pf_info pf;
struct bnxt_vf_info vf;
uint16_t hwrm_cmd_seq;
uint32_t hwrm_cmd_timeo; /* milliseconds */
struct iflib_dma_info hwrm_cmd_resp;
struct iflib_dma_info hwrm_short_cmd_req_addr;
/* Interrupt info for HWRM */
struct if_irq irq;
struct mtx hwrm_lock;
uint16_t hwrm_max_req_len;
uint16_t hwrm_max_ext_req_len;
uint32_t hwrm_spec_code;
#define BNXT_MAX_QUEUE 8
uint8_t max_tc;
uint8_t max_lltc;
struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE];
struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE];
uint8_t tc_to_qidx[BNXT_MAX_QUEUE];
uint8_t tx_q_ids[BNXT_MAX_QUEUE];
uint8_t rx_q_ids[BNXT_MAX_QUEUE];
uint8_t tx_max_q;
uint8_t rx_max_q;
uint8_t is_asym_q;
struct bnxt_ieee_ets *ieee_ets;
struct bnxt_ieee_pfc *ieee_pfc;
uint8_t dcbx_cap;
uint8_t default_pri;
uint8_t max_dscp_value;
uint64_t admin_ticks;
struct iflib_dma_info hw_rx_port_stats;
struct iflib_dma_info hw_tx_port_stats;
struct rx_port_stats *rx_port_stats;
struct tx_port_stats *tx_port_stats;
struct iflib_dma_info hw_tx_port_stats_ext;
struct iflib_dma_info hw_rx_port_stats_ext;
struct tx_port_stats_ext *tx_port_stats_ext;
struct rx_port_stats_ext *rx_port_stats_ext;
uint16_t fw_rx_stats_ext_size;
uint16_t fw_tx_stats_ext_size;
uint16_t hw_ring_stats_size;
uint8_t tx_pri2cos_idx[8];
uint8_t rx_pri2cos_idx[8];
bool pri2cos_valid;
uint64_t tx_bytes_pri[8];
uint64_t tx_packets_pri[8];
uint64_t rx_bytes_pri[8];
uint64_t rx_packets_pri[8];
uint8_t port_count;
int num_cp_rings;
struct bnxt_cp_ring *nq_rings;
struct bnxt_ring *tx_rings;
struct bnxt_cp_ring *tx_cp_rings;
struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES];
int ntxqsets;
struct bnxt_vnic_info vnic_info;
struct bnxt_ring *ag_rings;
struct bnxt_ring *rx_rings;
struct bnxt_cp_ring *rx_cp_rings;
struct bnxt_grp_info *grp_info;
struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES];
int nrxqsets;
uint16_t rx_buf_size;
struct bnxt_cp_ring def_cp_ring;
struct bnxt_cp_ring def_nq_ring;
struct iflib_dma_info def_cp_ring_mem;
struct iflib_dma_info def_nq_ring_mem;
struct grouptask def_cp_task;
int db_size;
int legacy_db_size;
struct bnxt_doorbell_ops db_ops;
struct sysctl_ctx_list hw_stats;
struct sysctl_oid *hw_stats_oid;
struct sysctl_ctx_list hw_lro_ctx;
struct sysctl_oid *hw_lro_oid;
struct sysctl_ctx_list flow_ctrl_ctx;
struct sysctl_oid *flow_ctrl_oid;
struct sysctl_ctx_list dcb_ctx;
struct sysctl_oid *dcb_oid;
struct bnxt_ver_info *ver_info;
struct bnxt_nvram_info *nvm_info;
bool wol;
bool is_dev_init;
struct bnxt_hw_lro hw_lro;
uint8_t wol_filter_id;
uint16_t rx_coal_usecs;
uint16_t rx_coal_usecs_irq;
uint16_t rx_coal_frames;
uint16_t rx_coal_frames_irq;
uint16_t tx_coal_usecs;
uint16_t tx_coal_usecs_irq;
uint16_t tx_coal_frames;
uint16_t tx_coal_frames_irq;
#define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
#define BNXT_DEF_STATS_COAL_TICKS 1000000
#define BNXT_MIN_STATS_COAL_TICKS 250000
#define BNXT_MAX_STATS_COAL_TICKS 1000000
uint64_t fw_cap;
#define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
#define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
#define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
#define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
#define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
#define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5)
#define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6)
#define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
#define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8)
#define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9)
#define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
#define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
#define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12)
#define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
#define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
#define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
#define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
#define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19)
#define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
#define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
#define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23)
#define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
#define BNXT_FW_CAP_CFA_EEM BIT_ULL(27)
#define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29)
#define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
#define BNXT_FW_CAP_ECN_STATS BIT_ULL(31)
#define BNXT_FW_CAP_TRUFLOW BIT_ULL(32)
#define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33)
#define BNXT_FW_CAP_PTP_PPS BIT_ULL(34)
#define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35)
#define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36)
#define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37)
#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38)
#define BNXT_FW_CAP_PTP_RTC BIT_ULL(39)
#define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40)
#define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41)
#define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42)
#define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43)
#define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44)
#define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45)
#define BNXT_FW_CAP_PTP_PTM BIT_ULL(46)
#define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47)
#define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48)
#define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49)
uint32_t lpi_tmr_lo;
uint32_t lpi_tmr_hi;
/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
uint16_t phy_flags;
#define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED
#define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED
#define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED
#define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED
#define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
#define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
#define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN
#define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS
#define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8)
#define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8)
#define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8)
struct bnxt_aux_dev *aux_dev;
struct net_device *net_dev;
struct mtx en_ops_lock;
uint8_t port_partition_type;
struct bnxt_en_dev *edev;
unsigned long state;
#define BNXT_STATE_OPEN 0
#define BNXT_STATE_IN_SP_TASK 1
#define BNXT_STATE_READ_STATS 2
#define BNXT_STATE_FW_RESET_DET 3
#define BNXT_STATE_IN_FW_RESET 4
#define BNXT_STATE_ABORT_ERR 5
#define BNXT_STATE_FW_FATAL_COND 6
#define BNXT_STATE_DRV_REGISTERED 7
#define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8
#define BNXT_STATE_NAPI_DISABLED 9
#define BNXT_STATE_L2_FILTER_RETRY 10
#define BNXT_STATE_FW_ACTIVATE 11
#define BNXT_STATE_RECOVER 12
#define BNXT_STATE_FW_NON_FATAL_COND 13
#define BNXT_STATE_FW_ACTIVATE_RESET 14
#define BNXT_STATE_HALF_OPEN 15
#define BNXT_NO_FW_ACCESS(bp) \
test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state)
struct pci_dev *pdev;
struct work_struct sp_task;
unsigned long sp_event;
#define BNXT_RX_MASK_SP_EVENT 0
#define BNXT_RX_NTP_FLTR_SP_EVENT 1
#define BNXT_LINK_CHNG_SP_EVENT 2
#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
#define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
#define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
#define BNXT_RESET_TASK_SP_EVENT 6
#define BNXT_RST_RING_SP_EVENT 7
#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
#define BNXT_PERIODIC_STATS_SP_EVENT 9
#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
#define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
#define BNXT_FLOW_STATS_SP_EVENT 15
#define BNXT_UPDATE_PHY_SP_EVENT 16
#define BNXT_RING_COAL_NOW_SP_EVENT 17
#define BNXT_FW_RESET_NOTIFY_SP_EVENT 18
#define BNXT_FW_EXCEPTION_SP_EVENT 19
#define BNXT_VF_VNIC_CHANGE_SP_EVENT 20
#define BNXT_LINK_CFG_CHANGE_SP_EVENT 21
#define BNXT_PTP_CURRENT_TIME_EVENT 22
#define BNXT_FW_ECHO_REQUEST_SP_EVENT 23
#define BNXT_VF_CFG_CHNG_SP_EVENT 24
struct delayed_work fw_reset_task;
int fw_reset_state;
#define BNXT_FW_RESET_STATE_POLL_VF 1
#define BNXT_FW_RESET_STATE_RESET_FW 2
#define BNXT_FW_RESET_STATE_ENABLE_DEV 3
#define BNXT_FW_RESET_STATE_POLL_FW 4
#define BNXT_FW_RESET_STATE_OPENING 5
#define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6
u16 fw_reset_min_dsecs;
#define BNXT_DFLT_FW_RST_MIN_DSECS 20
u16 fw_reset_max_dsecs;
#define BNXT_DFLT_FW_RST_MAX_DSECS 60
unsigned long fw_reset_timestamp;
struct bnxt_fw_health *fw_health;
};
struct bnxt_filter_info {
STAILQ_ENTRY(bnxt_filter_info) next;
uint64_t fw_l2_filter_id;
#define INVALID_MAC_INDEX ((uint16_t)-1)
uint16_t mac_index;
/* Filter Characteristics */
uint32_t flags;
uint32_t enables;
uint8_t l2_addr[ETHER_ADDR_LEN];
uint8_t l2_addr_mask[ETHER_ADDR_LEN];
uint16_t l2_ovlan;
uint16_t l2_ovlan_mask;
uint16_t l2_ivlan;
uint16_t l2_ivlan_mask;
uint8_t t_l2_addr[ETHER_ADDR_LEN];
uint8_t t_l2_addr_mask[ETHER_ADDR_LEN];
uint16_t t_l2_ovlan;
uint16_t t_l2_ovlan_mask;
uint16_t t_l2_ivlan;
uint16_t t_l2_ivlan_mask;
uint8_t tunnel_type;
uint16_t mirror_vnic_id;
uint32_t vni;
uint8_t pri_hint;
uint64_t l2_filter_id_hint;
};
#define I2C_DEV_ADDR_A0 0xa0
#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
/* Function declarations */
void bnxt_report_link(struct bnxt_softc *softc);
bool bnxt_check_hwrm_version(struct bnxt_softc *softc);
struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name);
int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr,
uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr,
uint16_t data_length, uint8_t *buf);
void bnxt_dcb_init(struct bnxt_softc *softc);
void bnxt_dcb_free(struct bnxt_softc *softc);
uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode);
uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc);
int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets);
int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets);
uint8_t get_phy_type(struct bnxt_softc *softc);
int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc);
int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc);
int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app);
int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app);
int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, int *num_inputs);
#endif /* _BNXT_H */
diff --git a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
index 4aec765e1b26..baecfc8f659c 100644
--- a/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
+++ b/sys/dev/bnxt/bnxt_en/hsi_struct_def.h
@@ -1,78386 +1,91515 @@
/*-
* BSD LICENSE
*
- * Copyright (c) 2016 Broadcom, All Rights Reserved.
+ * Copyright (c) 2024 Broadcom, All Rights Reserved.
* The term Broadcom refers to Broadcom Limited and/or its subsidiaries
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
- * Copyright(c) 2001-2023, Broadcom. All rights reserved. The
+ * Copyright(c) 2001-2024, Broadcom. All rights reserved. The
* term Broadcom refers to Broadcom Inc. and/or its subsidiaries.
* Proprietary and Confidential Information.
*
* This source file is the property of Broadcom Corporation, and
* may not be copied or distributed in any isomorphic form without
* the prior written consent of Broadcom Corporation.
*
* DO NOT MODIFY!!! This file is automatically generated.
*/
#ifndef _HSI_STRUCT_DEF_H_
#define _HSI_STRUCT_DEF_H_
+#if defined(HAVE_STDINT_H)
+#include <stdint.h>
+#endif
+
/* This is the HWRM command header. */
/* hwrm_cmd_hdr (size:128b/16B) */
typedef struct hwrm_cmd_hdr {
/* The HWRM command request type. */
uint16_t req_type;
/*
* The completion ring to send the completion event on. This should
* be the NQ ID returned from the `nq_alloc` HWRM command.
*/
uint16_t cmpl_ring;
/*
* The sequence ID is used by the driver for tracking multiple
* commands. This ID is treated as opaque data by the firmware and
* the value is returned in the `hwrm_resp_hdr` upon completion.
*/
uint16_t seq_id;
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
* * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
* * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
/*
* A physical address pointer pointing to a host buffer that the
* command's response data will be written. This can be either a host
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
*/
- uint64_t resp_addr;
+ uint64_t resp_addr;
} hwrm_cmd_hdr_t, *phwrm_cmd_hdr_t;
/* This is the HWRM response header. */
/* hwrm_resp_hdr (size:64b/8B) */
typedef struct hwrm_resp_hdr {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t req_type;
/* The sequence ID from the original command. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
} hwrm_resp_hdr_t, *phwrm_resp_hdr_t;
/*
* TLV encapsulated message. Use the TLV type field of the
* TLV to determine the type of message encapsulated.
*/
#define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP
/* HWRM request message */
#define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
/* HWRM response message */
#define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
+/* RoCE slow path command to query CC Gen2 support. */
+#define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6)
+/* RoCE slow path command to modify CC Gen2 support. */
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7)
/* Engine CKV - The Alias key EC curve and ECC public key information. */
#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
/* Engine CKV - Initialization vector. */
#define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
/* Engine CKV - Authentication tag. */
#define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
/* Engine CKV - The encrypted data. */
#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
/* Engine CKV - Supported host_algorithms. */
#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
/* Engine CKV - The Host EC curve name and ECC public key information. */
#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
/* Engine CKV - The ECDSA signature. */
#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
/* Engine CKV - The firmware EC curve name and ECC public key information. */
#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
/* Engine CKV - Supported firmware algorithms. */
#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
/* tlv (size:64b/8B) */
typedef struct tlv {
/*
* The command discriminator is used to differentiate between various
* types of HWRM messages. This includes legacy HWRM and RoCE slowpath
* command messages as well as newer TLV encapsulated HWRM commands.
*
* For TLV encapsulated messages this field must be 0x8000.
*/
uint16_t cmd_discr;
uint8_t reserved_8b;
uint8_t flags;
/*
* Indicates the presence of additional TLV encapsulated data
* follows this TLV.
*/
#define TLV_FLAGS_MORE UINT32_C(0x1)
/* Last TLV in a sequence of TLVs. */
#define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
/* More TLVs follow this TLV. */
#define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
/*
* When an HWRM receiver detects a TLV type that it does not
* support with the TLV required flag set, the receiver must
* reject the HWRM message with an error code indicating an
* unsupported TLV type.
*/
#define TLV_FLAGS_REQUIRED UINT32_C(0x2)
/* No */
#define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
/* Yes */
#define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
#define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
/*
* This field defines the TLV type value which is divided into
* two ranges to differentiate between global and local TLV types.
* Global TLV types must be unique across all defined TLV types.
* Local TLV types are valid only for extensions to a given
* HWRM message and may be repeated across different HWRM message
* types. There is a direct correlation of each HWRM message type
* to a single global TLV type value.
*
* Global TLV range: `0 - (63k-1)`
*
* Local TLV range: `63k - (64k-1)`
*/
uint16_t tlv_type;
/*
* Length of the message data encapsulated by this TLV in bytes.
* This length does not include the size of the TLV header itself
* and it must be an integer multiple of 8B.
*/
uint16_t length;
} tlv_t, *ptlv_t;
/* Input */
/* input (size:128b/16B) */
typedef struct input {
/*
- * This value indicates what type of request this is. The format
+ * This value indicates what type of request this is. The format
* for the rest of the command is determined by this field.
*/
uint16_t req_type;
/*
* This value indicates the what completion ring the request will
- * be optionally completed on. If the value is -1, then no
- * CR completion will be generated. Any other value must be a
+ * be optionally completed on. If the value is -1, then no
+ * CR completion will be generated. Any other value must be a
* valid CR ring_id value for this function.
*/
uint16_t cmpl_ring;
/* This value indicates the command sequence number. */
uint16_t seq_id;
/*
* Target ID of this command.
*
* 0x0 - 0xFFF8 - Used for function ids
* 0xFFF8 - 0xFFFE - Reserved for internal processors
* 0xFFFF - HWRM
*/
uint16_t target_id;
/*
* This is the host address where the response will be written
- * when the request is complete. This area must be 16B aligned
+ * when the request is complete. This area must be 16B aligned
* and must be cleared to zero before the request is made.
*/
uint64_t resp_addr;
} input_t, *pinput_t;
/* Output */
/* output (size:64b/8B) */
typedef struct output {
/*
* Pass/Fail or error type
*
* Note: receiver to verify the in parameters, and fail the call
* with an error when appropriate
*/
uint16_t error_code;
/* This field returns the type of original request. */
uint16_t req_type;
/* This field provides original sequence number of the command. */
uint16_t seq_id;
/*
- * This field is the length of the response in bytes. The
+ * This field is the length of the response in bytes. The
* last byte of the response is a valid flag that will read
* as '1' when the command has been completely written to
* memory.
*/
uint16_t resp_len;
} output_t, *poutput_t;
/* Short Command Structure */
/* hwrm_short_input (size:128b/16B) */
typedef struct hwrm_short_input {
/*
* This field indicates the type of request in the request buffer.
* The format for the rest of the command (request) is determined
* by this field.
*/
uint16_t req_type;
/*
* This field indicates a signature that is used to identify short
* form of the command listed here. This field shall be set to
* 17185 (0x4321).
*/
uint16_t signature;
/* Signature indicating this is a short form of HWRM command */
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
/* The target ID of the command */
uint16_t target_id;
/* Default target_id (0x0) to maintain compatibility with old driver */
#define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
/* Reserved for user-space HWRM interface */
#define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
#define HWRM_SHORT_INPUT_TARGET_ID_LAST HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
* This is the host address where the request was written.
* This area must be 16B aligned.
*/
uint64_t req_addr;
} hwrm_short_input_t, *phwrm_short_input_t;
#define GET_HWRM_REQ_TYPE(x) \
(((x) < 0x80) ? \
((x) == 0x0 ? "HWRM_VER_GET": \
((x) == 0xb ? "HWRM_FUNC_ECHO_RESPONSE": \
((x) == 0xc ? "HWRM_ERROR_RECOVERY_QCFG": \
((x) == 0xd ? "HWRM_FUNC_DRV_IF_CHANGE": \
((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
((x) == 0x10 ? "HWRM_RESERVED1": \
((x) == 0x11 ? "HWRM_FUNC_RESET": \
((x) == 0x12 ? "HWRM_FUNC_GETFID": \
((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
((x) == 0x16 ? "HWRM_FUNC_QCFG": \
((x) == 0x17 ? "HWRM_FUNC_CFG": \
((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
((x) == 0x23 ? "HWRM_PORT_QSTATS": \
((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
((x) == 0x29 ? "HWRM_PORT_MAC_PTP_QCFG": \
((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
((x) == 0x2d ? "HWRM_PORT_LED_CFG": \
((x) == 0x2e ? "HWRM_PORT_LED_QCFG": \
((x) == 0x2f ? "HWRM_PORT_LED_QCAPS": \
((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
((x) == 0x32 ? "HWRM_QUEUE_CFG": \
((x) == 0x33 ? "HWRM_FUNC_VLAN_CFG": \
((x) == 0x34 ? "HWRM_FUNC_VLAN_QCFG": \
((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
((x) == 0x3b ? "HWRM_QUEUE_DSCP_QCAPS": \
((x) == 0x3c ? "HWRM_QUEUE_DSCP2PRI_QCFG": \
((x) == 0x3d ? "HWRM_QUEUE_DSCP2PRI_CFG": \
((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
((x) == 0x41 ? "HWRM_VNIC_FREE": \
((x) == 0x42 ? "HWRM_VNIC_CFG": \
((x) == 0x43 ? "HWRM_VNIC_QCFG": \
((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
((x) == 0x4b ? "HWRM_VNIC_UPDATE": \
((x) == 0x50 ? "HWRM_RING_ALLOC": \
((x) == 0x51 ? "HWRM_RING_FREE": \
((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
((x) == 0x54 ? "HWRM_RING_AGGINT_QCAPS": \
((x) == 0x55 ? "HWRM_RING_SCHQ_ALLOC": \
((x) == 0x56 ? "HWRM_RING_SCHQ_CFG": \
((x) == 0x57 ? "HWRM_RING_SCHQ_FREE": \
((x) == 0x5e ? "HWRM_RING_RESET": \
((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
((x) == 0x62 ? "HWRM_RING_CFG": \
((x) == 0x63 ? "HWRM_RING_QCFG": \
((x) == 0x64 ? "HWRM_RESERVED5": \
((x) == 0x65 ? "HWRM_RESERVED6": \
((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
"Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x100) ? \
((x) == 0x80 ? "HWRM_QUEUE_MPLS_QCAPS": \
((x) == 0x81 ? "HWRM_QUEUE_MPLSTC2PRI_QCFG": \
((x) == 0x82 ? "HWRM_QUEUE_MPLSTC2PRI_CFG": \
((x) == 0x83 ? "HWRM_QUEUE_VLANPRI_QCAPS": \
((x) == 0x84 ? "HWRM_QUEUE_VLANPRI2PRI_QCFG": \
((x) == 0x85 ? "HWRM_QUEUE_VLANPRI2PRI_CFG": \
((x) == 0x86 ? "HWRM_QUEUE_GLOBAL_CFG": \
((x) == 0x87 ? "HWRM_QUEUE_GLOBAL_QCFG": \
+ ((x) == 0x88 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG": \
+ ((x) == 0x89 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG": \
+ ((x) == 0x8a ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG": \
+ ((x) == 0x8b ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG": \
+ ((x) == 0x8c ? "HWRM_QUEUE_QCAPS": \
+ ((x) == 0x8d ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG": \
+ ((x) == 0x8e ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG": \
+ ((x) == 0x8f ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG": \
((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
((x) == 0x94 ? "HWRM_CFA_VLAN_ANTISPOOF_CFG": \
((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
+ ((x) == 0xa3 ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG": \
((x) == 0xaf ? "HWRM_STAT_CTX_ENG_QUERY": \
((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
((x) == 0xb4 ? "HWRM_PORT_QSTATS_EXT": \
((x) == 0xb5 ? "HWRM_PORT_PHY_MDIO_WRITE": \
((x) == 0xb6 ? "HWRM_PORT_PHY_MDIO_READ": \
((x) == 0xb7 ? "HWRM_PORT_PHY_MDIO_BUS_ACQUIRE": \
((x) == 0xb8 ? "HWRM_PORT_PHY_MDIO_BUS_RELEASE": \
((x) == 0xb9 ? "HWRM_PORT_QSTATS_EXT_PFC_WD": \
((x) == 0xba ? "HWRM_RESERVED7": \
((x) == 0xbb ? "HWRM_PORT_TX_FIR_CFG": \
((x) == 0xbc ? "HWRM_PORT_TX_FIR_QCFG": \
((x) == 0xbd ? "HWRM_PORT_ECN_QSTATS": \
((x) == 0xbe ? "HWRM_FW_LIVEPATCH_QUERY": \
((x) == 0xbf ? "HWRM_FW_LIVEPATCH": \
((x) == 0xc0 ? "HWRM_FW_RESET": \
((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
((x) == 0xc2 ? "HWRM_FW_HEALTH_CHECK": \
((x) == 0xc3 ? "HWRM_FW_SYNC": \
((x) == 0xc4 ? "HWRM_FW_STATE_QCAPS": \
((x) == 0xc5 ? "HWRM_FW_STATE_QUIESCE": \
((x) == 0xc6 ? "HWRM_FW_STATE_BACKUP": \
((x) == 0xc7 ? "HWRM_FW_STATE_RESTORE": \
((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
((x) == 0xca ? "HWRM_FW_SET_STRUCTURED_DATA": \
((x) == 0xcb ? "HWRM_FW_GET_STRUCTURED_DATA": \
((x) == 0xcc ? "HWRM_FW_IPC_MAILBOX": \
((x) == 0xcd ? "HWRM_FW_ECN_CFG": \
((x) == 0xce ? "HWRM_FW_ECN_QCFG": \
((x) == 0xcf ? "HWRM_FW_SECURE_CFG": \
((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
((x) == 0xd2 ? "HWRM_FWD_RESP": \
((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
((x) == 0xd4 ? "HWRM_OEM_CMD": \
((x) == 0xd5 ? "HWRM_PORT_PRBS_TEST": \
((x) == 0xd6 ? "HWRM_PORT_SFP_SIDEBAND_CFG": \
((x) == 0xd7 ? "HWRM_PORT_SFP_SIDEBAND_QCFG": \
((x) == 0xd8 ? "HWRM_FW_STATE_UNQUIESCE": \
((x) == 0xd9 ? "HWRM_PORT_DSC_DUMP": \
((x) == 0xda ? "HWRM_PORT_EP_TX_QCFG": \
((x) == 0xdb ? "HWRM_PORT_EP_TX_CFG": \
((x) == 0xdc ? "HWRM_PORT_CFG": \
((x) == 0xdd ? "HWRM_PORT_QCFG": \
+ ((x) == 0xdf ? "HWRM_PORT_MAC_QCAPS": \
((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \
((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \
((x) == 0xe3 ? "HWRM_REG_POWER_HISTOGRAM": \
((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
((x) == 0xf4 ? "HWRM_CFA_METER_QCAPS": \
((x) == 0xf5 ? "HWRM_CFA_METER_PROFILE_ALLOC": \
((x) == 0xf6 ? "HWRM_CFA_METER_PROFILE_FREE": \
((x) == 0xf7 ? "HWRM_CFA_METER_PROFILE_CFG": \
((x) == 0xf8 ? "HWRM_CFA_METER_INSTANCE_ALLOC": \
((x) == 0xf9 ? "HWRM_CFA_METER_INSTANCE_FREE": \
((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \
((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \
((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \
- "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \
+ "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x180) ? \
((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \
((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \
((x) == 0x102 ? "HWRM_CFA_VF_PAIR_INFO": \
((x) == 0x103 ? "HWRM_CFA_FLOW_ALLOC": \
((x) == 0x104 ? "HWRM_CFA_FLOW_FREE": \
((x) == 0x105 ? "HWRM_CFA_FLOW_FLUSH": \
((x) == 0x106 ? "HWRM_CFA_FLOW_STATS": \
((x) == 0x107 ? "HWRM_CFA_FLOW_INFO": \
((x) == 0x108 ? "HWRM_CFA_DECAP_FILTER_ALLOC": \
((x) == 0x109 ? "HWRM_CFA_DECAP_FILTER_FREE": \
((x) == 0x10a ? "HWRM_CFA_VLAN_ANTISPOOF_QCFG": \
((x) == 0x10b ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC": \
((x) == 0x10c ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE": \
((x) == 0x10d ? "HWRM_CFA_PAIR_ALLOC": \
((x) == 0x10e ? "HWRM_CFA_PAIR_FREE": \
((x) == 0x10f ? "HWRM_CFA_PAIR_INFO": \
((x) == 0x110 ? "HWRM_FW_IPC_MSG": \
((x) == 0x111 ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO": \
((x) == 0x112 ? "HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE": \
((x) == 0x113 ? "HWRM_CFA_FLOW_AGING_TIMER_RESET": \
((x) == 0x114 ? "HWRM_CFA_FLOW_AGING_CFG": \
((x) == 0x115 ? "HWRM_CFA_FLOW_AGING_QCFG": \
((x) == 0x116 ? "HWRM_CFA_FLOW_AGING_QCAPS": \
((x) == 0x117 ? "HWRM_CFA_CTX_MEM_RGTR": \
((x) == 0x118 ? "HWRM_CFA_CTX_MEM_UNRGTR": \
((x) == 0x119 ? "HWRM_CFA_CTX_MEM_QCTX": \
((x) == 0x11a ? "HWRM_CFA_CTX_MEM_QCAPS": \
((x) == 0x11b ? "HWRM_CFA_COUNTER_QCAPS": \
((x) == 0x11c ? "HWRM_CFA_COUNTER_CFG": \
((x) == 0x11d ? "HWRM_CFA_COUNTER_QCFG": \
((x) == 0x11e ? "HWRM_CFA_COUNTER_QSTATS": \
((x) == 0x11f ? "HWRM_CFA_TCP_FLAG_PROCESS_QCFG": \
((x) == 0x120 ? "HWRM_CFA_EEM_QCAPS": \
((x) == 0x121 ? "HWRM_CFA_EEM_CFG": \
((x) == 0x122 ? "HWRM_CFA_EEM_QCFG": \
((x) == 0x123 ? "HWRM_CFA_EEM_OP": \
((x) == 0x124 ? "HWRM_CFA_ADV_FLOW_MGNT_QCAPS": \
((x) == 0x125 ? "HWRM_CFA_TFLIB": \
((x) == 0x126 ? "HWRM_CFA_LAG_GROUP_MEMBER_RGTR": \
((x) == 0x127 ? "HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR": \
((x) == 0x128 ? "HWRM_CFA_TLS_FILTER_ALLOC": \
((x) == 0x129 ? "HWRM_CFA_TLS_FILTER_FREE": \
+ ((x) == 0x12a ? "HWRM_CFA_RELEASE_AFM_FUNC": \
((x) == 0x12e ? "HWRM_ENGINE_CKV_STATUS": \
((x) == 0x12f ? "HWRM_ENGINE_CKV_CKEK_ADD": \
((x) == 0x130 ? "HWRM_ENGINE_CKV_CKEK_DELETE": \
((x) == 0x131 ? "HWRM_ENGINE_CKV_KEY_ADD": \
((x) == 0x132 ? "HWRM_ENGINE_CKV_KEY_DELETE": \
((x) == 0x133 ? "HWRM_ENGINE_CKV_FLUSH": \
((x) == 0x134 ? "HWRM_ENGINE_CKV_RNG_GET": \
((x) == 0x135 ? "HWRM_ENGINE_CKV_KEY_GEN": \
((x) == 0x136 ? "HWRM_ENGINE_CKV_KEY_LABEL_CFG": \
((x) == 0x137 ? "HWRM_ENGINE_CKV_KEY_LABEL_QCFG": \
((x) == 0x13c ? "HWRM_ENGINE_QG_CONFIG_QUERY": \
((x) == 0x13d ? "HWRM_ENGINE_QG_QUERY": \
((x) == 0x13e ? "HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY": \
((x) == 0x13f ? "HWRM_ENGINE_QG_METER_PROFILE_QUERY": \
((x) == 0x140 ? "HWRM_ENGINE_QG_METER_PROFILE_ALLOC": \
((x) == 0x141 ? "HWRM_ENGINE_QG_METER_PROFILE_FREE": \
((x) == 0x142 ? "HWRM_ENGINE_QG_METER_QUERY": \
((x) == 0x143 ? "HWRM_ENGINE_QG_METER_BIND": \
((x) == 0x144 ? "HWRM_ENGINE_QG_METER_UNBIND": \
((x) == 0x145 ? "HWRM_ENGINE_QG_FUNC_BIND": \
((x) == 0x146 ? "HWRM_ENGINE_SG_CONFIG_QUERY": \
((x) == 0x147 ? "HWRM_ENGINE_SG_QUERY": \
((x) == 0x148 ? "HWRM_ENGINE_SG_METER_QUERY": \
((x) == 0x149 ? "HWRM_ENGINE_SG_METER_CONFIG": \
((x) == 0x14a ? "HWRM_ENGINE_SG_QG_BIND": \
((x) == 0x14b ? "HWRM_ENGINE_QG_SG_UNBIND": \
((x) == 0x154 ? "HWRM_ENGINE_CONFIG_QUERY": \
((x) == 0x155 ? "HWRM_ENGINE_STATS_CONFIG": \
((x) == 0x156 ? "HWRM_ENGINE_STATS_CLEAR": \
((x) == 0x157 ? "HWRM_ENGINE_STATS_QUERY": \
((x) == 0x158 ? "HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR": \
((x) == 0x15e ? "HWRM_ENGINE_RQ_ALLOC": \
((x) == 0x15f ? "HWRM_ENGINE_RQ_FREE": \
((x) == 0x160 ? "HWRM_ENGINE_CQ_ALLOC": \
((x) == 0x161 ? "HWRM_ENGINE_CQ_FREE": \
((x) == 0x162 ? "HWRM_ENGINE_NQ_ALLOC": \
((x) == 0x163 ? "HWRM_ENGINE_NQ_FREE": \
((x) == 0x164 ? "HWRM_ENGINE_ON_DIE_RQE_CREDITS": \
((x) == 0x165 ? "HWRM_ENGINE_FUNC_QCFG": \
- "Unknown decode" ))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \
+ "Unknown decode" )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) : \
(((x) < 0x200) ? \
((x) == 0x190 ? "HWRM_FUNC_RESOURCE_QCAPS": \
((x) == 0x191 ? "HWRM_FUNC_VF_RESOURCE_CFG": \
((x) == 0x192 ? "HWRM_FUNC_BACKING_STORE_QCAPS": \
((x) == 0x193 ? "HWRM_FUNC_BACKING_STORE_CFG": \
((x) == 0x194 ? "HWRM_FUNC_BACKING_STORE_QCFG": \
((x) == 0x195 ? "HWRM_FUNC_VF_BW_CFG": \
((x) == 0x196 ? "HWRM_FUNC_VF_BW_QCFG": \
((x) == 0x197 ? "HWRM_FUNC_HOST_PF_IDS_QUERY": \
((x) == 0x198 ? "HWRM_FUNC_QSTATS_EXT": \
((x) == 0x199 ? "HWRM_STAT_EXT_CTX_QUERY": \
((x) == 0x19a ? "HWRM_FUNC_SPD_CFG": \
((x) == 0x19b ? "HWRM_FUNC_SPD_QCFG": \
((x) == 0x19c ? "HWRM_FUNC_PTP_PIN_QCFG": \
((x) == 0x19d ? "HWRM_FUNC_PTP_PIN_CFG": \
((x) == 0x19e ? "HWRM_FUNC_PTP_CFG": \
((x) == 0x19f ? "HWRM_FUNC_PTP_TS_QUERY": \
((x) == 0x1a0 ? "HWRM_FUNC_PTP_EXT_CFG": \
((x) == 0x1a1 ? "HWRM_FUNC_PTP_EXT_QCFG": \
((x) == 0x1a2 ? "HWRM_FUNC_KEY_CTX_ALLOC": \
((x) == 0x1a3 ? "HWRM_FUNC_BACKING_STORE_CFG_V2": \
((x) == 0x1a4 ? "HWRM_FUNC_BACKING_STORE_QCFG_V2": \
((x) == 0x1a5 ? "HWRM_FUNC_DBR_PACING_CFG": \
((x) == 0x1a6 ? "HWRM_FUNC_DBR_PACING_QCFG": \
((x) == 0x1a7 ? "HWRM_FUNC_DBR_PACING_BROADCAST_EVENT": \
((x) == 0x1a8 ? "HWRM_FUNC_BACKING_STORE_QCAPS_V2": \
((x) == 0x1a9 ? "HWRM_FUNC_DBR_PACING_NQLIST_QUERY": \
((x) == 0x1aa ? "HWRM_FUNC_DBR_RECOVERY_COMPLETED": \
((x) == 0x1ab ? "HWRM_FUNC_SYNCE_CFG": \
((x) == 0x1ac ? "HWRM_FUNC_SYNCE_QCFG": \
- "Unknown decode" ))))))))))))))))))))))))))))) : \
+ ((x) == 0x1ad ? "HWRM_FUNC_KEY_CTX_FREE": \
+ ((x) == 0x1ae ? "HWRM_FUNC_LAG_MODE_CFG": \
+ ((x) == 0x1af ? "HWRM_FUNC_LAG_MODE_QCFG": \
+ ((x) == 0x1b0 ? "HWRM_FUNC_LAG_CREATE": \
+ ((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \
+ ((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \
+ ((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \
+ "Unknown decode" )))))))))))))))))))))))))))))))))))) : \
(((x) < 0x280) ? \
((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \
((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \
((x) == 0x202 ? "HWRM_SELFTEST_IRQ": \
((x) == 0x203 ? "HWRM_SELFTEST_RETRIEVE_SERDES_DATA": \
((x) == 0x204 ? "HWRM_PCIE_QSTATS": \
((x) == 0x205 ? "HWRM_MFG_FRU_WRITE_CONTROL": \
((x) == 0x206 ? "HWRM_MFG_TIMERS_QUERY": \
((x) == 0x207 ? "HWRM_MFG_OTP_CFG": \
((x) == 0x208 ? "HWRM_MFG_OTP_QCFG": \
((x) == 0x209 ? "HWRM_MFG_HDMA_TEST": \
((x) == 0x20a ? "HWRM_MFG_FRU_EEPROM_WRITE": \
((x) == 0x20b ? "HWRM_MFG_FRU_EEPROM_READ": \
((x) == 0x20c ? "HWRM_MFG_SOC_IMAGE": \
((x) == 0x20d ? "HWRM_MFG_SOC_QSTATUS": \
- ((x) == 0x20e ? "HWRM_MFG_PARAM_SEEPROM_SYNC": \
- ((x) == 0x20f ? "HWRM_MFG_PARAM_SEEPROM_READ": \
- ((x) == 0x210 ? "HWRM_MFG_PARAM_SEEPROM_HEALTH": \
+ ((x) == 0x20e ? "HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE": \
+ ((x) == 0x20f ? "HWRM_MFG_PARAM_CRITICAL_DATA_READ": \
+ ((x) == 0x210 ? "HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH": \
((x) == 0x211 ? "HWRM_MFG_PRVSN_EXPORT_CSR": \
((x) == 0x212 ? "HWRM_MFG_PRVSN_IMPORT_CERT": \
((x) == 0x213 ? "HWRM_MFG_PRVSN_GET_STATE": \
((x) == 0x214 ? "HWRM_MFG_GET_NVM_MEASUREMENT": \
((x) == 0x215 ? "HWRM_MFG_PSOC_QSTATUS": \
((x) == 0x216 ? "HWRM_MFG_SELFTEST_QLIST": \
((x) == 0x217 ? "HWRM_MFG_SELFTEST_EXEC": \
((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \
- "Unknown decode" ))))))))))))))))))))))))) : \
+ ((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \
+ ((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \
+ ((x) == 0x258 ? "HWRM_UDCC_QCAPS": \
+ ((x) == 0x259 ? "HWRM_UDCC_CFG": \
+ ((x) == 0x25a ? "HWRM_UDCC_QCFG": \
+ ((x) == 0x25b ? "HWRM_UDCC_SESSION_CFG": \
+ ((x) == 0x25c ? "HWRM_UDCC_SESSION_QCFG": \
+ ((x) == 0x25d ? "HWRM_UDCC_SESSION_QUERY": \
+ ((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \
+ ((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \
+ ((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \
+ "Unknown decode" )))))))))))))))))))))))))))))))))))) : \
(((x) < 0x300) ? \
((x) == 0x2bc ? "HWRM_TF": \
((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \
((x) == 0x2c6 ? "HWRM_TF_SESSION_OPEN": \
- ((x) == 0x2c7 ? "HWRM_TF_SESSION_ATTACH": \
((x) == 0x2c8 ? "HWRM_TF_SESSION_REGISTER": \
((x) == 0x2c9 ? "HWRM_TF_SESSION_UNREGISTER": \
((x) == 0x2ca ? "HWRM_TF_SESSION_CLOSE": \
((x) == 0x2cb ? "HWRM_TF_SESSION_QCFG": \
((x) == 0x2cc ? "HWRM_TF_SESSION_RESC_QCAPS": \
((x) == 0x2cd ? "HWRM_TF_SESSION_RESC_ALLOC": \
((x) == 0x2ce ? "HWRM_TF_SESSION_RESC_FREE": \
((x) == 0x2cf ? "HWRM_TF_SESSION_RESC_FLUSH": \
((x) == 0x2d0 ? "HWRM_TF_SESSION_RESC_INFO": \
((x) == 0x2d1 ? "HWRM_TF_SESSION_HOTUP_STATE_SET": \
((x) == 0x2d2 ? "HWRM_TF_SESSION_HOTUP_STATE_GET": \
((x) == 0x2da ? "HWRM_TF_TBL_TYPE_GET": \
((x) == 0x2db ? "HWRM_TF_TBL_TYPE_SET": \
((x) == 0x2dc ? "HWRM_TF_TBL_TYPE_BULK_GET": \
- ((x) == 0x2e2 ? "HWRM_TF_CTXT_MEM_ALLOC": \
- ((x) == 0x2e3 ? "HWRM_TF_CTXT_MEM_FREE": \
- ((x) == 0x2e4 ? "HWRM_TF_CTXT_MEM_RGTR": \
- ((x) == 0x2e5 ? "HWRM_TF_CTXT_MEM_UNRGTR": \
- ((x) == 0x2e6 ? "HWRM_TF_EXT_EM_QCAPS": \
- ((x) == 0x2e7 ? "HWRM_TF_EXT_EM_OP": \
- ((x) == 0x2e8 ? "HWRM_TF_EXT_EM_CFG": \
- ((x) == 0x2e9 ? "HWRM_TF_EXT_EM_QCFG": \
((x) == 0x2ea ? "HWRM_TF_EM_INSERT": \
((x) == 0x2eb ? "HWRM_TF_EM_DELETE": \
((x) == 0x2ec ? "HWRM_TF_EM_HASH_INSERT": \
((x) == 0x2ed ? "HWRM_TF_EM_MOVE": \
((x) == 0x2f8 ? "HWRM_TF_TCAM_SET": \
((x) == 0x2f9 ? "HWRM_TF_TCAM_GET": \
((x) == 0x2fa ? "HWRM_TF_TCAM_MOVE": \
((x) == 0x2fb ? "HWRM_TF_TCAM_FREE": \
((x) == 0x2fc ? "HWRM_TF_GLOBAL_CFG_SET": \
((x) == 0x2fd ? "HWRM_TF_GLOBAL_CFG_GET": \
((x) == 0x2fe ? "HWRM_TF_IF_TBL_SET": \
((x) == 0x2ff ? "HWRM_TF_IF_TBL_GET": \
- "Unknown decode" )))))))))))))))))))))))))))))))))))))) : \
+ "Unknown decode" ))))))))))))))))))))))))))))) : \
+ (((x) < 0x380) ? \
+ ((x) == 0x300 ? "HWRM_TF_RESC_USAGE_SET": \
+ ((x) == 0x301 ? "HWRM_TF_RESC_USAGE_QUERY": \
+ ((x) == 0x302 ? "HWRM_TF_TBL_TYPE_ALLOC": \
+ ((x) == 0x303 ? "HWRM_TF_TBL_TYPE_FREE": \
+ "Unknown decode" )))) : \
(((x) < 0x400) ? \
((x) == 0x380 ? "HWRM_TFC_TBL_SCOPE_QCAPS": \
((x) == 0x381 ? "HWRM_TFC_TBL_SCOPE_ID_ALLOC": \
((x) == 0x382 ? "HWRM_TFC_TBL_SCOPE_CONFIG": \
((x) == 0x383 ? "HWRM_TFC_TBL_SCOPE_DECONFIG": \
((x) == 0x384 ? "HWRM_TFC_TBL_SCOPE_FID_ADD": \
((x) == 0x385 ? "HWRM_TFC_TBL_SCOPE_FID_REM": \
((x) == 0x386 ? "HWRM_TFC_TBL_SCOPE_POOL_ALLOC": \
((x) == 0x387 ? "HWRM_TFC_TBL_SCOPE_POOL_FREE": \
((x) == 0x388 ? "HWRM_TFC_SESSION_ID_ALLOC": \
((x) == 0x389 ? "HWRM_TFC_SESSION_FID_ADD": \
((x) == 0x38a ? "HWRM_TFC_SESSION_FID_REM": \
((x) == 0x38b ? "HWRM_TFC_IDENT_ALLOC": \
((x) == 0x38c ? "HWRM_TFC_IDENT_FREE": \
((x) == 0x38d ? "HWRM_TFC_IDX_TBL_ALLOC": \
((x) == 0x38e ? "HWRM_TFC_IDX_TBL_ALLOC_SET": \
((x) == 0x38f ? "HWRM_TFC_IDX_TBL_SET": \
((x) == 0x390 ? "HWRM_TFC_IDX_TBL_GET": \
((x) == 0x391 ? "HWRM_TFC_IDX_TBL_FREE": \
((x) == 0x392 ? "HWRM_TFC_GLOBAL_ID_ALLOC": \
((x) == 0x393 ? "HWRM_TFC_TCAM_SET": \
((x) == 0x394 ? "HWRM_TFC_TCAM_GET": \
((x) == 0x395 ? "HWRM_TFC_TCAM_ALLOC": \
((x) == 0x396 ? "HWRM_TFC_TCAM_ALLOC_SET": \
((x) == 0x397 ? "HWRM_TFC_TCAM_FREE": \
- "Unknown decode" )))))))))))))))))))))))) : \
+ ((x) == 0x398 ? "HWRM_TFC_IF_TBL_SET": \
+ ((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \
+ ((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \
+ ((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \
+ ((x) == 0x39c ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \
+ ((x) == 0x39d ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \
+ ((x) == 0x39e ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \
+ "Unknown decode" ))))))))))))))))))))))))))))))) : \
(((x) < 0x480) ? \
((x) == 0x400 ? "HWRM_SV": \
"Unknown decode" ) : \
(((x) < 0xff80) ? \
+ ((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \
((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
((x) == 0xff14 ? "HWRM_DBG_DUMP": \
((x) == 0xff15 ? "HWRM_DBG_ERASE_NVM": \
((x) == 0xff16 ? "HWRM_DBG_CFG": \
((x) == 0xff17 ? "HWRM_DBG_COREDUMP_LIST": \
((x) == 0xff18 ? "HWRM_DBG_COREDUMP_INITIATE": \
((x) == 0xff19 ? "HWRM_DBG_COREDUMP_RETRIEVE": \
((x) == 0xff1a ? "HWRM_DBG_FW_CLI": \
((x) == 0xff1b ? "HWRM_DBG_I2C_CMD": \
((x) == 0xff1c ? "HWRM_DBG_RING_INFO_GET": \
((x) == 0xff1d ? "HWRM_DBG_CRASHDUMP_HEADER": \
((x) == 0xff1e ? "HWRM_DBG_CRASHDUMP_ERASE": \
((x) == 0xff1f ? "HWRM_DBG_DRV_TRACE": \
((x) == 0xff20 ? "HWRM_DBG_QCAPS": \
((x) == 0xff21 ? "HWRM_DBG_QCFG": \
((x) == 0xff22 ? "HWRM_DBG_CRASHDUMP_MEDIUM_CFG": \
((x) == 0xff23 ? "HWRM_DBG_USEQ_ALLOC": \
((x) == 0xff24 ? "HWRM_DBG_USEQ_FREE": \
((x) == 0xff25 ? "HWRM_DBG_USEQ_FLUSH": \
((x) == 0xff26 ? "HWRM_DBG_USEQ_QCAPS": \
((x) == 0xff27 ? "HWRM_DBG_USEQ_CW_CFG": \
((x) == 0xff28 ? "HWRM_DBG_USEQ_SCHED_CFG": \
((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \
((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \
((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \
- "Unknown decode" )))))))))))))))))))))))))))) : \
+ "Unknown decode" ))))))))))))))))))))))))))))) : \
(((x) <= 0xffff) ? \
+ ((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \
+ ((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \
((x) == 0xffec ? "HWRM_NVM_DEFRAG": \
((x) == 0xffed ? "HWRM_NVM_REQ_ARBITRATION": \
((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \
((x) == 0xffef ? "HWRM_NVM_VALIDATE_OPTION": \
((x) == 0xfff0 ? "HWRM_NVM_FLUSH": \
((x) == 0xfff1 ? "HWRM_NVM_GET_VARIABLE": \
((x) == 0xfff2 ? "HWRM_NVM_SET_VARIABLE": \
((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
((x) == 0xfffd ? "HWRM_NVM_READ": \
((x) == 0xfffe ? "HWRM_NVM_WRITE": \
((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
- "Unknown decode" )))))))))))))))))))) : \
- "Unknown decode" ))))))))))
+ "Unknown decode" )))))))))))))))))))))) : \
+ "Unknown decode" )))))))))))
/*
* Command numbering
* # NOTE - definitions already in hwrm_req_type, in hwrm_types.yaml
* # So only structure definition is provided here.
*/
/* cmd_nums (size:64b/8B) */
typedef struct cmd_nums {
/*
* This version of the specification defines the commands listed in
* the table below. The following are general implementation
* requirements for these commands:
*
* # All commands listed below that are marked neither
* reserved nor experimental shall be implemented by the HWRM.
* # A HWRM client compliant to this specification should not use
* commands outside of the list below.
* # A HWRM client compliant to this specification should not use
* command numbers marked reserved below.
* # A command marked experimental below may not be implemented
* by the HWRM.
* # A command marked experimental may change in the
* future version of the HWRM specification.
* # A command not listed below may be implemented by the HWRM.
* The behavior of commands that are not listed below is outside
* the scope of this specification.
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
#define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
#define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
/* Reserved for future use. */
#define HWRM_RESERVED1 UINT32_C(0x10)
#define HWRM_FUNC_RESET UINT32_C(0x11)
#define HWRM_FUNC_GETFID UINT32_C(0x12)
#define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
#define HWRM_FUNC_VF_FREE UINT32_C(0x14)
#define HWRM_FUNC_QCAPS UINT32_C(0x15)
#define HWRM_FUNC_QCFG UINT32_C(0x16)
#define HWRM_FUNC_CFG UINT32_C(0x17)
#define HWRM_FUNC_QSTATS UINT32_C(0x18)
#define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
#define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
#define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
#define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
#define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
#define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
#define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
#define HWRM_PORT_PHY_CFG UINT32_C(0x20)
#define HWRM_PORT_MAC_CFG UINT32_C(0x21)
/* Experimental */
#define HWRM_PORT_TS_QUERY UINT32_C(0x22)
#define HWRM_PORT_QSTATS UINT32_C(0x23)
#define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
/* Experimental */
#define HWRM_PORT_CLR_STATS UINT32_C(0x25)
/* Experimental */
#define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
#define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
#define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
/* Experimental */
#define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
#define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
#define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
#define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
#define HWRM_PORT_LED_CFG UINT32_C(0x2d)
#define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
#define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
#define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
#define HWRM_QUEUE_QCFG UINT32_C(0x31)
#define HWRM_QUEUE_CFG UINT32_C(0x32)
#define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
#define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
#define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
#define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
- #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
+ #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
#define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
#define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
#define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
#define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
#define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
#define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
#define HWRM_VNIC_ALLOC UINT32_C(0x40)
#define HWRM_VNIC_FREE UINT32_C(0x41)
#define HWRM_VNIC_CFG UINT32_C(0x42)
#define HWRM_VNIC_QCFG UINT32_C(0x43)
#define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
/* Experimental */
#define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
#define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
#define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
#define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
#define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
#define HWRM_VNIC_QCAPS UINT32_C(0x4a)
/* Updates specific fields in RX VNIC structure */
#define HWRM_VNIC_UPDATE UINT32_C(0x4b)
#define HWRM_RING_ALLOC UINT32_C(0x50)
#define HWRM_RING_FREE UINT32_C(0x51)
#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
#define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
#define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
#define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
#define HWRM_RING_RESET UINT32_C(0x5e)
#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
#define HWRM_RING_GRP_FREE UINT32_C(0x61)
#define HWRM_RING_CFG UINT32_C(0x62)
#define HWRM_RING_QCFG UINT32_C(0x63)
/* Reserved for future use. */
#define HWRM_RESERVED5 UINT32_C(0x64)
/* Reserved for future use. */
#define HWRM_RESERVED6 UINT32_C(0x65)
#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
#define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
#define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
#define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
#define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
#define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
#define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
#define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
#define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
#define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
+ #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88)
+ #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89)
+ #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a)
+ #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b)
+ #define HWRM_QUEUE_QCAPS UINT32_C(0x8c)
+ #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d)
+ #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e)
+ #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f)
#define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
#define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
#define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
#define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
#define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
#define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
#define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
/* Experimental */
#define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
/* Experimental */
#define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
#define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
#define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
#define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
/* Experimental */
#define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
/* Experimental */
#define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
/* Experimental */
#define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3)
#define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
#define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
#define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
#define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
#define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
/* Reserved. */
#define HWRM_RESERVED7 UINT32_C(0xba)
#define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
#define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
#define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
#define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
#define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
#define HWRM_FW_SYNC UINT32_C(0xc3)
#define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
#define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
#define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
#define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
/* Experimental */
#define HWRM_FW_SET_TIME UINT32_C(0xc8)
/* Experimental */
#define HWRM_FW_GET_TIME UINT32_C(0xc9)
/* Experimental */
#define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
/* Experimental */
#define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
/* Experimental */
#define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
#define HWRM_FW_ECN_CFG UINT32_C(0xcd)
#define HWRM_FW_ECN_QCFG UINT32_C(0xce)
#define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
#define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
#define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
/* Tells the fw to run PRBS test on a given port and lane. */
#define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
#define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
#define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
/* Tells the fw to collect dsc dump on a given port and lane. */
#define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
#define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
#define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
#define HWRM_PORT_CFG UINT32_C(0xdc)
#define HWRM_PORT_QCFG UINT32_C(0xdd)
+ /* Queries MAC capabilities for the specified port */
+ #define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
#define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
#define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
#define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
/* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
/* Experimental */
#define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
/* Experimental */
#define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
/* Experimental */
#define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
/* Experimental */
#define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
/* Experimental */
#define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
/* Experimental */
#define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
#define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
#define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
/* Experimental */
#define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
/* Experimental */
#define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
#define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
/* Experimental */
#define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
/* Experimental */
#define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
/* Experimental */
#define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
/* Experimental */
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Experimental */
#define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
/* Experimental */
#define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
/* Experimental */
#define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
/* Experimental */
#define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
/* Experimental */
#define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
/* Experimental */
#define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
/* Experimental */
#define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
/* Experimental */
#define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
/* Experimental */
#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
/* Experimental */
#define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
/* Experimental */
#define HWRM_CFA_EEM_CFG UINT32_C(0x121)
/* Experimental */
#define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
/* Experimental */
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Experimental - DEPRECATED */
#define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Experimental */
#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
/* Experimental */
#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
/* Experimental */
#define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128)
/* Experimental */
#define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129)
- /* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
+ /* Release an AFM function for TF control */
+ #define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a)
+ /*
+ * Engine CKV - Get the current allocation status of keys provisioned in
+ * the key vault.
+ */
#define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
/* Engine CKV - Add a new CKEK used to encrypt keys. */
#define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
/* Engine CKV - Delete a previously added CKEK. */
#define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
/* Engine CKV - Add a new key to the key vault. */
#define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
/* Engine CKV - Delete a key from the key vault. */
#define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
/* Engine CKV - Delete all keys from the key vault. */
#define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
/* Engine CKV - Get random data. */
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine CKV - Query a label */
#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
#define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
/* Engine - Query the available queue group meter profile configuration. */
#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
/* Engine - Query the configuration of a queue group meter profile. */
#define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
/* Engine - Allocate a queue group meter profile. */
#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
/* Engine - Free a queue group meter profile. */
#define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
/* Engine - Query the meters assigned to a queue group. */
#define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
/* Engine - Bind a queue group meter profile to a queue group. */
#define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
/* Engine - Unbind a queue group meter profile from a queue group. */
#define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
/* Engine - Bind a queue group to a function. */
#define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
/* Engine - Query the scheduling group configuration. */
#define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
/* Engine - Query the queue groups assigned to a scheduling group. */
#define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
/* Engine - Query the configuration of a scheduling group's meter profiles. */
#define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
/* Engine - Configure a scheduling group's meter profiles. */
#define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
/* Engine - Bind a queue group to a scheduling group. */
#define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
/* Engine - Unbind a queue group from its scheduling group. */
#define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
/* Engine - Query the Engine configuration. */
#define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
/* Engine - Configure the statistics accumulator for an Engine. */
#define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
/* Engine - Clear the statistics accumulator for an Engine. */
#define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
/* Engine - Query the statistics accumulator for an Engine. */
#define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
- /* Engine - Query statistics counters for continuous errors from all CDDIP Engines. */
+ /*
+ * Engine - Query statistics counters for continuous errors from all CDDIP
+ * Engines.
+ */
#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
/* Engine - Allocate an Engine RQ. */
#define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
/* Engine - Free an Engine RQ. */
#define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
/* Engine - Allocate an Engine CQ. */
#define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
/* Engine - Free an Engine CQ. */
#define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
/* Engine - Allocate an NQ. */
#define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
/* Engine - Free an NQ. */
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
/* Engine - Query the engine function configuration. */
#define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
#define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
/* Experimental */
#define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
/* Experimental */
#define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
/* Experimental */
#define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
/* Configures the BW of any VF */
#define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
/* Queries the BW of any VF */
#define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
/* Queries pf ids belong to specified host(s) */
#define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
/* Queries extended stats per function */
#define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
/* Queries extended statistics context */
#define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
/* Configure SoC packet DMA settings */
#define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
/* Query SoC packet DMA settings */
#define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
/* PTP - Queries configuration of timesync IO pins. */
#define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
/* PTP - Configuration of timesync IO pins. */
#define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
/* PTP - Configuration for disciplining PHC. */
#define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
/* PTP - Queries for PHC timestamps. */
#define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
/* PTP - Extended PTP configuration. */
#define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
/* PTP - Query extended PTP configuration. */
#define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
/* The command is used to allocate KTLS or QUIC key contexts. */
#define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
/* The is the new API to configure backing stores. */
#define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
/* The is the new API to query backing store configurations. */
#define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
/* To support doorbell pacing configuration. */
#define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5)
/* To query doorbell pacing configuration. */
#define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6)
/*
* To broadcast the doorbell event to the drivers to
* initiate pacing of doorbells.
*/
#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
/* The is the new API to query backing store capabilities. */
#define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
/* To query doorbell pacing NQ id list configuration. */
#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)
/*
* To notify the firmware that recovery cycle has been
* completed by host function drivers.
*/
#define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)
/* Configures SyncE configurations. */
#define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)
/* Queries SyncE configurations. */
#define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)
+ /* The command is used to deallocate KTLS or QUIC key contexts. */
+ #define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad)
+ /* The command is used to configure link aggr group mode. */
+ #define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae)
+ /* The command is used to query link aggr group mode. */
+ #define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af)
+ /* The command is used to create a link aggr group. */
+ #define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0)
+ /* The command is used to update a link aggr group. */
+ #define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1)
+ /* The command is used to free a link aggr group. */
+ #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2)
+ /* The command is used to query a link aggr group. */
+ #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3)
/* Experimental */
#define HWRM_SELFTEST_QLIST UINT32_C(0x200)
/* Experimental */
#define HWRM_SELFTEST_EXEC UINT32_C(0x201)
/* Experimental */
#define HWRM_SELFTEST_IRQ UINT32_C(0x202)
/* Experimental */
#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
#define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
/* Returns the current value of a free running counter from the device. */
#define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
/* Experimental */
#define HWRM_MFG_OTP_CFG UINT32_C(0x207)
/* Experimental */
#define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
/*
* Tells the fw to run the DMA read from the host and DMA write
* to the host test.
*/
#define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
/* Tells the fw to program the fru memory */
#define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
/* Tells the fw to read the fru memory */
#define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
/* Used to provision SoC software images */
#define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
/* Retrieves the SoC status and image provisioning information */
#define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
- /* Tells the fw to program the seeprom memory */
- #define HWRM_MFG_PARAM_SEEPROM_SYNC UINT32_C(0x20e)
- /* Tells the fw to read the seeprom memory */
- #define HWRM_MFG_PARAM_SEEPROM_READ UINT32_C(0x20f)
- /* Tells the fw to get the health of seeprom data */
- #define HWRM_MFG_PARAM_SEEPROM_HEALTH UINT32_C(0x210)
+ /* Tells the fw to finalize the critical data (store and lock it) */
+ #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e)
+ /* Tells the fw to read the critical data */
+ #define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f)
+ /* Tells the fw to get the health of critical data */
+ #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210)
/*
* The command is used for certificate provisioning to export a
* Certificate Signing Request (CSR) from the device.
*/
#define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
/*
* The command is used for certificate provisioning to import a
* CA-signed certificate chain to the device.
*/
#define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
/*
* The command is used for certificate provisioning to query the
* provisioned state.
*/
#define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
/*
* The command is used to get the hash of the NVM configuration that is
* calculated during firmware boot.
*/
#define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
/* Retrieves the PSOC status and provisioning information. */
#define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
/*
* This command allows manufacturing tool to determine which selftests
* are available to be run.
*/
#define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
/*
* This command allows manufacturing tool to request which selftests
* to run.
*/
#define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
/* Queries the generic stats */
#define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)
+ /*
+ * The command is used for certificate provisioning to export a
+ * certificate chain from the device.
+ */
+ #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219)
+ /* Query the statistics for doorbell drops due to various error conditions. */
+ #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a)
+ /*
+ * This command returns the capabilities related to User Defined
+ * Congestion Control on a function.
+ */
+ #define HWRM_UDCC_QCAPS UINT32_C(0x258)
+ /* This command configures User Defined Congestion Control on a function. */
+ #define HWRM_UDCC_CFG UINT32_C(0x259)
+ /*
+ * This command queries the configuration of User Defined Congestion
+ * Control on a function.
+ */
+ #define HWRM_UDCC_QCFG UINT32_C(0x25a)
+ /* This command configures an existing UDCC session. */
+ #define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b)
+ /* This command queries the configuration of a UDCC session. */
+ #define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c)
+ /* This command queries the UDCC session. */
+ #define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d)
+ /* This command configures the computation unit. */
+ #define HWRM_UDCC_COMP_CFG UINT32_C(0x25e)
+ /* This command queries the configuration of the computation unit. */
+ #define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f)
+ /* This command queries the status and statistics of the computation unit. */
+ #define HWRM_UDCC_COMP_QUERY UINT32_C(0x260)
/* Experimental */
#define HWRM_TF UINT32_C(0x2bc)
/* Experimental */
#define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
/* Experimental */
#define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
/* Experimental */
- #define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)
- /* Experimental */
#define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
/* Experimental */
#define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
/* Experimental */
#define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
/* Experimental */
#define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
/* Experimental */
#define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
/* Experimental */
#define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
/* Experimental */
#define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
/* Experimental */
#define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
/* Experimental */
#define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
/* Experimental */
#define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)
/* Experimental */
#define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)
/* Experimental */
#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
/* Experimental */
#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
/* Experimental */
#define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
/* Experimental */
- #define HWRM_TF_CTXT_MEM_ALLOC UINT32_C(0x2e2)
- /* Experimental */
- #define HWRM_TF_CTXT_MEM_FREE UINT32_C(0x2e3)
- /* Experimental */
- #define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)
- /* Experimental */
- #define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)
- /* Experimental */
- #define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)
- /* Experimental */
- #define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)
- /* Experimental */
- #define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)
- /* Experimental */
- #define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)
- /* Experimental */
#define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
/* Experimental */
#define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
/* Experimental */
#define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
/* Experimental */
#define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
/* Experimental */
#define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
/* Experimental */
#define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
/* Experimental */
#define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
/* Experimental */
#define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
/* Experimental */
#define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
/* Experimental */
#define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
/* Experimental */
#define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
/* Experimental */
#define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
+ /* Experimental */
+ #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300)
+ /* Experimental */
+ #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301)
+ /* Truflow command to allocate a table */
+ #define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302)
+ /* Truflow command to free a table */
+ #define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303)
/* TruFlow command to check firmware table scope capabilities. */
#define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)
/* TruFlow command to allocate a table scope ID and create the pools. */
#define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)
/* TruFlow command to configure the table scope memory. */
#define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)
/* TruFlow command to deconfigure a table scope memory. */
#define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)
/* TruFlow command to add a FID to a table scope. */
#define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)
/* TruFlow command to remove a FID from a table scope. */
#define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)
- /* TruFlow command to allocate a table scope pool. */
+ /* DEPRECATED */
#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)
- /* TruFlow command to free a table scope pool. */
+ /* DEPRECATED */
#define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)
/* Experimental */
#define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)
/* Experimental */
#define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)
/* Experimental */
#define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)
/* Experimental */
#define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)
/* Experimental */
#define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)
/* TruFlow command to allocate an index table entry */
#define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)
/* TruFlow command to allocate and set an index table entry */
#define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)
/* TruFlow command to set an index table entry */
#define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)
/* TruFlow command to get an index table entry */
#define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)
/* TruFlow command to free an index table entry */
#define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)
/* TruFlow command to allocate resources for a global id. */
#define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)
/* TruFlow command to set TCAM entry. */
#define HWRM_TFC_TCAM_SET UINT32_C(0x393)
/* TruFlow command to get TCAM entry. */
#define HWRM_TFC_TCAM_GET UINT32_C(0x394)
/* TruFlow command to allocate a TCAM entry. */
#define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)
/* TruFlow command allocate and set TCAM entry. */
#define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)
/* TruFlow command to free a TCAM entry. */
#define HWRM_TFC_TCAM_FREE UINT32_C(0x397)
+ /* Truflow command to set an interface table entry */
+ #define HWRM_TFC_IF_TBL_SET UINT32_C(0x398)
+ /* Truflow command to get an interface table entry */
+ #define HWRM_TFC_IF_TBL_GET UINT32_C(0x399)
+ /* TruFlow command to get configured info about a table scope. */
+ #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a)
+ /* TruFlow command to query the resource usage state. */
+ #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b)
+ /*
+ * This command is used to query the pfc watchdog max configurable
+ * timeout value.
+ */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c)
+ /* This command is used to set the PFC watchdog timeout value. */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d)
+ /*
+ * This command is used to query the current configured pfc watchdog
+ * timeout value.
+ */
+ #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e)
/* Experimental */
#define HWRM_SV UINT32_C(0x400)
+ /* Flush any trace buffer data that has not been sent to the host. */
+ #define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f)
/* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
/* Experimental */
#define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
/* Experimental */
#define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
#define HWRM_DBG_DUMP UINT32_C(0xff14)
/* Experimental */
#define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
/* Experimental */
#define HWRM_DBG_CFG UINT32_C(0xff16)
/* Experimental */
#define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
/* Experimental */
#define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
/* Experimental */
#define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
/* Experimental */
#define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
/* */
#define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
#define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
/* Experimental */
#define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
/* Send driver debug information to firmware */
#define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
/* Query debug capabilities of firmware */
#define HWRM_DBG_QCAPS UINT32_C(0xff20)
/* Retrieve debug settings of firmware */
#define HWRM_DBG_QCFG UINT32_C(0xff21)
/* Set destination parameters for crashdump medium */
#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
/* Experimental */
#define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
/* Experimental */
#define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
/* Experimental */
#define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
/* Experimental */
#define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
/* Experimental */
#define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
/* Experimental */
#define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
/* Experimental */
#define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
/* Experimental */
#define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
/* Experimental */
#define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
+ #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea)
+ #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb)
#define HWRM_NVM_DEFRAG UINT32_C(0xffec)
#define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
/* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
#define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
#define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
#define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
#define HWRM_NVM_MODIFY UINT32_C(0xfff4)
#define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
#define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
#define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
#define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
#define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
#define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
#define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
#define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
#define HWRM_NVM_READ UINT32_C(0xfffd)
#define HWRM_NVM_WRITE UINT32_C(0xfffe)
#define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
#define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK
uint16_t unused_0[3];
} cmd_nums_t, *pcmd_nums_t;
/* Return Codes */
/* ret_codes (size:64b/8B) */
typedef struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
#define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
#define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
#define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
#define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
#define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
#define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
#define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
#define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
#define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* This error code is only reported by the firmware when during
* flow allocation when a request for a flow counter fails because
* the number of flow counters are exhausted.
*/
#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
/*
* This error code is only reported by firmware when the registered
- * driver instances requested to offloaded a flow but was unable to because
- * the requested key's hash collides with the installed keys.
+ * driver instances requested to offloaded a flow but was unable to
+ * because the requested key's hash collides with the installed keys.
*/
#define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
/*
* This error code is only reported by firmware when the registered
- * driver instances requested to offloaded a flow but was unable to because
- * the same key has already been installed.
+ * driver instances requested to offloaded a flow but was unable to
+ * because the same key has already been installed.
*/
#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
#define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
- * Firmware is unable to service the request at the present time. Caller
- * may try again later.
+ * Firmware is unable to service the request at the present time.
+ * Caller may try again later.
*/
#define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
/*
* This error code is reported by Firmware when an operation requested
* by the host is not allowed due to a secure lock violation.
*/
#define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
/*
* This error code is reported by Firmware when an operation requested
* by a VF cannot be forwarded to the parent PF as required, either
* because the PF is down or otherwise doesn't have an appropriate
* async completion ring or associated forwarding buffers configured.
*/
#define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
+ /*
+ * This error code is reported by Firmware when the specific entity
+ * requested by the host is not present or does not exist.
+ */
+ #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
* hwrm_resp_hdr TLV. This value is not an indication of any error
* by itself, just an indication that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
#define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
} ret_codes_t, *pret_codes_t;
#define GET_HWRM_ERROR_CODE(x) \
(((x) < 0x80) ? \
((x) == 0x0 ? "SUCCESS": \
((x) == 0x1 ? "FAIL": \
((x) == 0x2 ? "INVALID_PARAMS": \
((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
((x) == 0x5 ? "INVALID_FLAGS": \
((x) == 0x6 ? "INVALID_ENABLES": \
((x) == 0x7 ? "UNSUPPORTED_TLV": \
((x) == 0x8 ? "NO_BUFFER": \
((x) == 0x9 ? "UNSUPPORTED_OPTION_ERR": \
((x) == 0xa ? "HOT_RESET_PROGRESS": \
((x) == 0xb ? "HOT_RESET_FAIL": \
((x) == 0xc ? "NO_FLOW_COUNTER_DURING_ALLOC": \
((x) == 0xd ? "KEY_HASH_COLLISION": \
((x) == 0xe ? "KEY_ALREADY_EXISTS": \
((x) == 0xf ? "HWRM_ERROR": \
((x) == 0x10 ? "BUSY": \
((x) == 0x11 ? "RESOURCE_LOCKED": \
((x) == 0x12 ? "PF_UNAVAILABLE": \
- "Unknown decode" ))))))))))))))))))) : \
+ ((x) == 0x13 ? "ENTITY_NOT_PRESENT": \
+ "Unknown decode" )))))))))))))))))))) : \
(((x) < 0x8080) ? \
((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \
"Unknown decode" ) : \
(((x) <= 0xffff) ? \
((x) == 0xfffe ? "UNKNOWN_ERR": \
((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
"Unknown decode" )) : \
"Unknown decode" )))
/* Output */
/* hwrm_err_output (size:128b/16B) */
typedef struct hwrm_err_output {
/*
* Pass/Fail or error type
*
* Note: receiver to verify the in parameters, and fail the call
* with an error when appropriate
*/
uint16_t error_code;
/* This field returns the type of original request. */
uint16_t req_type;
/* This field provides original sequence number of the command. */
uint16_t seq_id;
/*
- * This field is the length of the response in bytes. The
+ * This field is the length of the response in bytes. The
* last byte of the response is a valid flag that will read
* as '1' when the command has been completely written to
* memory.
*/
uint16_t resp_len;
/* debug info for this error response. */
uint32_t opaque_0;
/* debug info for this error response. */
uint16_t opaque_1;
/*
* In the case of an error response, command specific error
* code is returned in this field.
*/
uint8_t cmd_err;
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
} hwrm_err_output_t, *phwrm_err_output_t;
/*
* Following is the signature for HWRM message field that indicates not
* applicable (All F's). Need to cast it the size of the field if needed.
*/
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
-/* hwrm_func_buf_rgtr */
+/*
+ * This is reflecting the size of the PF mailbox and not the maximum
+ * command size for any of the HWRM command structures. To determine
+ * the maximum size of an HWRM command supported by the firmware, see
+ * the max_ext_req_len field in the response of the HWRM_VER_GET command.
+ */
#define HWRM_MAX_REQ_LEN 128
/* hwrm_cfa_flow_info */
#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
/* Reserved for BONO processor */
#define HWRM_TARGET_ID_BONO 0xFFF8
/* Reserved for KONG processor */
#define HWRM_TARGET_ID_KONG 0xFFF9
/* Reserved for APE processor */
#define HWRM_TARGET_ID_APE 0xFFFA
/*
* This value will be used by tools for User-space HWRM Interface.
* When tool execute any HWRM command with this target_id, firmware
* will copy the response and/or data payload via register space instead
* of DMAing it.
*/
#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_UPDATE 3
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 136
-#define HWRM_VERSION_STR "1.10.2.136"
+#define HWRM_VERSION_RSVD 42
+#define HWRM_VERSION_STR "1.10.3.42"
/****************
* hwrm_ver_get *
****************/
/* hwrm_ver_get_input (size:192b/24B) */
typedef struct hwrm_ver_get_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
* The completion ring to send the completion event on. This should
* be the NQ ID returned from the `nq_alloc` HWRM command.
*/
uint16_t cmpl_ring;
/*
* The sequence ID is used by the driver for tracking multiple
* commands. This ID is treated as opaque data by the firmware and
* the value is returned in the `hwrm_resp_hdr` upon completion.
*/
uint16_t seq_id;
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
* * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
* * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
/*
* A physical address pointer pointing to a host buffer that the
* command's response data will be written. This can be either a host
* physical address (HPA) or a guest physical address (GPA) and must
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
/*
* This field represents the major version of HWRM interface
* specification supported by the driver HWRM implementation.
* The interface major version is intended to change only when
* non backward compatible changes are made to the HWRM
* interface specification.
*/
uint8_t hwrm_intf_maj;
/*
* This field represents the minor version of HWRM interface
* specification supported by the driver HWRM implementation.
* A change in interface minor version is used to reflect
* significant backward compatible modification to HWRM
* interface specification.
* This can be due to addition or removal of functionality.
* HWRM interface specifications with the same major version
* but different minor versions are compatible.
*/
uint8_t hwrm_intf_min;
/*
* This field represents the update version of HWRM interface
* specification supported by the driver HWRM implementation.
* The interface update version is used to reflect minor
* changes or bug fixes to a released HWRM interface
* specification.
*/
uint8_t hwrm_intf_upd;
uint8_t unused_0[5];
} hwrm_ver_get_input_t, *phwrm_ver_get_input_t;
/* hwrm_ver_get_output (size:1408b/176B) */
typedef struct hwrm_ver_get_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
uint16_t req_type;
/* The sequence ID from the original command. */
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
/*
* This field represents the major version of HWRM interface
* specification supported by the HWRM implementation.
* The interface major version is intended to change only when
* non backward compatible changes are made to the HWRM
* interface specification.
* A HWRM implementation that is compliant with this
* specification shall provide value of 1 in this field.
*/
uint8_t hwrm_intf_maj_8b;
/*
* This field represents the minor version of HWRM interface
* specification supported by the HWRM implementation.
* A change in interface minor version is used to reflect
* significant backward compatible modification to HWRM
* interface specification.
* This can be due to addition or removal of functionality.
* HWRM interface specifications with the same major version
* but different minor versions are compatible.
* A HWRM implementation that is compliant with this
* specification shall provide value of 2 in this field.
*/
uint8_t hwrm_intf_min_8b;
/*
* This field represents the update version of HWRM interface
* specification supported by the HWRM implementation.
* The interface update version is used to reflect minor
* changes or bug fixes to a released HWRM interface
* specification.
* A HWRM implementation that is compliant with this
* specification shall provide value of 2 in this field.
*/
uint8_t hwrm_intf_upd_8b;
uint8_t hwrm_intf_rsvd_8b;
/*
* This field represents the major version of HWRM firmware.
* A change in firmware major version represents a major
* firmware release.
*/
uint8_t hwrm_fw_maj_8b;
/*
* This field represents the minor version of HWRM firmware.
* A change in firmware minor version represents significant
* firmware functionality changes.
*/
uint8_t hwrm_fw_min_8b;
/*
* This field represents the build version of HWRM firmware.
* A change in firmware build version represents bug fixes
* to a released firmware.
*/
uint8_t hwrm_fw_bld_8b;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version of the
* HWRM firmware.
*/
uint8_t hwrm_fw_rsvd_8b;
/*
* This field represents the major version of mgmt firmware.
* A change in major version represents a major release.
*/
uint8_t mgmt_fw_maj_8b;
/*
* This field represents the minor version of mgmt firmware.
* A change in minor version represents significant
* functionality changes.
*/
uint8_t mgmt_fw_min_8b;
/*
* This field represents the build version of mgmt firmware.
* A change in update version represents bug fixes.
*/
uint8_t mgmt_fw_bld_8b;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version
*/
uint8_t mgmt_fw_rsvd_8b;
/*
* This field represents the major version of network
* control firmware.
* A change in major version represents a major release.
*/
uint8_t netctrl_fw_maj_8b;
/*
* This field represents the minor version of network
* control firmware.
* A change in minor version represents significant
* functionality changes.
*/
uint8_t netctrl_fw_min_8b;
/*
* This field represents the build version of network
* control firmware.
* A change in update version represents bug fixes.
*/
uint8_t netctrl_fw_bld_8b;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version
*/
uint8_t netctrl_fw_rsvd_8b;
/*
* This field is used to indicate device's capabilities and
* configurations.
*/
uint32_t dev_caps_cfg;
/*
* If set to 1, then secure firmware update behavior
* is supported.
* If set to 0, then secure firmware update behavior is
* not supported.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
/*
* If set to 1, then firmware based DCBX agent is supported.
* If set to 0, then firmware based DCBX agent capability
* is not supported on this device.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
/*
* If set to 1, then HWRM short command format is supported.
* If set to 0, then HWRM short command format is not supported.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED UINT32_C(0x4)
/*
* If set to 1, then HWRM short command format is required.
* If set to 0, then HWRM short command format is not required.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED UINT32_C(0x8)
/*
* If set to 1, then the KONG host mailbox channel is supported.
* If set to 0, then the KONG host mailbox channel is not supported.
- * By default, this flag should be 0 for older version of core firmware.
+ * By default, this flag should be 0 for older version of core
+ * firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED UINT32_C(0x10)
/*
- * If set to 1, then the 64bit flow handle is supported in addition to the
- * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not
- * supported. By default, this flag should be 0 for older version of core firmware.
+ * If set to 1, then the 64bit flow handle is supported in addition
+ * to the legacy 16bit flow handle. If set to 0, then the 64bit flow
+ * handle is not supported. By default, this flag should be 0 for
+ * older version of core firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED UINT32_C(0x20)
/*
- * If set to 1, then filter type can be provided in filter_alloc or filter_cfg
- * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.
- * If set to 0, then filter types not supported.
- * By default, this flag should be 0 for older version of core firmware.
+ * If set to 1, then filter type can be provided in filter_alloc or
+ * filter_cfg filter types like L2 for l2 traffic and ROCE for roce &
+ * l2 traffic. If set to 0, then filter types not supported. By
+ * default, this flag should be 0 for older version of core firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED UINT32_C(0x40)
/*
- * If set to 1, firmware is capable to support virtio vSwitch offload model.
- * If set to 0, firmware can't supported virtio vSwitch offload model.
- * By default, this flag should be 0 for older version of core firmware.
+ * If set to 1, firmware is capable to support virtio vSwitch offload
+ * model. If set to 0, firmware can't supported virtio vSwitch
+ * offload model.
+ * By default, this flag should be 0 for older version of core
+ * firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED UINT32_C(0x80)
/*
* If set to 1, firmware is capable to support trusted VF.
* If set to 0, firmware is not capable to support trusted VF.
- * By default, this flag should be 0 for older version of core firmware.
+ * By default, this flag should be 0 for older version of core
+ * firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED UINT32_C(0x100)
/*
* If set to 1, firmware is capable to support flow aging.
* If set to 0, firmware is not capable to support flow aging.
- * By default, this flag should be 0 for older version of core firmware.
- * (deprecated)
+ * By default, this flag should be 0 for older version of core
+ * firmware. (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED UINT32_C(0x200)
/*
- * If set to 1, firmware is capable to support advanced flow counters like,
- * Meter drop counters and EEM counters.
- * If set to 0, firmware is not capable to support advanced flow counters.
- * By default, this flag should be 0 for older version of core firmware.
- * (deprecated)
+ * If set to 1, firmware is capable to support advanced flow counters
+ * like, Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow
+ * counters. By default, this flag should be 0 for older version of
+ * core firmware. (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED UINT32_C(0x400)
/*
* If set to 1, the firmware is able to support the use of the CFA
* Extended Exact Match(EEM) feature.
* If set to 0, firmware is not capable to support the use of the
* CFA EEM feature.
- * By default, this flag should be 0 for older version of core firmware.
- * (deprecated)
+ * By default, this flag should be 0 for older version of core
+ * firmware. (deprecated)
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED UINT32_C(0x800)
/*
- * If set to 1, the firmware is able to support advance CFA flow management
- * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
- * If set to 0, then the firmware doesn’t support the advance CFA flow management
- * features.
- * By default, this flag should be 0 for older version of core firmware.
+ * If set to 1, the firmware is able to support advance CFA flow
+ * management features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn't support the advance CFA
+ * flow management features.
+ * By default, this flag should be 0 for older version of core
+ * firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED UINT32_C(0x1000)
/*
* Deprecated and replaced with cfa_truflow_supported.
* If set to 1, the firmware is able to support TFLIB features.
- * If set to 0, then the firmware doesn’t support TFLIB features.
- * By default, this flag should be 0 for older version of core firmware.
+ * If set to 0, then the firmware doesn't support TFLIB features.
+ * By default, this flag should be 0 for older version of core
+ * firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED UINT32_C(0x2000)
/*
* If set to 1, the firmware is able to support TruFlow features.
- * If set to 0, then the firmware doesn’t support TruFlow features.
+ * If set to 0, then the firmware doesn't support TruFlow features.
* By default, this flag should be 0 for older version of
* core firmware.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED UINT32_C(0x4000)
/*
* If set to 1, then firmware supports secure boot.
* If set to 0, then firmware doesn't support secure boot.
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE UINT32_C(0x8000)
+ /*
+ * If set to 1, then firmware is able to support the secure solution
+ * feature.
+ * If set to 0, then firmware does not support the secure solution
+ * feature.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
*/
uint8_t roce_fw_maj_8b;
/*
* This field represents the minor version of RoCE firmware.
* A change in minor version represents significant
* functionality changes.
*/
uint8_t roce_fw_min_8b;
/*
* This field represents the build version of RoCE firmware.
* A change in update version represents bug fixes.
*/
uint8_t roce_fw_bld_8b;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version
*/
uint8_t roce_fw_rsvd_8b;
/*
* This field represents the name of HWRM FW (ASCII chars
* with NULL at the end).
*/
char hwrm_fw_name[16];
/*
* This field represents the name of mgmt FW (ASCII chars
* with NULL at the end).
*/
char mgmt_fw_name[16];
/*
* This field represents the name of network control
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
/* This field represents the active board package name. */
char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
*/
char roce_fw_name[16];
/* This field returns the chip number. */
uint16_t chip_num;
/* This field returns the revision of chip. */
uint8_t chip_rev;
/* This field returns the chip metal number. */
uint8_t chip_metal;
/* This field returns the bond id of the chip. */
uint8_t chip_bond_id;
- /* This value indicates the type of platform used for chip implementation. */
+ /*
+ * This value indicates the type of platform used for chip
+ * implementation.
+ */
uint8_t chip_platform_type;
/* ASIC */
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
/* FPGA platform of the chip. */
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
/* Palladium platform of the chip. */
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_LAST HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM
/*
* This field returns the maximum value of request window that
* is supported by the HWRM. The request window is mapped
* into device address space using MMIO.
*/
uint16_t max_req_win_len;
/*
* This field returns the maximum value of response buffer in
* bytes.
*/
uint16_t max_resp_len;
/*
* This field returns the default request timeout value in
* milliseconds.
*/
uint16_t def_req_timeout;
/*
* This field will indicate if any subsystems is not fully
* initialized.
*/
uint8_t flags;
/*
* If set to 1, it will indicate to host drivers that firmware is
* not ready to start full blown HWRM commands. Host drivers should
* re-try HWRM_VER_GET with some timeout period. The timeout period
* can be selected up to 5 seconds. Host drivers should also check
* for dev_not_rdy_backing_store to identify if flag is set due to
* backing store not been available.
* For Example, PCIe hot-plug:
* Hot plug timing is system dependent. It generally takes up to
* 600 milliseconds for firmware to clear DEV_NOT_RDY flag.
* If set to 0, device is ready to accept all HWRM commands.
*/
#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
/*
* If set to 1, external version present.
* If set to 0, external version not present.
*/
#define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
/*
* Firmware sets this flag along with dev_not_rdy flag to indicate
* host drivers that it has not completed resource initialization
* required for data path operations. Host drivers should not send
* any HWRM command that requires data path resources. Firmware will
- * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry
- * those commands once both the flags are cleared.
+ * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can
+ * retry those commands once both the flags are cleared.
* If this flag and dev_not_rdy flag are set to 0, device is ready
* to accept all HWRM commands.
*/
#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE UINT32_C(0x4)
uint8_t unused_0[2];
/*
* For backward compatibility this field must be set to 1.
* Older drivers might look for this field to be 1 before
* processing the message.
*/
uint8_t always_1;
/*
* This field represents the major version of HWRM interface
* specification supported by the HWRM implementation.
* The interface major version is intended to change only when
* non backward compatible changes are made to the HWRM
* interface specification. A HWRM implementation that is
* compliant with this specification shall provide value of 1
* in this field.
*/
uint16_t hwrm_intf_major;
/*
* This field represents the minor version of HWRM interface
* specification supported by the HWRM implementation.
* A change in interface minor version is used to reflect
* significant backward compatible modification to HWRM
* interface specification. This can be due to addition or
* removal of functionality. HWRM interface specifications
* with the same major version but different minor versions are
* compatible. A HWRM implementation that is compliant with
* this specification shall provide value of 2 in this field.
*/
uint16_t hwrm_intf_minor;
/*
* This field represents the update version of HWRM interface
* specification supported by the HWRM implementation. The
* interface update version is used to reflect minor changes or
* bug fixes to a released HWRM interface specification.
* A HWRM implementation that is compliant with this
* specification shall provide value of 2 in this field.
*/
uint16_t hwrm_intf_build;
/*
* This field represents the patch version of HWRM interface
* specification supported by the HWRM implementation.
*/
uint16_t hwrm_intf_patch;
/*
* This field represents the major version of HWRM firmware.
* A change in firmware major version represents a major
* firmware release.
*/
uint16_t hwrm_fw_major;
/*
* This field represents the minor version of HWRM firmware.
* A change in firmware minor version represents significant
* firmware functionality changes.
*/
uint16_t hwrm_fw_minor;
/*
* This field represents the build version of HWRM firmware.
* A change in firmware build version represents bug fixes to
* a released firmware.
*/
uint16_t hwrm_fw_build;
/*
* This field is a reserved field.
* This field can be used to represent firmware branches or customer
* specific releases tied to a specific (major,minor,update) version
* of the HWRM firmware.
*/
uint16_t hwrm_fw_patch;
/*
* This field represents the major version of mgmt firmware.
* A change in major version represents a major release.
*/
uint16_t mgmt_fw_major;
/*
* This field represents the minor version of HWRM firmware.
* A change in firmware minor version represents significant
* firmware functionality changes.
*/
uint16_t mgmt_fw_minor;
/*
* This field represents the build version of mgmt firmware.
* A change in update version represents bug fixes.
*/
uint16_t mgmt_fw_build;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version.
*/
uint16_t mgmt_fw_patch;
/*
* This field represents the major version of network control
* firmware. A change in major version represents
* a major release.
*/
uint16_t netctrl_fw_major;
/*
* This field represents the minor version of network control
* firmware. A change in minor version represents significant
* functionality changes.
*/
uint16_t netctrl_fw_minor;
/*
* This field represents the build version of network control
* firmware. A change in update version represents bug fixes.
*/
uint16_t netctrl_fw_build;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version
*/
uint16_t netctrl_fw_patch;
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
*/
uint16_t roce_fw_major;
/*
* This field represents the minor version of RoCE firmware.
* A change in minor version represents significant
* functionality changes.
*/
uint16_t roce_fw_minor;
/*
* This field represents the build version of RoCE firmware.
* A change in update version represents bug fixes.
*/
uint16_t roce_fw_build;
/*
* This field is a reserved field. This field can be used to
* represent firmware branches or customer specific releases
* tied to a specific (major,minor,update) version
*/
uint16_t roce_fw_patch;
/*
* This field returns the maximum extended request length acceptable
* by the device which allows requests greater than mailbox size when
* used with the short cmd request format.
*/
uint16_t max_ext_req_len;
/*
* This field returns the maximum request timeout value in seconds.
* For backward compatibility, a value of zero should be interpreted
* as the default value of 40 seconds. Drivers should always honor the
* maximum timeout, but are permitted to warn if a longer duration than
* this default is advertised. Values larger than 40 seconds should
* only be used as a stopgap measure to address a device limitation or
* for the purposes of test and debugging. The long term goal is for
* firmware to significantly reduce this value in the passage of time.
*/
uint16_t max_req_timeout;
uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
- * to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written. When
+ * writing a command completion or response to an internal processor,
* the order of writes has to be such that this field is written last.
*/
uint8_t valid;
} hwrm_ver_get_output_t, *phwrm_ver_get_output_t;
/* cfa_bds_read_cmd_data_msg (size:128b/16B) */
typedef struct cfa_bds_read_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/*
* This is read command. From 32 to 128B can be read from a table
* using this command.
*/
#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ
/* This value selects the table type to be acted upon. */
uint8_t table_type;
/* This value selects the table type to be acted upon. */
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
/* This command acts on the action table of the specified scope. */
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
/* This command acts on the exact match table of the specified scope. */
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_LAST CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed. A
* value of zero is invalid. Maximum value is 4.
*/
uint8_t data_size;
#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
/* This is the 32B index into the selected table to access. */
uint32_t table_index;
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
/*
* This is the 64b host address where you want the data returned to. The
* data will be written to the same function as the one that owns the SQ
* this command is read from. The bottom two bits of this value must be
* zero. The size of the write is controlled by the data_size field.
*/
uint64_t host_address;
} cfa_bds_read_cmd_data_msg_t, *pcfa_bds_read_cmd_data_msg_t;
/* cfa_bds_write_cmd_data_msg (size:1152b/144B) */
typedef struct cfa_bds_write_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/*
* This is write command. From 32 to 128B can be written to a table
* using this command.
*/
#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE
/* This value selects the table type to be acted upon. */
uint8_t write_thru_table_type;
/* This value selects the table type to be acted upon. */
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
/* This command acts on the action table of the specified scope. */
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
/* This command acts on the exact match table of the specified scope. */
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_LAST CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM
/*
* Indicates write-through control. Indicates write-through when set,
* or write back when cleared.
*/
#define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed. A
* value of zero is invalid. Maximum value is 4.
*/
uint8_t data_size;
#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
/* This is the 32B index into the selected table to access. */
uint32_t table_index;
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
uint32_t unused0;
uint32_t unused1;
/*
* This is the data to be written. Data length is determined by the
* data_size field. The bd_cnt in the encapsulating BD must also be set
* correctly to ensure that the BD is processed correctly and the full
* WRITE_CMD message is extracted from the BD.
*/
uint32_t dta[32];
} cfa_bds_write_cmd_data_msg_t, *pcfa_bds_write_cmd_data_msg_t;
/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */
typedef struct cfa_bds_read_clr_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/*
* This is read-clear command. 32B can be read from a table and
* a 16b mask can be used to clear specific 16b units after the
* read as an atomic operation.
*/
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR
/* This value selects the table type to be acted upon. */
uint8_t table_type;
/* This value selects the table type to be acted upon. */
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
/* This command acts on the action table of the specified scope. */
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
/* This command acts on the exact match table of the specified scope. */
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_LAST CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed.
* Always set the value to 1.
*/
uint8_t data_size;
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
/* This is the 32B index into the selected table to access. */
uint32_t table_index;
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
/*
* This is the 64b host address where you want the data returned to. The
* data will be written to the same function as the one that owns the SQ
* this command is read from. The bottom two bits of this value must be
* zero. The size of the write is controlled by the data_size field.
*/
uint64_t host_address;
/*
* This is active high clear mask for the 32B of data that this command
* can read. Bit 0 of the field will clear bits 15:0 of the first word
* of data read when set to '1'.
*/
uint16_t clear_mask;
uint16_t unused0[3];
uint16_t unused1[4];
} cfa_bds_read_clr_cmd_data_msg_t, *pcfa_bds_read_clr_cmd_data_msg_t;
/* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */
typedef struct cfa_bds_em_insert_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/*
* An exact match table insert will be attempted into the table.
* If there is a free location in the bucket, the payload will
* be written to the bucket.
*/
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT
/*
* Indicates write-through control. Indicates write-through when set,
* or write back when cleared.
*/
uint8_t write_thru;
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
/*
* Indicates write-through control. Indicates write-through when set,
* or write back when cleared.
*/
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed. A
* value of zero is invalid. Maximum value is 4.
*/
uint8_t data_size;
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
/* This is the 32B index into the selected table to access. */
uint32_t table_index;
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
/*
* This is the 64b host address where you want the data returned to. The
* data will be written to the same function as the one that owns the SQ
*/
uint64_t host_address;
/*
* This is the Exact Match Lookup Record. Data length is determined by
* the data_size field. The bd_cnt in the encapsulating BD must also be
*/
uint32_t dta[32];
} cfa_bds_em_insert_cmd_data_msg_t, *pcfa_bds_em_insert_cmd_data_msg_t;
/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */
typedef struct cfa_bds_em_delete_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/* An exact match table delete will be attempted. */
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE
/*
* Indicates write-through control. Indicates write-through when set,
* or write back when cleared.
*/
uint8_t write_thru;
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
/*
* Indicates write-through control. Indicates write-through when set,
* or write back when cleared.
*/
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed. A
* value of zero is invalid. Maximum value is 4.
*/
uint8_t data_size;
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
uint32_t unused0;
/*
* This is the 64b host address where you want the data returned to. The
* data will be written to the same function as the one that owns the SQ
*/
uint64_t host_address;
/*
* This is the Exact Match Lookup Record. Data length is determined by
* the data_size field. The bd_cnt in the encapsulating BD must also be
*/
uint64_t dta;
uint64_t unused1;
} cfa_bds_em_delete_cmd_data_msg_t, *pcfa_bds_em_delete_cmd_data_msg_t;
/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */
typedef struct cfa_bds_invalidate_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/*
* The specified table area will be invalidated. If it is needed.
* again, it will be read from the backing store.
*/
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE
/* This value selects the table type to be acted upon. */
uint8_t table_type;
/* This value selects the table type to be acted upon. */
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
/* This command acts on the action table of the specified scope. */
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
/* This command acts on the exact match table of the specified scope. */
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_LAST CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/* This value specifies the number of cache lines to invalidate. */
uint8_t data_size;
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
/* This is the 32B index into the selected table to access. */
uint32_t table_index;
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
uint64_t unused;
} cfa_bds_invalidate_cmd_data_msg_t, *pcfa_bds_invalidate_cmd_data_msg_t;
/* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */
typedef struct cfa_bds_event_collect_cmd_data_msg {
/* This value selects the format for the mid-path command for the CFA. */
uint8_t opcode;
/* Reads notification messages from the Host Notification Queue. */
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT UINT32_C(0x6)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_LAST CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT
uint8_t unused0;
/* This value selects which table scope will be accessed. */
uint8_t table_scope;
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
/*
* This value identifies the number of 32B units will be accessed. A
* value of zero is invalid. Maximum value is 4.
*/
uint8_t data_size;
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
uint32_t unused1;
/*
* This is the 64b host address where you want the data returned to. The
* data will be written to the same function as the one that owns the SQ
*/
uint64_t host_address;
} cfa_bds_event_collect_cmd_data_msg_t, *pcfa_bds_event_collect_cmd_data_msg_t;
/* ce_bds_add_data_msg (size:576b/72B) */
typedef struct ce_bds_add_data_msg {
uint32_t version_algorithm_kid_opcode;
/*
* This value selects the operation for the mid-path command for the
* crypto blocks.
*/
#define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
/*
* This is the add command. Using this opcode, Host Driver can add
* information required for kTLS processing. The information is
* updated in the CFCK context.
*/
#define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
#define CE_BDS_ADD_DATA_MSG_OPCODE_LAST CE_BDS_ADD_DATA_MSG_OPCODE_ADD
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
#define CE_BDS_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_ADD_DATA_MSG_KID_SFT 4
/*
* Currently only two algorithms are supported, AES_GCM_128 and
* AES_GCM_256. Additional bits for future growth.
*/
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_SFT 24
/* AES_GCM_128 Algorithm */
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 UINT32_C(0x1000000)
/* AES_GCM_256 Algorithm */
#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 UINT32_C(0x2000000)
/*
* Version number of TLS connection. HW will provide registers that
* converts the 4b encoded version number to 16b of actual version
* number in the TLS Header. This field is initialized/updated by
* this "KTLS crypto add" mid-path command.
*/
#define CE_BDS_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
#define CE_BDS_ADD_DATA_MSG_VERSION_SFT 28
/* TLS1.2 Version */
#define CE_BDS_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
/* TLS1.3 Version */
#define CE_BDS_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
#define CE_BDS_ADD_DATA_MSG__LAST CE_BDS_ADD_DATA_MSG__TLS1_3
uint8_t ctx_kind;
/* This field selects the context kind for the request. */
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0
/* Crypto key transmit context */
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)
/* Crypto key receive context */
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)
#define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX
uint8_t unused0[3];
/*
* Salt is part of the nonce that is used as the Initial Vector (IV) in
* AES-GCM cipher suites. These are exchanged as part of the handshake
* process and is either the client_write_iv (when the client is
* sending) or server_write_iv (when the server is sending). In
* TLS1.2, 4B of Salt is concatenated with 8B of explicit_nonce to
* generate the 12B of IV. In TLS1.3, 8B of TLS record sequence number
* is zero padded to 12B and then xor'ed with the 4B of salt to generate
* the 12B of IV. This value is initialized by this mid-path command.
*/
uint8_t salt[4];
uint8_t unused1[4];
/*
* This field keeps track of the TCP sequence number that is expected as
* the first byte in the next TCP packet. This field is calculated by HW
* using the output of the parser. The field is initialized as part of
* the Mid-path BD download/update of a kTLS connection. For every TCP
* packet processed, TCE HW will update the value to Current packet TCP
* sequence number + Current packet TCP Payload Length.
*/
uint32_t pkt_tcp_seq_num;
/*
* This field maintains the TCP sequence number of the first byte in the
* header of the active TLS record. This field is initialized as part of
* the Mid-path BD download/update of a kTLS connection. For every
* record that is processed, TCE HW copies the value from the
* next_tls_header_tcp_seq_num field.
*/
uint32_t tls_header_tcp_seq_num;
/*
* This is sequence number for the TLS record in a particular session.
* In TLS1.2, record sequence number is part of the Associated Data (AD)
* in the AEAD algorithm. In TLS1.3, record sequence number is part of
* the Initial Vector (IV). The field is initialized as part of the
* mid-path BD download/update of a kTLS connection. TCE HW increments
* the field after that for every record processed as it parses the TCP
* packet.
*/
uint64_t record_seq_num;
/*
* Key used for encrypting or decrypting TLS records. The Key is
* exchanged during the hand-shake protocol by the client-server and
* provided to HW through this mid-path BD.
*/
uint8_t session_key[32];
/*
* Additional IV that is exchanged as part of sessions setup between
* the two end points. This field is used for TLS1.3 only.
*/
uint8_t addl_iv[8];
} ce_bds_add_data_msg_t, *pce_bds_add_data_msg_t;
/* ce_bds_delete_data_msg (size:32b/4B) */
typedef struct ce_bds_delete_data_msg {
uint32_t kid_opcode_ctx_kind;
/*
* This value selects the operation for the mid-path command for the
* crypto blocks.
*/
#define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
/*
* This is the delete command. Using this opcode, the host Driver
* can remove a key context from the CFCK. If context is deleted
* and packets with the same KID come through the pipeline, the
* following actions are taken. For transmit packets, no crypto
* operation will be performed, payload will be zero'ed out. For
* receive packets, no crypto operation will be performed,
* payload will be unmodified.
*/
#define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
#define CE_BDS_DELETE_DATA_MSG_OPCODE_LAST CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
#define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_DELETE_DATA_MSG_KID_SFT 4
/* This field selects the context kind for the request. */
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_SFT 24
/* Crypto Key Transmit Context. */
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24)
/* Crypto Key Receive Context. */
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24)
/* QUIC Key Transmit Context. */
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24)
/* QUIC Key Receive Context. */
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX
} ce_bds_delete_data_msg_t, *pce_bds_delete_data_msg_t;
/* ce_bds_resync_resp_ack_msg (size:128b/16B) */
typedef struct ce_bds_resync_resp_ack_msg {
uint32_t resync_status_kid_opcode;
/*
* This value selects the operation for the mid-path command for the
* crypto blocks.
*/
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
/*
* This command is used by the driver as a response to the resync
* request sent by the crypto engine.
*/
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_LAST CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_SFT 4
/*
* This field indicates if the resync request resulted in a success or
* a failure.
*/
#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
/*
* An ACK indicates that the driver was able to find the TLS record
* associated with TCP sequence number provided by the HW
*/
#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK (UINT32_C(0x0) << 24)
#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_LAST CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK
/*
* This field is the echo of the TCP sequence number provided in the
* resync request by the HW. If HW sent multiple resync requests, it
* only tracks the latest TCP sequence number. When the response from
* the Driver doesn't match the latest request, HW will drop the resync
* response.
*/
uint32_t resync_record_tcp_seq_num;
/*
* This field indicates the TLS record sequence number associated with
* the resync request. HW will take this number and add the delta records
* it has found since sending the resync request, update the context and
* resume decrypting records.
*/
uint64_t resync_record_seq_num;
} ce_bds_resync_resp_ack_msg_t, *pce_bds_resync_resp_ack_msg_t;
/* ce_bds_resync_resp_nack_msg (size:64b/8B) */
typedef struct ce_bds_resync_resp_nack_msg {
uint32_t resync_status_kid_opcode;
/*
* This value selects the operation for the mid-path command for the
* crypto blocks.
*/
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
/*
* This command is used by the driver as a response to the resync
* request sent by the crypto engine.
*/
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_LAST CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_SFT 4
/*
* This field indicates if the resync request resulted in a success or
* a failure.
*/
#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
/*
* An NAK indicates that the driver wasn't able to find the TLS
* record associated with TCP sequence number provided by the HW
*/
#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK (UINT32_C(0x1) << 24)
#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_LAST CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK
/*
* This field is the echo of the TCP sequence number provided in the
* resync request by the HW. If HW sent multiple resync requests, it
* only tracks the latest TCP sequence number. When the response from
* the Driver doesn't match the latest request, HW will drop the resync
* response.
*/
uint32_t resync_record_tcp_seq_num;
} ce_bds_resync_resp_nack_msg_t, *pce_bds_resync_resp_nack_msg_t;
/* crypto_presync_bd_cmd (size:256b/32B) */
typedef struct crypto_presync_bd_cmd {
uint8_t flags;
/*
* Typically, presync BDs are used for packet retransmissions. Source
* port sends all the packets in order over the network to destination
* port and packets get dropped in the network. The destination port
- * will request retranmission of dropped packets and source port driver
- * will send presync BD to setup the transmitter appropriately. It will
- * provide the start and end TCP sequence number of the data to be
- * transmitted. HW keeps two sets of context variable, one for in order
- * traffic and one for retransmission traffic. HW is designed to
+ * will request retransmission of dropped packets and source port
+ * driver will send presync BD to setup the transmitter appropriately.
+ * It will provide the start and end TCP sequence number of the data to
+ * be transmitted. HW keeps two sets of context variable, one for in
+ * order traffic and one for retransmission traffic. HW is designed to
* transmit everything posted in the presync BD and return to in order
* mode after that. No inorder context variables are updated in the
* process. There is a special case where packets can be dropped
* between the TCP stack and Device Driver (Berkeley Packet Filter for
* ex) and HW still needs to transmit rest of the traffic. In this
* mode, driver will send a presync BD as if it is a retransmission but
* at the end of the transmission, the in order variables need to be
* updated. This flag is used by driver to indicate that in order
* variables needs to be updated at the end of completing the task
* associated with the presync BD.
*/
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR UINT32_C(0x1)
/*
* When packet with an authentication TAG is lost in the network,
* During retransmission Device driver will post the entire record for
* the hardware to recalculate the TAG. Hardware is set to retransmit
* only portions of the record, it does so by looking at the Header
* TCP Sequence Number and Start TCP Sequence Number. However, there
* is a case where the header packet gets dropped in the stack for ex
* BPF packet filter and it is impossible for the Hardware to
* determine if this is a case of full replay for only the TAG
* generation.
*/
#define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN UINT32_C(0x2)
uint8_t unused0;
uint16_t unused1;
/*
* This field maintains the TCP sequence number of the first byte in the
* Header of the active TLS record. This field is set to 0 during
* mid-path BD updates, but is set to correct value when a presync BD is
* detected. For every record that is processed, the value from the
* next_tls_header_tcp_seq_num field is copied.
*/
uint32_t header_tcp_seq_num;
/*
* When a retransmitted packet has a TLS authentication TAG present and
* the data spans multiple TCP Packets, HW is required to read the entire
* record to recalculate the TAG but only transmit what is required. This
* field is the start TCP sequence number of the packet(s) that need to
* be re-transmitted. This field is initialized to 0 during Mid-path BD
* add command and initialized to value provided by the driver when
* Pre-sync BD is detected. This field is never updated unless another
* Pre-sync BD signaling a new retransmission is scheduled.
*/
uint32_t start_tcp_seq_num;
/*
* When a retransmitted packet has a TLS authentication TAG present and
* the data spans multiple TCP Packets, HW is required to read the
* entire record to recalculate the TAG but only transmit what is
* required. This field is the end TCP sequence number of the packet(s)
* that need to be re-transmitted. This field is initialized to 0 during
* Mid-path BD add command and initialized to value provided by the
* driver when Pre-sync BD is detected. This field is never updated
* unless another Pre-sync BD signaling a new retransmission is
* scheduled.
*/
uint32_t end_tcp_seq_num;
/*
* For TLS1.2, an explicit nonce is used as part of the IV (concatenated
* with the SALT). For retrans packets, this field is extracted from the
* TLS record, field right after the TLS Header and stored in the
* context. This field needs to be stored in context as TCP segmentation
* could have split the field into multiple TCP packets. This value is
* initialized to 0 when presync BD is detected by taking the value from
* the first TLS header. When subsequent TLS Headers are detected, the
* value is extracted from packet.
*/
uint8_t explicit_nonce[8];
/*
* This is sequence number for the TLS record in a particular session. In
* TLS1.2, record sequence number is part of the Associated Data (AD) in
* the AEAD algorithm. In TLS1.3, record sequence number is part of the
* Initial Vector (IV). The field is initialized to 0 during Mid-path BD
* download. Is initialized to correct value when a pre-sync BD is
* detected. TCE HW increments the field after that for every record
* processed as it parses the TCP packet. Subsequent pre-sync BDs
* delivering more retransmission instruction will also update this
* field.
*/
uint64_t record_seq_num;
} crypto_presync_bd_cmd_t, *pcrypto_presync_bd_cmd_t;
/* ce_bds_quic_add_data_msg (size:832b/104B) */
typedef struct ce_bds_quic_add_data_msg {
uint32_t ver_algo_kid_opcode;
/*
* This value selects the operation for the mid-path command for the
* crypto blocks.
*/
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0
/*
* This is the add command. Using this opcode, Host Driver can add
* information required for QUIC processing. The information is
* updated in the CFCK context.
*/
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated QUIC offloaded connection.
*/
#define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
#define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4
/* Algorithm used for encryption and decryption. */
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24
/* AES_GCM_128 Algorithm. */
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 (UINT32_C(0x1) << 24)
/* AES_GCM_256 Algorithm. */
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 (UINT32_C(0x2) << 24)
/* Chacha20 Algorithm. */
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 (UINT32_C(0x3) << 24)
#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20
/* Version number of QUIC connection. */
#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28
/* TLS1.2 Version */
#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
/* TLS1.3 Version */
#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
/* DTLS1.2 Version */
#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 (UINT32_C(0x2) << 28)
/* DTLS1.2 for RoCE Version */
#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE (UINT32_C(0x3) << 28)
/* QUIC Version */
#define CE_BDS_QUIC_ADD_DATA_MSG__QUIC (UINT32_C(0x4) << 28)
#define CE_BDS_QUIC_ADD_DATA_MSG__LAST CE_BDS_QUIC_ADD_DATA_MSG__QUIC
uint32_t ctx_kind_dcid_width_key_phase;
/* Key phase. */
#define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)
/* Destination connection ID width. */
#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1
/* This field selects the context kind for the request. */
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6
/* QUIC key transmit context */
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 6)
/* QUIC key receive context */
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 6)
#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX
uint64_t unused_0;
/*
* Least-significant 64 bits (of 96) of additional IV that is
* exchanged as part of sessions setup between the two end
* points for QUIC operations.
*/
- uint64_t quic_iv_lo;
+ uint8_t quic_iv_lo[8];
/*
* Most-significant 32 bits (of 96) of additional IV that is
* exchanged as part of sessions setup between the two end
* points for QUIC operations.
*/
- uint32_t quic_iv_hi;
+ uint8_t quic_iv_hi[4];
uint32_t unused_1;
/*
* Key used for encrypting or decrypting records. The Key is exchanged
* as part of sessions setup between the two end points through this
* mid-path BD.
*/
- uint32_t session_key[8];
+ uint8_t session_key[32];
/* Header protection key. */
- uint32_t hp_key[8];
+ uint8_t hp_key[32];
/* Packet number associated with the QUIC connection. */
uint64_t pkt_number;
} ce_bds_quic_add_data_msg_t, *pce_bds_quic_add_data_msg_t;
/* bd_base (size:64b/8B) */
typedef struct bd_base {
uint8_t type;
/* This value identifies the type of buffer descriptor. */
#define BD_BASE_TYPE_MASK UINT32_C(0x3f)
#define BD_BASE_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is used for
* normal L2 packet transmission.
*/
#define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
/*
* Indicates that this BD is 1BB long and is an empty
* TX BD. Not valid for use by the driver.
*/
#define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
/*
* Indicates that this BD is 16B long and is an RX Producer
* (i.e. empty) buffer descriptor.
*/
#define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
/*
* Indicates that this BD is 16B long and is an RX
* Producer Buffer BD.
*/
#define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
/*
* Indicates that this BD is 16B long and is an
* RX Producer Assembly Buffer Descriptor.
*/
#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
/*
* Indicates that this BD is used to issue a command to one of
* the mid-path destinations.
*/
#define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
/*
* Indicates that this BD is used to issue a cryptographic pre-
* sync command through the fast path and destined for TCE.
*/
#define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
/*
* Indicates a timed transmit BD. This is a 16b BD that is inserted
* into a packet BD chain immediately after the first BD. It is used
* to control the flow in a timed transmit operation.
*/
#define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
/*
* Indicates that this BD is 32B long and is used for
* normal L2 packet transmission.
*/
#define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
/*
* Indicates that this BD is 32B long and is used for
* L2 packet transmission for small packets that require
* low latency.
*/
#define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
#define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE
uint8_t unused_1[7];
} bd_base_t, *pbd_base_t;
/* tx_bd_short (size:128b/16B) */
typedef struct tx_bd_short {
/*
* All bits in this field must be valid on the first BD of a packet.
* Only the packet_end bit must be valid for the remaining BDs
* of a packet.
*/
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_SHORT_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is used for
* normal L2 packet transmission.
*/
#define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
#define TX_BD_SHORT_TYPE_LAST TX_BD_SHORT_TYPE_TX_BD_SHORT
/*
* All bits in this field must be valid on the first BD of a packet.
* Only the packet_end bit must be valid for the remaining BDs
* of a packet.
*/
#define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
#define TX_BD_SHORT_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
* pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
/*
* If set to 1, the device will not generate a completion for
* this transmit packet unless there is an error in it's
* processing.
* If this bit
* is set to 0, then the packet will be completed normally.
*
* This bit must be valid only on the first BD of a packet.
*/
#define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
/*
* This value indicates how many 16B BD locations are consumed
* in the ring by this packet.
* A value of 1 indicates that this BD is the only BD (and that
* it is a short BD). A value
* of 3 indicates either 3 short BDs or 1 long BD and one short
* BD in the packet. A value of 0 indicates
* that there are 32 BD locations in the packet (the maximum).
*
* This field is valid only on the first BD of a packet.
*/
#define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
/*
* This value is a hint for the length of the entire packet.
* It is used by the chip to optimize internal processing.
*
* The packet will be dropped if the hint is too short.
*
* This field is valid only on the first BD of a packet.
*/
#define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define TX_BD_SHORT_FLAGS_LHINT_SFT 13
/* indicates packet length < 512B */
#define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
/* indicates 512 <= packet length < 1KB */
#define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
/* indicates 1KB <= packet length < 2KB */
#define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
/* indicates packet length >= 2KB */
#define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
#define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
/*
* If set to 1, the device immediately updates the Send Consumer
* Index after the buffer associated with this descriptor has
* been transferred via DMA to NIC memory from host memory. An
* interrupt may or may not be generated according to the state
* of the interrupt avoidance mechanisms. If this bit
* is set to 0, then the Consumer Index is only updated as soon
* as one of the host interrupt coalescing conditions has been met.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
/*
* This is the length of the host physical buffer this BD describes
* in bytes.
*
* This field must be valid on all BDs of a packet.
*/
uint16_t len;
/*
* The opaque data field is pass through to the completion and can be
* used for any data that the driver wants to associate with the
* transmit BD.
*
* This field must be valid on the first BD of a packet. If completion
* coalescing is enabled on the TX ring, it is suggested that the driver
* populate the opaque field to indicate the specific TX ring with which
* the completion is associated, then utilize the opaque and sq_cons_idx
* fields in the coalesced completion record to determine the specific
* packets that are to be completed on that ring.
*/
uint32_t opaque;
/*
* This is the host physical address for the portion of the packet
* described by this TX BD.
*
* This value must be valid on all BDs of a packet.
*/
- uint64_t addr;
+ uint32_t addr_lo;
+ uint32_t addr_hi;
} tx_bd_short_t, *ptx_bd_short_t;
/* tx_bd_long (size:128b/16B) */
typedef struct tx_bd_long {
/* This value identifies the type of buffer descriptor. */
uint16_t flags_type;
/*
* This value indicates the type of buffer descriptor.
* packet.
*/
#define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_LONG_TYPE_SFT 0
/*
* Indicates that this BD is 32B long and is used for
* normal L2 packet transmission.
*/
#define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
#define TX_BD_LONG_TYPE_LAST TX_BD_LONG_TYPE_TX_BD_LONG
/*
* All bits in this field must be valid on the first BD of a packet.
* Only the packet_end bit must be valid for the remaining BDs
* of a packet.
*/
#define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
#define TX_BD_LONG_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
* pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
/*
* If set to 1, the device will not generate a completion for
* this transmit packet unless there is an error in it's
* processing.
* If this bit
* is set to 0, then the packet will be completed normally.
*
* This bit must be valid only on the first BD of a packet.
*/
#define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
/*
* This value indicates how many 16B BD locations are consumed
* in the ring by this packet.
* A value of 1 indicates that this BD is the only BD (and that
* it is a short BD). A value
* of 3 indicates either 3 short BDs or 1 long BD and one short
* BD in the packet. A value of 0 indicates
* that there are 32 BD locations in the packet (the maximum).
*
* This field is valid only on the first BD of a packet.
*/
#define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
/*
* This value is a hint for the length of the entire packet.
* It is used by the chip to optimize internal processing.
*
* The packet will be dropped if the hint is too short.
*
* This field is valid only on the first BD of a packet.
*/
#define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define TX_BD_LONG_FLAGS_LHINT_SFT 13
/* indicates packet length < 512B */
#define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
/* indicates 512 <= packet length < 1KB */
#define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
/* indicates 1KB <= packet length < 2KB */
#define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
/* indicates packet length >= 2KB */
#define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
#define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
/*
* If set to 1, the device immediately updates the Send Consumer
* Index after the buffer associated with this descriptor has
* been transferred via DMA to NIC memory from host memory. An
* interrupt may or may not be generated according to the state
* of the interrupt avoidance mechanisms. If this bit
* is set to 0, then the Consumer Index is only updated as soon
* as one of the host interrupt coalescing conditions has been met.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
/*
* This is the length of the host physical buffer this BD describes
* in bytes.
*
* This field must be valid on all BDs of a packet.
*/
uint16_t len;
/*
* The opaque data field is passed through to the completion and can be
* used for any data that the driver wants to associate with the
* transmit BD.
*
* This field must be valid on the first BD of a packet. If completion
* coalescing is enabled on the TX ring, it is suggested that the driver
* populate the opaque field to indicate the specific TX ring with which
* the completion is associated, then utilize the opaque and sq_cons_idx
* fields in the coalesced completion record to determine the specific
* packets that are to be completed on that ring.
*/
uint32_t opaque;
/*
* This is the host physical address for the portion of the packet
* described by this TX BD.
*
* This value must be valid on all BDs of a packet.
*/
uint64_t addr;
} tx_bd_long_t, *ptx_bd_long_t;
/* Last 16 bytes of tx_bd_long. */
/* tx_bd_long_hi (size:128b/16B) */
typedef struct tx_bd_long_hi {
/*
* All bits in this field must be valid on the first BD of a packet.
* Their value on other BDs of the packet will be ignored.
*/
uint16_t lflags;
/*
* If set to 1, the controller replaces the TCP/UPD checksum
* fields of normal TCP/UPD checksum, or the inner TCP/UDP
* checksum field of the encapsulated TCP/UDP packets with the
* hardware calculated TCP/UDP checksum for the packet associated
* with this descriptor. The flag is ignored if the LSO flag is set.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
/*
* If set to 1, the controller replaces the IP checksum of the
* normal packets, or the inner IP checksum of the encapsulated
* packets with the hardware calculated IP checksum for the
* packet associated with this descriptor.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
/*
* If set to 1, the controller will not append an Ethernet CRC
* to the end of the frame.
*
* This bit must be valid on the first BD of a packet.
*
* Packet must be 64B or longer when this flag is set. It is not
* useful to use this bit with any form of TX offload such as
* CSO or LSO. The intent is that the packet from the host already
* has a valid Ethernet CRC on the packet.
*/
#define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
/*
* This bit, in conjunction with the stamp_1step bit, controls whether
* a TX packet timestamp is collected and the type of timestamp that
* is collected.
*
* This bit must be valid on the first BD of a packet.
*
* Enumerations of the concatenation { stamp, stamp_1step } are
* as follows:
*
* - 2'b00: ts_none - no timestamp
* - 2'b01: ts_ptp_1step - 1-step PTP
* - 2'b10: ts_2cmpl - 2-step PTP timestamp or PA timestamp
* - 2'b11: ts_rsvd - reserved, same behavior as ts_none
* For the ts_2cmpl enumeration, an additional completion is returned.
* This additional completion may carry a 2-step PTP timestamp or a PA
* timestamp, depending on parsing of the transmitted packet.
*/
#define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
/*
* If set to 1, The controller replaces the tunnel IP checksum
* field with hardware calculated IP checksum for the IP header
* of the packet associated with this descriptor.
*
* For outer UDP checksum, global outer UDP checksum TE_NIC register
* needs to be enabled. If the global outer UDP checksum TE_NIC
* register bit is set, outer UDP checksum will be calculated for
* the following cases:
* 1. Packets with tcp_udp_chksum flag set to offload checksum for
* inner packet AND the inner packet is TCP/UDP. If the inner packet
* is ICMP for example (non-TCP/UDP), even if the tcp_udp_chksum is
* set, the outer UDP checksum will not be calculated.
* 2. Packets with lso flag set which implies inner TCP checksum
* calculation as part of LSO operation.
*/
#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
/*
* If set to 1, the device will treat this packet with LSO(Large
* Send Offload) processing for both normal or encapsulated
* packets, which is a form of TCP segmentation. When this bit
* is 1, the hdr_size and mss fields must be valid. The driver
* doesn't need to set ot_ip_chksum, t_ip_chksum, ip_chksum, and
* tcp_udp_chksum flags since the controller will replace the
* appropriate checksum fields for segmented packets.
*
* When this bit is 1, the hdr_size and mss fields must be valid.
*/
#define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
/*
* If set to zero when LSO is '1', then the IPID will be treated
* as a 16b number and will be wrapped if it exceeds a value of
* 0xffff.
*
* If set to one when LSO is '1', then the IPID will be treated
- * as a 15b number and will be wrapped if it exceeds a value 0f
+ * as a 15b number and will be wrapped if it exceeds a value of
* 0x7fff.
*/
#define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
/*
* If set to zero when LSO is '1', then the IPID of the tunnel
* IP header will not be modified during LSO operations.
*
* If set to one when LSO is '1', then the IPID of the tunnel
* IP header will be incremented for each subsequent segment of an
* LSO operation.
*
* The flag is ignored if the LSO packet is a normal (non-tunneled)
* TCP packet.
*/
#define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
/*
* If set to '1', then the RoCE ICRC will be appended to the
* packet. Packet must be a valid RoCE format packet.
*/
#define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
/*
* If set to '1', then the FCoE CRC will be appended to the
* packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
/*
* If set to '1', then the timestamp from the BD is used. If cleared
* to 0, then TWE provides the timestamp.
*/
/*
* The BD timestamp feature cannot be enabled concurrently with
* cryptography (KTLS), thus lflags.bd_ts_en and lflags.crypto_en
* shall never both be set in a BD.
*/
#define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
/*
* If set to '1', this operation will cause a trace capture in each
* block it passes through.
*/
#define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
/*
* This bit, in conjunction with the stamp bit, controls whether a
* TX packet timestamp is collected and the type of timestamp that
* is collected.
*
* See the stamp field for a description of the valid combinations of
* stamp and stamp_1step.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
/*
* If set to '1', the controller replaces the Outer-tunnel IP checksum
* field with hardware calculated IP checksum for the IP header of the
* packet associated with this descriptor. For outer UDP checksum, it
* will be the following behavior for all cases independent of
* settings of inner LSO and checksum offload BD flags.
* If outer UDP checksum is 0, then do not update it.
- * If outer UDP checksum is non zero, then the hardware should
+ * If outer UDP checksum is non zero, then the hardware should
* compute and update it.
*/
#define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
/*
* If set to zero when LSO is '1', then the IPID of the Outer-tunnel
* IP header will not be modified during LSO operations. If set to one
* when LSO is '1', then the IPID of the Outer-tunnel IP header will
* be incremented for each subsequent segment of an LSO operation. The
* flag is ignored if the LSO packet is a normal (non-tunneled) TCP
* packet.
*/
#define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
/*
* If set to '1', When set to 1, KTLS encryption will be enabled for
* the packet.
*/
/*
* The BD timestamp feature cannot be enabled concurrently with
* cryptography (KTLS), thus lflags.bd_ts_en and lflags.crypto_en
* shall never both be set in a BD.
*/
#define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
uint16_t kid_or_ts_low_hdr_size;
/*
* When LSO is '1', this field must contain the offset of the
* TCP payload from the beginning of the packet in as
* 16b words. In case of encapsulated/tunneling packet, this field
* contains the offset of the inner TCP payload from beginning of the
* packet as 16-bit words.
*
* This value must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
#define TX_BD_LONG_HDR_SIZE_SFT 0
/*
* If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
* timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
* the 20-bit KID.
*/
/*
* The KID value of all-ones is reserved for non-KTLS packets, which
* only implies that this value must not be used when filling this
* field for crypto packets.
*/
#define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
#define TX_BD_LONG_KID_OR_TS_LOW_SFT 9
uint32_t kid_or_ts_high_mss;
/*
* This is the MSS value that will be used to do the LSO processing.
* The value is the length in bytes of the TCP payload for each
* segment generated by the LSO operation.
*
* This value must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
#define TX_BD_LONG_MSS_SFT 0
/*
* If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
* timestamp. If lflags.crypto_en is 1, the least significant 13 bits
* of this field contain the upper 13 bits of the 20-bit KID.
*/
/*
* The KID value of all-ones is reserved for non-KTLS packets, which
* only implies that this value must not be used when filling this
* field for crypto packets.
*/
#define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
#define TX_BD_LONG_KID_OR_TS_HIGH_SFT 15
/*
* This value selects bits 25:16 of the CFA action to perform on the
* packet. See the cfa_action field for more information.
*/
uint16_t cfa_action_high;
#define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
/*
* This value selects a CFA action to perform on the packet.
* Set this value to zero if no CFA action is desired.
*
* This value must be valid on the first BD of a packet.
*/
uint16_t cfa_action;
/*
* This value is action meta-data that defines CFA edit operations
* that are done in addition to any action editing.
*/
uint32_t cfa_meta;
/* When key=1, This is the VLAN tag VID value. */
#define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
/* When key=1, This is the VLAN tag DE value. */
#define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
/* When key=1, This is the VLAN tag PRI value. */
#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
/* When key=1, This is the VLAN tag TPID select value. */
#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
/* 0x88a8 */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
/* 0x8100 */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
/* 0x9100 */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
/* 0x9200 */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
/* 0x9300 */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
/* Value programmed in CFA VLANTPID register. */
#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define TX_BD_LONG_CFA_META_VLAN_TPID_LAST TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
/* When key=1, This is the VLAN tag TPID select value. */
#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
/*
* This field identifies the type of edit to be performed
* on the packet.
*
* This value must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define TX_BD_LONG_CFA_META_KEY_SFT 28
/* No editing */
#define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
/*
* - meta[17:16] - TPID select value (0 = 0x8100).
* - meta[15:12] - PRI/DE value.
* - meta[11:0] - VID value.
*/
#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
/*
* Provide metadata
* - Wh+/SR - this option is not supported.
* - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
* is set in the Lookup Table.
- * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
+ * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
* en_bd_meta is set in the Lookup Table.
*/
#define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
#define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER
} tx_bd_long_hi_t, *ptx_bd_long_hi_t;
/*
* This structure is used to inform the NIC of packet data that needs to
* be transmitted with additional processing that requires extra data
* such as VLAN insertion plus attached inline data.
* This BD type may be used to improve latency for small packets needing
* the additional extended features supported by long BDs.
*/
/* tx_bd_long_inline (size:256b/32B) */
typedef struct tx_bd_long_inline {
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_LONG_INLINE_TYPE_SFT 0
/*
* This type of BD is 32B long and is used for inline L2 packet
* transmission.
*/
#define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
#define TX_BD_LONG_INLINE_TYPE_LAST TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE
/*
* All bits in this field may be set on the first BD of a packet.
* Only the packet_end bit may be set in non-first BDs.
*/
#define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
#define TX_BD_LONG_INLINE_FLAGS_SFT 6
/*
* If set to 1, the packet ends with the data in the buffer
* pointed to by this descriptor. This flag must be
* valid on every BD.
*/
#define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
/*
* If set to 1, the device will not generate a completion for
* this transmit packet unless there is an error in its processing.
* If this bit is set to 0, then the packet will be completed
* normally.
*
* This bit may be set only on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
/*
* This value indicates how many 16B BD locations are consumed
* in the ring by this packet, including the BD and inline
* data.
*/
#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8
/* This field is deprecated. */
#define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
#define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13
/*
* If set to 1, the device immediately updates the Send Consumer
* Index after the buffer associated with this descriptor has
* been transferred via DMA to NIC memory from host memory. An
* interrupt may or may not be generated according to the state
* of the interrupt avoidance mechanisms. If this bit
* is set to 0, then the Consumer Index is only updated as soon
* as one of the host interrupt coalescing conditions has been met.
*
* This bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
/*
* This is the length of the inline data, not including BD length, in
* bytes.
* The maximum value is 480.
*
* This field must be valid on all BDs of a packet.
*/
/*
* A fatal error will be generated if the value of this field
* does not correspond with the value of flags.bd_cnt. For example, if
* this field carries a value of 20, then bd_cnt must equal 4.
*/
uint16_t len;
/*
* The opaque data field is passed through to the completion and can be
* used for any data that the driver wants to associate with the
* transmit BD. This field must be valid on the first BD of a packet.
* If completion coalescing is enabled on the TX ring, it is suggested
* that the driver populate the opaque field to indicate the specific
* TX ring with which the completion is associated, then utilize the
* opaque and sq_cons_idx fields in the coalesced completion record to
* determine the specific packets that are to be completed on that ring.
*
* This field must be valid on the first BD of a packet.
*/
uint32_t opaque;
- uint64_t unused1;
+ uint32_t unused1_lo;
+ uint32_t unused1_hi;
/*
* All bits in this field must be valid on the first BD of a packet.
* Their value on other BDs of the packet is ignored.
*/
uint16_t lflags;
/*
* If set to 1, the controller replaces the TCP/UPD checksum
* fields of normal TCP/UPD checksum, or the inner TCP/UDP
* checksum field of the encapsulated TCP/UDP packets with the
* hardware calculated TCP/UDP checksum for the packet associated
* with this descriptor. The flag is ignored if the LSO flag is set.
*/
#define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
/*
* If set to 1, the controller replaces the IP checksum of the
* normal packets, or the inner IP checksum of the encapsulated
* packets with the hardware calculated IP checksum for the
* packet associated with this descriptor.
*/
#define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
/*
* If set to 1, the controller will not append an Ethernet CRC
* to the end of the frame.
*
* Packet must be 64B or longer when this flag is set. It is not
* useful to use this bit with any form of TX offload such as
* CSO or LSO. The intent is that the packet from the host already
* has a valid Ethernet CRC on the packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
/*
* If set to 1, the device will record the time at which the packet
* was actually transmitted at the TX MAC for 2-step time sync. This
* bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
/*
* If set to 1, the controller replaces the tunnel IP checksum
* field with hardware calculated IP checksum for the IP header
* of the packet associated with this descriptor. The hardware
* updates an outer UDP checksum if it is non-zero.
*/
#define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
/*
* This bit must be 0 for BDs of this type. LSO is not supported with
* inline BDs.
*/
#define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
/* Since LSO is not supported with inline BDs, this bit is not used. */
#define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
/* Since LSO is not supported with inline BDs, this bit is not used. */
#define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
/*
* If set to '1', then the RoCE ICRC will be appended to the
* packet. Packet must be a valid RoCE format packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
/*
* If set to '1', then the FCoE CRC will be appended to the
* packet. Packet must be a valid FCoE format packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
/*
* If set to '1', then the timestamp from the BD is used. If cleared
* to 0, then TWE provides the timestamp.
*/
/*
* The BD timestamp feature cannot be enabled concurrently with
* cryptography (KTLS), thus lflags.bd_ts_en and lflags.crypto_en
* shall never both be set in a BD.
*/
#define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
/*
* If set to '1', this operation will cause a trace capture in each
* block it passes through.
*/
#define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
/*
* If set to '1', the device will record the time at which the packet
* was actually transmitted at the TX MAC for 1-step time sync. This
* bit must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
/*
* If set to '1', the controller replaces the Outer-tunnel IP checksum
* field with hardware calculated IP checksum for the IP header of the
* packet associated with this descriptor. For outer UDP checksum, it
* will be the following behavior for all cases independent of settings
* of inner LSO and checksum offload BD flags. If outer UDP checksum
* is 0, then do not update it. If outer UDP checksum is non zero, then
* the hardware should compute and update it.
*/
#define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
/*
* If set to zero when LSO is '1', then the IPID of the Outer-tunnel IP
* header will not be modified during LSO operations. If set to one
* when LSO is '1', then the IPID of the Outer-tunnel IP header will be
* incremented for each subsequent segment of an LSO operation. The
* flag is ignored if the LSO packet is a normal (non-tunneled) TCP
* packet.
*/
#define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
/*
* If set to '1', When set to 1, KTLS encryption will be enabled for
* the packet.
*/
/*
* The BD timestamp feature cannot be enabled concurrently with
* cryptography (KTLS), thus lflags.bd_ts_en and lflags.crypto_en
* shall never both be set in a BD.
*/
#define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
uint8_t unused2;
uint8_t kid_or_ts_low;
#define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
/*
* If lflags.bd_ts_en is 1, this is the lower 7 bits of the 24-bit
* timestamp. If lflags.crypto_en is 1, this is the lower 7 bits of
* the 20-bit KID.
*/
/*
* The KID value of all-ones is reserved for non-KTLS packets, which
* only implies that this value must not be used when filling this
* field for crypto packets.
*/
#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_SFT 1
uint32_t kid_or_ts_high;
#define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
#define TX_BD_LONG_INLINE_UNUSED_SFT 0
/*
* If lflags.bd_ts_en is 1, this is the upper 17 bits of the 24-bit
* timestamp. If lflags.crypto_en is 1, the least significant 13 bits
* of this field contain the upper 13 bits of the 20-bit KID.
*/
/*
* The KID value of all-ones is reserved for non-KTLS packets, which
* only implies that this value must not be used when filling this
* field for crypto packets.
*/
#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_SFT 15
/*
* This value selects bits 25:16 of the CFA action to perform on the
* packet. See the cfa_action field for more information.
*/
uint16_t cfa_action_high;
#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
/*
* This value selects a CFA action to perform on the packet.
* Set this value to zero if no CFA action is desired.
*
* This value must be valid on the first BD of a packet.
*/
uint16_t cfa_action;
/*
* This value is action meta-data that defines CFA edit operations
* that are done in addition to any action editing.
*/
uint32_t cfa_meta;
/* When key = 1, this is the VLAN tag VID value. */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
/* When key = 1, this is the VLAN tag DE value. */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
/* When key = 1, this is the VLAN tag PRI value. */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13
/* When key = 1, this is the VLAN tag TPID select value. */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16
/* 0x88a8 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
/* 0x8100 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
/* 0x9100 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
/* 0x9200 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
/* 0x9300 */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
/* Value programmed in CFA VLANTPID register. */
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG
#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19
/*
* This field identifies the type of edit to be performed
* on the packet.
*
* This value must be valid on the first BD of a packet.
*/
#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK UINT32_C(0xf0000000)
#define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28
/* No editing */
#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
/*
* - meta[17:16] - TPID select value (0 = 0x8100).
* - meta[15:12] - PRI/DE value.
* - meta[11:0] - VID value.
*/
#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
/*
* Provide metadata
* - Wh+/SR - this option is not supported.
* - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
* is set in the Lookup Table.
- * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if
+ * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
* en_bd_meta is set in the Lookup Table.
*/
#define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
#define TX_BD_LONG_INLINE_CFA_META_KEY_LAST TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER
} tx_bd_long_inline_t, *ptx_bd_long_inline_t;
/* tx_bd_empty (size:128b/16B) */
typedef struct tx_bd_empty {
/* This value identifies the type of buffer descriptor. */
uint8_t type;
#define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_EMPTY_TYPE_SFT 0
/*
* Indicates that this BD is 1BB long and is an empty
* TX BD. Not valid for use by the driver.
*/
#define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
#define TX_BD_EMPTY_TYPE_LAST TX_BD_EMPTY_TYPE_TX_BD_EMPTY
uint8_t unused_1[3];
uint8_t unused_2;
uint8_t unused_3[3];
uint8_t unused_4[8];
} tx_bd_empty_t, *ptx_bd_empty_t;
/* tx_bd_mp_cmd (size:128b/16B) */
typedef struct tx_bd_mp_cmd {
/* Unless otherwise stated, sub-fields of this field are always valid. */
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_MP_CMD_TYPE_SFT 0
/*
* Indicates that this BD is used to issue a command to one of
* the mid-path destinations.
*/
#define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
#define TX_BD_MP_CMD_TYPE_LAST TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD
#define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
#define TX_BD_MP_CMD_FLAGS_SFT 6
/* */
#define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
#define TX_BD_MP_CMD_FLAGS_UNUSED_SFT 6
/*
* This value indicates the number of 16B BD locations (slots)
* consumed in the ring by this mid-path command BD, including the
* BD header and the command field.
*/
#define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_MP_CMD_FLAGS_BD_CNT_SFT 8
/*
* This value defines the length of command field in bytes. The maximum
* value shall be 496.
*/
/*
* Note that a fatal error will be generated if the value of this field
* does not correspond with the value of flags.bd_cnt. For example, if
* this field carries a value of 20, then bd_cnt must equal 3.
*/
uint16_t len;
/*
* The opaque data field is pass through to the completion and can be
* used for any data that the driver wants to associate with this
* Tx mid-path command.
*/
uint32_t opaque;
- uint64_t unused1;
+ uint32_t unused1_lo;
+ uint32_t unused1_hi;
} tx_bd_mp_cmd_t, *ptx_bd_mp_cmd_t;
/* tx_bd_presync_cmd (size:128b/16B) */
typedef struct tx_bd_presync_cmd {
/* Unless otherwise stated, sub-fields of this field are always valid. */
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
#define TX_BD_PRESYNC_CMD_TYPE_SFT 0
/*
* Indicates that this BD is used to issue a cryptographic pre-
* sync command through the fast path and destined for TCE.
*/
#define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
#define TX_BD_PRESYNC_CMD_TYPE_LAST TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD
#define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
#define TX_BD_PRESYNC_CMD_FLAGS_SFT 6
/* */
#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_SFT 6
/*
* This value indicates the number of 16B BD locations (slots)
* consumed in the ring by this pre-sync command BD, including the
* BD header and the command field.
*/
#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_SFT 8
/*
* This value defines the length of command field in bytes. The maximum
* value shall be 496.
*/
/*
* Note that a fatal error will be generated if the value of this field
* does not correspond with the value of flags.bd_cnt. For example, if
* this field carries a value of 20, then bd_cnt must equal 3.
*/
uint16_t len;
/*
* The opaque data field is pass through to TCE and can be used for
* debug.
*/
uint32_t opaque;
/*
* This field is the Crypto Context ID to which the retransmit packet is
* applied. The KID references the context fields used by the
* associated kTLS offloaded connection.
*/
uint32_t kid;
/*
* The KID value of all-ones is reserved for non-KTLS packets, which
* only implies that this value must not be used when filling this
* field for crypto packets.
*/
#define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
#define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
uint32_t unused_1;
} tx_bd_presync_cmd_t, *ptx_bd_presync_cmd_t;
+/*
+ * This structure is used to send additional information for transmitting
+ * packets using timed transmit scheduling. It must only to be applied as
+ * the second BD of a BD chain that represents a packet. Any subsequent
+ * BDs will follow the timed transmit BD.
+ */
+/* tx_bd_timedtx (size:128b/16B) */
+
+typedef struct tx_bd_timedtx {
+ uint16_t flags_type;
+ /* This value identifies the type of buffer descriptor. */
+ #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f)
+ #define TX_BD_TIMEDTX_TYPE_SFT 0
+ /*
+ * Indicates a timed transmit BD. This is a 16b BD that is inserted
+ * into a packet BD chain immediately after the first BD. It is used
+ * to control the flow in a timed transmit operation.
+ */
+ #define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
+ #define TX_BD_TIMEDTX_TYPE_LAST TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX
+ /* Unless otherwise stated, sub-fields of this field are always valid. */
+ #define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0)
+ #define TX_BD_TIMEDTX_FLAGS_SFT 6
+ /*
+ * This value identifies the kind of buffer timed transmit mode that
+ * is to be enabled for the packet.
+ */
+ #define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0)
+ #define TX_BD_TIMEDTX_FLAGS_KIND_SFT 6
+ /*
+ * This timed transmit mode indicates that the packet will be
+ * scheduled and send immediately (or as soon as possible), once
+ * it is scheduled in the transmitter.
+ * Note: This mode is similar to regular (non-timed transmit)
+ * operation. Its main purpose is to cancel pace mode timed
+ * transmit.
+ */
+ #define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6)
+ /*
+ * This timed transmit mode is used to schedule transmission of
+ * the packet no earlier than the time given in the tx_time
+ * field of the BD.
+ * Note: In case subsequent packets don't include a timed transmit
+ * BD, they will be scheduled subsequently for transmission
+ * without any timed transmit constraint.
+ */
+ #define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6)
+ /*
+ * This timed transmit mode is used to enable rate control for the
+ * flow (QP) at a rate as defined by the rate field of this BD.
+ * Note: In case subsequent, adjacent packets on the same flow
+ * don't include a timed transmit BD, they will continue to be
+ * paced by the transmitter at the same rate as given in this BD.
+ */
+ #define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6)
+ #define TX_BD_TIMEDTX_FLAGS_KIND_LAST TX_BD_TIMEDTX_FLAGS_KIND_PACE
+ /*
+ * This field exists in all Tx BDs. It doesn't apply to this particular
+ * BD type since the BD never represents an SGL or inline data; i.e. it
+ * is only a command. This field must be zero.
+ */
+ /*
+ * Note that if this field is not zero, a fatal length error will be
+ * generated as it will be included in the aggregate of SGE lengths for
+ * the packet.
+ */
+ uint16_t len;
+ /*
+ * This field represents the rate of the flow (QP) in terms of KB/s.
+ * This applies to pace mode timed transmit.
+ */
+ uint32_t rate;
+ /*
+ * Applying this rate to a QP will result in this and all subsequent
+ * packets of the flow being paced at the given rate, until such time
+ * that the timed transmit mode is either changed or the rate is
+ * updated in a future packet on the flow.
+ * This field is applicable only if flags.kind is pace.
+ */
+ #define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff)
+ #define TX_BD_TIMEDTX_RATE_VAL_SFT 0
+ /*
+ * This field represents the nano-second time to transmit the
+ * corresponding packet using SO_TXTIME mode of timed transmit.
+ * This field is applicable only if flags.kind is so_txtime.
+ */
+ uint32_t tx_time_lo;
+ uint32_t tx_time_hi;
+} tx_bd_timedtx_t, *ptx_bd_timedtx_t;
+
/* rx_prod_pkt_bd (size:128b/16B) */
typedef struct rx_prod_pkt_bd {
/* This value identifies the type of buffer descriptor. */
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
#define RX_PROD_PKT_BD_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is an RX Producer
* (i.e. empty) buffer descriptor.
*/
#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
#define RX_PROD_PKT_BD_TYPE_LAST RX_PROD_PKT_BD_TYPE_RX_PROD_PKT
#define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
#define RX_PROD_PKT_BD_FLAGS_SFT 6
/*
* If set to 1, the packet will be placed at the address plus
* 2B. The 2 Bytes of padding will be written as zero.
*/
/*
* This is intended to be used when the host buffer is
* cache-line aligned to produce packets that are easy to
* parse in host memory while still allowing writes to be cache
* line aligned.
*/
#define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
/*
* If set to 1, the packet write will be padded out to the
* nearest cache-line with zero value padding.
*/
/*
* If receive buffers start/end on cache-line boundaries, this
* feature will ensure that all data writes on the PCI bus
* start/end on cache line boundaries.
*/
#define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
/*
* This field has been deprecated. There can be no additional
* BDs for this packet from this ring.
*
* Old definition:
* This value is the number of additional buffers in the ring that
* describe the buffer space to be consumed for this packet.
* If the value is zero, then the packet must fit within the
* space described by this BD. If this value is 1 or more, it
* indicates how many additional "buffer" BDs are in the ring
* immediately following this BD to be used for the same
* network packet. Even if the packet to be placed does not need
* all the additional buffers, they will be consumed anyway.
*/
#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
#define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
/*
* This is the length in Bytes of the host physical buffer where
* data for the packet may be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provided end on a host cache line.
*/
uint16_t len;
/*
* The opaque data field is pass through to the completion and can be
* used for any data that the driver wants to associate with this
* receive buffer set.
*/
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
* be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provide start on a host cache line.
*/
uint64_t addr;
} rx_prod_pkt_bd_t, *prx_prod_pkt_bd_t;
/* rx_prod_bfr_bd (size:128b/16B) */
typedef struct rx_prod_bfr_bd {
/* This value identifies the type of buffer descriptor. */
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
#define RX_PROD_BFR_BD_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is an RX
* Producer Buffer BD.
*/
#define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
#define RX_PROD_BFR_BD_TYPE_LAST RX_PROD_BFR_BD_TYPE_RX_PROD_BFR
#define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
#define RX_PROD_BFR_BD_FLAGS_SFT 6
/*
* This is the length in Bytes of the host physical buffer where
* data for the packet may be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provided end on a host cache line.
*/
uint16_t len;
/* This field is not used. */
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
* be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provide start on a host cache line.
*/
- uint64_t addr;
+ uint32_t addr_lo;
+ uint32_t addr_hi;
} rx_prod_bfr_bd_t, *prx_prod_bfr_bd_t;
/* rx_prod_agg_bd (size:128b/16B) */
typedef struct rx_prod_agg_bd {
/* This value identifies the type of buffer descriptor. */
uint16_t flags_type;
/* This value identifies the type of buffer descriptor. */
#define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
#define RX_PROD_AGG_BD_TYPE_SFT 0
/*
* Indicates that this BD is 16B long and is an
* RX Producer Assembly Buffer Descriptor.
*/
#define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
#define RX_PROD_AGG_BD_TYPE_LAST RX_PROD_AGG_BD_TYPE_RX_PROD_AGG
#define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
#define RX_PROD_AGG_BD_FLAGS_SFT 6
/*
* If set to 1, the packet write will be padded out to the
* nearest cache-line with zero value padding.
*/
/*
* If receive buffers start/end on cache-line boundaries, this
* feature will ensure that all data writes on the PCI bus
* end on cache line boundaries.
*/
#define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
/*
* This is the length in Bytes of the host physical buffer where
* data for the packet may be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provided end on a host cache line.
*/
uint16_t len;
/*
* The opaque data field is pass through to the completion and can be
* used for any data that the driver wants to associate with this
* receive assembly buffer.
*/
uint32_t opaque;
/*
* This is the host physical address where data for the packet may
* be placed in host memory.
*/
/*
* While this is a Byte resolution value, it is often advantageous
* to ensure that the buffers provide start on a host cache line.
*/
- uint64_t addr;
+ uint32_t addr_lo;
+ uint32_t addr_hi;
} rx_prod_agg_bd_t, *prx_prod_agg_bd_t;
/* cfa_cmpls_cmp_data_msg (size:128b/16B) */
typedef struct cfa_cmpls_cmp_data_msg {
uint32_t mp_client_dma_length_opcode_status_type;
/*
* This field represents the Mid-Path client that generated the
* completion.
*/
/*
* This field indicates the exact type of the completion. By
* convention, the LSB identifies the length of the record in 16B
* units. Even values indicate 16B records. Odd values indicate 32B
* records.
*/
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
/* Mid Path Short Completion with length = 16B. */
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define CFA_CMPLS_CMP_DATA_MSG_TYPE_LAST CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
/* This value indicates the status for the command. */
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SFT 6
/* Completed without error. */
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK (UINT32_C(0x0) << 6)
/* Indicates an unsupported CFA opcode in the command. */
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR (UINT32_C(0x1) << 6)
/*
* Indicates a CFA command formatting error. This error can occur on
* any of the supported CFA commands.
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR (UINT32_C(0x2) << 6)
/*
* Indicates an SVIF-Table scope error. This error can occur on any
* of the supported CFA commands.
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR (UINT32_C(0x3) << 6)
/*
* Indicates that the table_index is either outside of the
* table_scope range set by its EM_SIZE or, for EM Insert, it is in
* the static bucket range. This error can occur on EM Insert
* commands. It can also occur on Read, Read Clear, Write, and
* Invalidate commands if the table_type is EM.
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR (UINT32_C(0x4) << 6)
/*
* Cache operation responded with an error. This error can occur on
* Read, Read Clear, Write, EM Insert, and EM Delete commands.
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR (UINT32_C(0x5) << 6)
/*
* Indicates failure on EM Insert or EM Delete Command. Hash index
* and hash msb are returned in table_index and hash_msb fields.
* Dma_length is set to 1 if the bucket is also returned (as dma
* data).
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL (UINT32_C(0x6) << 6)
/*
* Indicates no notifications were available on an Event Collection
* command.
*/
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL (UINT32_C(0x7) << 6)
#define CFA_CMPLS_CMP_DATA_MSG_STATUS_LAST CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 10
/* This is the opcode from the command. */
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK UINT32_C(0xff000)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_SFT 12
/*
* This is read command. From 32 to 128B can be read from a table
* using this command.
*/
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ (UINT32_C(0x0) << 12)
/*
* This is write command. From 32 to 128B can be written to a table
* using this command.
*/
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE (UINT32_C(0x1) << 12)
/*
* This is read-clear command. 32B can be read from a table and a 16b
* mask can be used to clear specific 16b units after the read as an
* atomic operation.
*/
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR (UINT32_C(0x2) << 12)
/*
* An exact match table insert will be attempted into the table. If
* there is a free location in the bucket, the payload will be
* written to the bucket.
*/
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT (UINT32_C(0x3) << 12)
/* An exact match table delete will be attempted. */
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE (UINT32_C(0x4) << 12)
/*
* The specified table area will be invalidated. If it is needed
* again, it will be read from the backing store.
*/
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE (UINT32_C(0x5) << 12)
/* Reads notification messages from the Host Notification Queue. */
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT (UINT32_C(0x6) << 12)
#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_LAST CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT
/*
* This field indicates the length of the DMA that accompanies the
* completion. Specified in units of DWords (32b). Valid values are
* between 0 and 128. A value of zero indicates that there is no DMA
* that accompanies the completion.
*/
#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK UINT32_C(0xff00000)
#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_SFT 20
/*
* This field represents the Mid-Path client that generated the
* completion.
*/
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf0000000)
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 28
/* TX configurable flow processing block. */
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA (UINT32_C(0x2) << 28)
/* RX configurable flow processing block. */
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA (UINT32_C(0x3) << 28)
#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA
/*
* This is a copy of the opaque field from the mid path BD of this
* command.
*/
uint32_t opaque;
uint16_t hash_msb_v;
/*
* This value is written by the NIC such that it will be different for
* each pass through the completion queue. The even passes will
* write 1. The odd passes will write 0.
*/
#define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 1
/*
* This is the upper 12b of the hash, returned on Exact Match
* Insertion/Deletion Commands.
*/
#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_SFT 4
/* This is the table type from the command. */
uint8_t table_type;
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_SFT 4
/* This command acts on the action table of the specified scope. */
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
/* This command acts on the exact match table of the specified scope. */
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_LAST CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM
uint8_t table_scope;
/* This is the table scope from the command. */
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
uint32_t table_index;
/*
* This is the table index from the command (if it exists). However, if
* an Exact Match Insertion/Deletion command failed, then this is the
* table index of the calculated static hash bucket.
*/
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
} cfa_cmpls_cmp_data_msg_t, *pcfa_cmpls_cmp_data_msg_t;
/* CFA Mid-Path 32B DMA Message */
/* cfa_dma32b_data_msg (size:256b/32B) */
typedef struct cfa_dma32b_data_msg {
/* DMA data value. */
uint32_t dta[8];
} cfa_dma32b_data_msg_t, *pcfa_dma32b_data_msg_t;
/* CFA Mid-Path 64B DMA Message */
/* cfa_dma64b_data_msg (size:512b/64B) */
typedef struct cfa_dma64b_data_msg {
/* DMA data value. */
uint32_t dta[16];
} cfa_dma64b_data_msg_t, *pcfa_dma64b_data_msg_t;
/* CFA Mid-Path 96B DMA Message */
/* cfa_dma96b_data_msg (size:768b/96B) */
typedef struct cfa_dma96b_data_msg {
/* DMA data value. */
uint32_t dta[24];
} cfa_dma96b_data_msg_t, *pcfa_dma96b_data_msg_t;
/* CFA Mid-Path 128B DMA Message */
/* cfa_dma128b_data_msg (size:1024b/128B) */
typedef struct cfa_dma128b_data_msg {
/* DMA data value. */
uint32_t dta[32];
} cfa_dma128b_data_msg_t, *pcfa_dma128b_data_msg_t;
/* ce_cmpls_cmp_data_msg (size:128b/16B) */
typedef struct ce_cmpls_cmp_data_msg {
uint16_t client_subtype_type;
/*
* This field indicates the exact type of the completion. By
* convention, the LSB identifies the length of the record in 16B
* units. Even values indicate 16B records. Odd values indicate 32B
* records.
*/
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
/* Completion of a Mid Path Command. Length = 16B */
#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
#define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT
#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6
/*
* This value indicates the CE sub-type operation that is being
* completed.
*/
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8
/* Completion Response for a Solicited Command. */
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)
/* Error Completion (Unsolicited). */
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)
/* Re-Sync Completion (Unsolicited) */
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)
#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC
/*
* This field represents the Mid-Path client that generated the
* completion.
*/
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12
/* TX crypto engine block. */
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE (UINT32_C(0x0) << 12)
/* RX crypto engine block. */
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE (UINT32_C(0x1) << 12)
#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE
uint16_t status;
/* This value indicates the status for the command. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0
/* Completed without error. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)
/* CFCK load error. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)
/* FID check error. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)
/* Context kind / MP version mismatch error. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)
/* Unsupported Destination Connection ID Length. */
#define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)
/*
* Invalid MP Command [anything other than ADD or DELETE
* triggers this for QUIC].
*/
#define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)
#define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR
#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4
/*
* This is a copy of the opaque field from the mid path BD of this
* command.
*/
uint32_t opaque;
uint32_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes will
* write 1. The odd passes will write 0.
*/
#define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1
uint32_t kid;
/*
* This field is the Crypto Context ID. The KID is used to store
* information used by the associated kTLS offloaded connection.
*/
#define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)
#define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0
#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20
} ce_cmpls_cmp_data_msg_t, *pce_cmpls_cmp_data_msg_t;
/* cmpl_base (size:128b/16B) */
typedef struct cmpl_base {
uint16_t type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
* record in 16B units. Even values indicate 16B
* records. Odd values indicate 32B
* records.
*/
#define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
* Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
* NO-OP completion:
* Completion of NO-OP. Length = 16B
*/
#define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
/*
* TX L2 coalesced completion:
* Completion of coalesced TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
/*
* TX L2 Packet Timestamp completion:
* Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
/*
* RX L2 TPA Start V2 Completion:
* Completion of and L2 RX packet. Length = 32B
* This is the new version of the RX_TPA_START completion used
* in SR2 and later chips.
*/
#define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
/*
* RX L2 V2 completion:
* Completion of and L2 RX packet. Length = 32B
* This is the new version of the RX_L2 completion used in SR2
* and later chips.
*/
#define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
/*
* RX L2 completion:
* This is the compressed version of Rx Completion for performance
* applications. Length = 16B
*/
#define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
/*
* RX L2 completion:
* Completion of and L2 RX packet. Length = 32B
*/
#define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
/*
* RX Aggregation Buffer completion:
* Completion of an L2 aggregation buffer in support of
* TPA, HDS, or Jumbo packet completion. Length = 16B
*/
#define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
/*
* RX L2 TPA Start Completion:
* Completion at the beginning of a TPA operation.
* Length = 32B
*/
#define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
/*
* RX L2 TPA End Completion:
* Completion at the end of a TPA operation.
* Length = 32B
*/
#define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
/*
* RX TPA Aggregation Buffer Completion:
* Completion of an L2 aggregation buffer in support of TPA packet
* completion.
* Length = 16B
*/
#define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16)
/*
* RX L2 completion: Completion of and L2 RX packet.
* Length = 32B
*/
#define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17)
/*
* RX L2 TPA Start completion: Completion at the beginning of a TPA
* operation.
* Length = 32B
*/
#define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
#define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
/*
* VEE Flush Completion:
* This completion is inserted manually by
* the Primate and processed by the VEE hardware to ensure that
* all completions on a VEE function have been processed by the
* VEE hardware before FLR process is completed.
*/
#define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
/*
* Mid Path Short Completion :
* Completion of a Mid Path Command. Length = 16B
*/
#define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
/*
* Mid Path Long Completion :
* Completion of a Mid Path Command. Length = 32B
*/
#define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
/*
* HWRM Command Completion:
* Completion of an HWRM command.
*/
#define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
/* Forwarded HWRM Request */
#define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
/* Forwarded HWRM Response */
#define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
/* HWRM Asynchronous Event Information */
#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
/* CQ Notification */
#define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
/* SRQ Threshold Event */
#define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
/* DBQ Threshold Event */
#define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
/* QP Async Notification */
#define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
/* Function Async Notification */
#define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
#define CMPL_BASE_TYPE_LAST CMPL_BASE_TYPE_FUNC_EVENT
/* info1 is 16 b */
uint16_t info1;
/* info2 is 32 b */
uint32_t info2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
uint32_t info3_v;
#define CMPL_BASE_V UINT32_C(0x1)
#define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
#define CMPL_BASE_INFO3_SFT 1
/* info4 is 32 b */
uint32_t info4;
} cmpl_base_t, *pcmpl_base_t;
/* tx_cmpl (size:128b/16B) */
typedef struct tx_cmpl {
uint16_t flags_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
* record in 16B units. Even values indicate 16B
* records. Odd values indicate 32B
* records.
*/
#define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
* Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
#define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define TX_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
* error of some type. Type of error is indicated in
* error_flags.
*/
#define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet completed
* was transmitted using the push acceleration data provided
* by the driver. When this bit is '0', it indicates that the
* packet had not push acceleration data written or was executed
* as a normal packet even though push data was provided.
*/
#define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
/* unused1 is 16 b */
uint16_t unused_0;
/*
* This is a copy of the opaque field from the first TX BD of this
* transmitted packet. Note that, if the packet was described by a short
* CSO or short CSO inline BD, then the 16-bit opaque field from the
* short CSO BD will appear in the bottom 16 bits of this field.
*/
uint32_t opaque;
uint16_t errors_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
#define TX_CMPL_V UINT32_C(0x1)
#define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
#define TX_CMPL_ERRORS_SFT 1
/*
* This error indicates that there was some sort of problem
* with the BDs for the packet.
*/
#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
/* No error */
#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
/*
* Bad Format:
* BDs were not formatted correctly.
*/
#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define TX_CMPL_ERRORS_BUFFER_ERROR_LAST TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
/*
* When this bit is '1', it indicates that the length of
* the packet was zero. No packet was transmitted.
*/
#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
/*
* When this bit is '1', it indicates that the packet
* was longer than the programmed limit in TDI. No
* packet was transmitted.
*/
#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
/*
* When this bit is '1', it indicates that one or more of the
* BDs associated with this packet generated a PCI error.
* This probably means the address was not valid.
*/
#define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet was longer
* than indicated by the hint. No packet was transmitted.
*/
#define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
/*
* When this bit is '1', it indicates that the packet was
* dropped due to Poison TLP error on one or more of the
* TLPs in the PXP completion.
*/
#define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
/*
* When this bit is '1', it indicates that the packet was dropped
* due to a transient internal error in TDC. The packet or LSO can
* be retried and may transmit successfully on a subsequent attempt.
*/
#define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
/*
* When this bit is '1', it was not possible to collect a timestamp
* for a PTP completion, in which case the timestamp_hi and
* timestamp_lo fields are invalid. When this bit is '0' for a PTP
* completion, the timestamp_hi and timestamp_lo fields are valid.
* RJRN will copy the value of this bit into the field of the same
* name in all TX completions, regardless of whether such completions
* are PTP completions or other TX completions.
*/
#define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
/* unused2 is 16 b */
uint16_t unused_1;
/* unused3 is 32 b */
uint32_t unused_2;
} tx_cmpl_t, *ptx_cmpl_t;
/* tx_cmpl_coal (size:128b/16B) */
typedef struct tx_cmpl_coal {
uint16_t flags_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
* record in 16B units. Even values indicate 16B
* records. Odd values indicate 32B
* records.
*/
#define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
#define TX_CMPL_COAL_TYPE_SFT 0
/*
* TX L2 coalesced completion:
* Completion of TX packet. Length = 16B
*/
#define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
#define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL
#define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
#define TX_CMPL_COAL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
* error of some type. Type of error is indicated in
* error_flags.
*/
#define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet completed
* was transmitted using the push acceleration data provided
* by the driver. When this bit is '0', it indicates that the
* packet had not push acceleration data written or was executed
* as a normal packet even though push data was provided.
*/
#define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
/* unused1 is 16 b */
uint16_t unused_0;
/*
* This is a copy of the opaque field from the first TX BD of the packet
* which corresponds with the reported sq_cons_idx. Note that, with
* coalesced completions, completions are generated for only some of the
* packets. The driver will see the opaque field for only those packets.
* Note that, if the packet was described by a short CSO or short CSO
* inline BD, then the 16-bit opaque field from the short CSO BD will
* appear in the bottom 16 bits of this field. For TX rings with
* completion coalescing enabled (which would use the coalesced
* completion record), it is suggested that the driver populate the
* opaque field to indicate the specific TX ring with which the
* completion is associated, then utilize the opaque and sq_cons_idx
* fields in the coalesced completion record to determine the specific
* packets that are to be completed on that ring.
*/
uint32_t opaque;
uint16_t errors_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
#define TX_CMPL_COAL_V UINT32_C(0x1)
#define TX_CMPL_COAL_ERRORS_MASK UINT32_C(0xfffe)
#define TX_CMPL_COAL_ERRORS_SFT 1
/*
* This error indicates that there was some sort of problem
* with the BDs for the packet.
*/
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1
/* No error */
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
/*
* Bad Format:
* BDs were not formatted correctly.
*/
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT
/*
* When this bit is '1', it indicates that the length of
* the packet was zero. No packet was transmitted.
*/
#define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
/*
* When this bit is '1', it indicates that the packet
* was longer than the programmed limit in TDI. No
* packet was transmitted.
*/
#define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
/*
* When this bit is '1', it indicates that one or more of the
* BDs associated with this packet generated a PCI error.
* This probably means the address was not valid.
*/
#define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
/*
* When this bit is '1', it indicates that the packet was longer
* than indicated by the hint. No packet was transmitted.
*/
#define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
/*
* When this bit is '1', it indicates that the packet was
* dropped due to Poison TLP error on one or more of the
* TLPs in the PXP completion.
*/
#define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
/*
* When this bit is '1', it indicates that the packet was dropped
* due to a transient internal error in TDC. The packet or LSO can
* be retried and may transmit successfully on a subsequent attempt.
*/
#define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
/*
* When this bit is '1', it was not possible to collect a a timestamp
* for a PTP completion, in which case the timestamp_hi and
* timestamp_lo fields are invalid. When this bit is '0' for a PTP
* completion, the timestamp_hi and timestamp_lo fields are valid.
* RJRN will copy the value of this bit into the field of the same
* name in all TX completions, regardless of whether such
* completions are PTP completions or other TX completions.
*/
#define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
/* unused2 is 16 b */
uint16_t unused_1;
uint32_t sq_cons_idx;
/*
* This value is SQ index for the start of the packet following the
* last completed packet.
*/
#define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
} tx_cmpl_coal_t, *ptx_cmpl_coal_t;
/* tx_cmpl_packet_timestamp (size:128b/16B) */
typedef struct tx_cmpl_packet_timestamp {
uint16_t ts_sub_ns_flags_type;
/*
* This field indicates the exact type of the completion. By
* convention, the LSB identifies the length of the record in 16B
* units. Even values indicate 16B records. Odd values indicate
* 32B records.
*/
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0
/*
* TX L2 Packet Timestamp completion:
* Completion of an L2 Packet Timestamp Packet. Length = 16B
*/
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
#define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an error
* of some type. Type of error is indicated in error_flags.
*/
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)
/*
* This field indicates the TX packet timestamp type that is
* represented by a TX Packet Timestamp Completion. Note that
* this field is invalid if the timestamp_invalid_error flag
* is set.
*/
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)
/* The packet timestamp came from PM. */
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM (UINT32_C(0x0) << 7)
/* The packet timestamp came from PA. */
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA (UINT32_C(0x1) << 7)
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA
/*
* This flag indicates that the timestamp should have come from PM,
* but came instead from PA because all PM timestamp resources were
* in use. This can occur in the following circumstances:
* 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet
* but PA could not request a PM timestamp
* 2. The BD specified ts_2cmpl_pm, but PA could not request a PM
* timestamp
*/
#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)
/*
* For 2-step PTP timestamps, bits[3:0] of this field represent the
* sub-nanosecond portion of the packet timestamp, returned from PM
* for 2-step PTP timestamps. For PA timestamps, this field also
* represents the sub-nanosecond portion of the packet timestamp;
* however, due to synchronization uncertainties, the accuracy of
* PA timestamps is limited to approximately +/- 4 ns. Therefore
* this field is of dubious value for PA timestamps.
*/
#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)
#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12
/*
* This is bits [47:32] of the nanoseconds portion of the packet
* timestamp, returned from PM for 2-step PTP timestamps or from
* PA for PA timestamps. This field is in units of 2^32 ns.
*/
uint16_t ts_ns_mid;
/*
* This is a copy of the opaque field from the first TX BD of this
* transmitted packet. Note that, if the packet was described by a
* short CSO or short CSO inline BD, then the 16-bit opaque field
* from the short CSO BD will appear in the bottom 16 bits of this
* field.
*/
uint32_t opaque;
uint16_t errors_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
#define TX_CMPL_PACKET_TIMESTAMP_V UINT32_C(0x1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK UINT32_C(0xfffe)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1
/*
* This field was previously used to indicate fatal errors, which
* now result in aborting and bringing down the ring. This field
* is deprecated.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1
/* No error. */
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
/* Deprecated. */
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT
/*
* This error is fatal and results in aborting and bringing down the
* ring, thus is deprecated.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
/*
* This error is fatal and results in aborting and bringing down the
* ring, thus is deprecated.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
/*
* When this bit is '1', it indicates that one or more of the BDs
* associated with this packet generated a PCI error when accessing
* header/payload data from host memory. It most likely indicates
* that the address was not valid. Note that this bit has no meaning
* for the timestamp completion and will always be '0'.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR UINT32_C(0x40)
/*
* This error is fatal and results in aborting and bringing down the
* ring, thus is deprecated.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
/*
* When this bit is '1', it indicates that the packet was dropped
* due to Poison TLP error on one or more of the TLPs in one or more
* of the associated PXP completion(s) when accessing header/payload
* data from host memory. Note that this bit has no meaning for the
* timestamp completion, and will always be '0'.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
/*
* When this bit is '1', it indicates that the packet was dropped
* due to a transient internal error in TDC. The packet or LSO can
* be retried and may transmit successfully on a subsequent attempt.
* Note that this bit has no meaning for the timestamp completion
* and will always be '0'.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
/*
* When this bit is '1', it was not possible to collect a timestamp
* for a timestamp completion, in which case the ts_ns and ts_sub_ns
* fields are invalid. When this bit is '0' in a timestamp
* completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields
* are valid. Note that this bit has meaning only for the timestamp
* completion. For types other than the timestamp completion, this
* bit will always be '0'.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
/*
* When this bit is '1', it indicates that a Timed Transmit
* SO-TXTIME packet violated the max_ttx_overtime constraint i.e.,
* the time the packet was processed for transmission in TWE was
* later than the time given by (TimedTx_BD.tx_time +
* max_ttx_overtime) and as result, the packet was dropped.
* Note that max_ttx_overtime is a global configuration in TWE.
* Note that this bit has no meaning in a timestamp completion,
* and will always be '0'.
*/
#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR UINT32_C(0x800)
/* unused2 is 16 b */
uint16_t unused_2;
/*
* This is bits [31:0] of the nanoseconds portion of the packet
* timestamp, returned from PM for 2-step PTP timestamp or from
* PA for PA timestamps. This field is in units of ns.
*/
uint32_t ts_ns_lo;
} tx_cmpl_packet_timestamp_t, *ptx_cmpl_packet_timestamp_t;
/* rx_pkt_cmpl (size:128b/16B) */
typedef struct rx_pkt_cmpl {
uint16_t flags_type;
/*
* This field indicates the exact type of the completion.
* By convention, the LSB identifies the length of the
* record in 16B units. Even values indicate 16B
* records. Odd values indicate 32B
* records.
*/
#define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
#define RX_PKT_CMPL_TYPE_SFT 0
/*
* RX L2 completion:
* Completion of and L2 RX packet. Length = 32B
*/
#define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
#define RX_PKT_CMPL_TYPE_LAST RX_PKT_CMPL_TYPE_RX_L2
#define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
#define RX_PKT_CMPL_FLAGS_SFT 6
/*
* When this bit is '1', it indicates a packet that has an
* error of some type. Type of error is indicated in
* error_flags.
*/
#define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/* This field indicates how the packet was placed in the buffer. */
#define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
/*
* Normal:
* Packet was placed using normal algorithm.
*/
#define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
/*
* Jumbo:
* Packet was placed using jumbo algorithm.
*/
#define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
/*
* Header/Data Separation:
* Packet was placed using Header/Data separation algorithm.
* The separation location is indicated by the itype field.
*/
#define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
#define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
/* This bit is '1' if the RSS field in this completion is valid. */
#define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
/*
* This bit is '1' if metadata has been added to the end of the
* packet in host memory.
*/
#define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
/*
* This value indicates what the inner packet determined for the
* packet was.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
/*
* Not Known:
* Indicates that the packet type was not known.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
/*
* IP Packet:
* Indicates that the packet was an IP packet, but further
* classification was not possible.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
/*
* TCP Packet:
* Indicates that the packet was IP and TCP.
* This indicates that the payload_offset field is valid.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
/*
* UDP Packet:
* Indicates that the packet was IP and UDP.
* This indicates that the payload_offset field is valid.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
/*
* FCoE Packet:
* Indicates that the packet was recognized as a FCoE.
* This also indicates that the payload_offset field is valid.
*/
#define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)