Index: head/sys/dev/acpica/acpi_pcib_acpi.c
===================================================================
--- head/sys/dev/acpica/acpi_pcib_acpi.c
+++ head/sys/dev/acpica/acpi_pcib_acpi.c
@@ -309,15 +309,19 @@
 		0x96, 0x57, 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66
 	};
 
+	/* Status Field */
+	cap_set[PCI_OSC_STATUS] = 0;
+
 	/* Support Field: Extended PCI Config Space, MSI */
-	cap_set[1] = 0x11;
+	cap_set[PCI_OSC_SUPPORT] = PCIM_OSC_SUPPORT_EXT_PCI_CONF |
+	    PCIM_OSC_SUPPORT_MSI;
 
 	/* Control Field */
-	cap_set[2] = 0;
+	cap_set[PCI_OSC_CTL] = 0;
 
 #ifdef PCI_HP
 	/* Control Field: PCI Express Native Hot Plug */
-	cap_set[2] |= 0x1;
+	cap_set[PCI_OSC_CTL] |= PCIM_OSC_CTL_PCIE_HP;
 #endif
 
 	status = acpi_EvaluateOSC(sc->ap_handle, pci_host_bridge_uuid, 1,
@@ -330,10 +334,16 @@
 		return;
 	}
 
-	if (cap_set[0] != 0) {
+	if (cap_set[PCI_OSC_STATUS] != 0) {
 		device_printf(sc->ap_dev, "_OSC returned error %#x\n",
 		    cap_set[0]);
 	}
+
+#ifdef PCI_HP
+	if ((cap_set[PCI_OSC_CTL] & PCIM_OSC_CTL_PCIE_HP) == 0 && bootverbose) {
+		device_printf(sc->ap_dev, "_OSC didn't allow HP control\n");
+	}
+#endif
 }
 
 static int
Index: head/sys/dev/pci/pcireg.h
===================================================================
--- head/sys/dev/pci/pcireg.h
+++ head/sys/dev/pci/pcireg.h
@@ -1040,3 +1040,19 @@
 #define	PCIR_SRIOV_BARS		0x24
 #define	PCIR_SRIOV_BAR(x)	(PCIR_SRIOV_BARS + (x) * 4)
 
+/*
+ * PCI Express Firmware Interface definitions
+ */
+#define	PCI_OSC_STATUS		0
+#define	PCI_OSC_SUPPORT		1
+#define	PCIM_OSC_SUPPORT_EXT_PCI_CONF	0x01	/* Extended PCI Config Space */
+#define	PCIM_OSC_SUPPORT_ASPM		0x02	/* Active State Power Management */
+#define	PCIM_OSC_SUPPORT_CPMC		0x04	/* Clock Power Management Cap */
+#define	PCIM_OSC_SUPPORT_SEG_GROUP	0x08	/* PCI Segment Groups supported */
+#define	PCIM_OSC_SUPPORT_MSI		0x10	/* MSI signalling supported */
+#define	PCI_OSC_CTL		2
+#define	PCIM_OSC_CTL_PCIE_HP		0x01	/* PCIe Native Hot Plug */
+#define	PCIM_OSC_CTL_SHPC_HP		0x02	/* SHPC Native Hot Plug */
+#define	PCIM_OSC_CTL_PCIE_PME		0x04	/* PCIe Native Power Mgt Events */
+#define	PCIM_OSC_CTL_PCIE_AER		0x08	/* PCIe Advanced Error Reporting */
+#define	PCIM_OSC_CTL_PCIE_CAP_STRUCT	0x10	/* Various Capability Structures */