Index: head/sys/arm/mv/mv_common.c
===================================================================
--- head/sys/arm/mv/mv_common.c
+++ head/sys/arm/mv/mv_common.c
@@ -98,6 +98,7 @@
 static void decode_win_usb3_setup(u_long);
 static void decode_win_eth_setup(u_long);
 static void decode_win_sata_setup(u_long);
+static void decode_win_ahci_setup(u_long);
 
 static void decode_win_idma_setup(u_long);
 static void decode_win_xor_setup(u_long);
@@ -107,6 +108,7 @@
 static void decode_win_eth_dump(u_long base);
 static void decode_win_idma_dump(u_long base);
 static void decode_win_xor_dump(u_long base);
+static void decode_win_sata_dump(u_long base);
 
 static int fdt_get_ranges(const char *, void *, int, int *, int *);
 #ifdef SOC_MV_ARMADA38X
@@ -139,6 +141,7 @@
 	{ "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
 	{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
 	{ "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
+	{ "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_sata_dump },
 	{ "mrvl,sata", &decode_win_sata_setup, NULL },
 	{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
 	{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
@@ -660,6 +663,11 @@
 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
+#if defined(SOC_MV_ARMADA38X)
+WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE);
+WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE);
+#endif
+
 #ifndef SOC_MV_DOVE
 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
@@ -1999,6 +2007,55 @@
 		}
 }
 
+static void
+decode_win_ahci_setup(u_long base)
+{
+	uint32_t br, cr, sz;
+	int i, j;
+
+	for (i = 0; i < MV_WIN_SATA_MAX; i++) {
+		win_sata_cr_write(base, i, 0);
+		win_sata_br_write(base, i, 0);
+		win_sata_sz_write(base, i, 0);
+	}
+
+	for (i = 0; i < MV_WIN_DDR_MAX; i++) {
+		if (ddr_is_active(i)) {
+			cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) |
+			    (ddr_target(i) << IO_WIN_TGT_SHIFT) |
+			    IO_WIN_ENA_MASK;
+			br = ddr_base(i);
+			sz = (ddr_size(i) - 1) &
+			    (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT);
+
+			/* Use first available SATA window */
+			for (j = 0; j < MV_WIN_SATA_MAX; j++) {
+				if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK)
+					continue;
+
+				/* BASE is set to DRAM base (0x00000000) */
+				win_sata_br_write(base, j, br);
+				/* CTRL targets DRAM ctrl with 0x0E or 0x0D */
+				win_sata_cr_write(base, j, cr);
+				/* SIZE is set to 16MB - max value */
+				win_sata_sz_write(base, j, sz);
+				break;
+			}
+		}
+	}
+}
+
+static void
+decode_win_sata_dump(u_long base)
+{
+	int i;
+
+	for (i = 0; i < MV_WIN_SATA_MAX; i++)
+		printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i,
+		    win_sata_cr_read(base, i), win_sata_br_read(base, i),
+		    win_sata_sz_read(base,i));
+}
+
 static int
 decode_win_sata_valid(void)
 {
Index: head/sys/arm/mv/mvwin.h
===================================================================
--- head/sys/arm/mv/mvwin.h
+++ head/sys/arm/mv/mvwin.h
@@ -324,9 +324,16 @@
 #define MV_PCIE_CONTROL			(0x1a00)
 #define MV_PCIE_ROOT_CMPLX		(1 << 1)
 
+#if defined(SOC_MV_ARMADA38X)
+#define	MV_WIN_SATA_CTRL(n)		(0x10 * (n) + 0x60)
+#define	MV_WIN_SATA_BASE(n)		(0x10 * (n) + 0x64)
+#define	MV_WIN_SATA_SIZE(n)		(0x10 * (n) + 0x68)
+#define	MV_WIN_SATA_MAX			4
+#else
 #define	MV_WIN_SATA_CTRL(n)		(0x10 * (n) + 0x30)
 #define	MV_WIN_SATA_BASE(n)		(0x10 * (n) + 0x34)
 #define	MV_WIN_SATA_MAX			4
+#endif
 
 #if defined(SOC_MV_ARMADA38X)
 #define	MV_BOOTROM_MEM_ADDR	0xFFF00000