Index: sys/arm/arm/pmap-v6.c
===================================================================
--- sys/arm/arm/pmap-v6.c
+++ sys/arm/arm/pmap-v6.c
@@ -500,7 +500,8 @@
 
 	/* Add shareable bits for normal memory in SMP case. */
 #ifdef SMP
-	prrr |= PRRR_NS1;
+	if (ARM_HAVE_MP_EXTENSIONS)
+		prrr |= PRRR_NS1;
 #endif
 	cp15_prrr_set(prrr);
 	cp15_nmrr_set(nmrr);
Index: sys/arm/conf/GENERIC
===================================================================
--- sys/arm/conf/GENERIC
+++ sys/arm/conf/GENERIC
@@ -21,6 +21,7 @@
 ident		GENERIC
 
 cpu		CPU_CORTEXA_MP
+cpu		CPU_CORTEXA8
 machine 	arm armv6
 makeoptions	CONF_CFLAGS="-march=armv7a"
 
@@ -37,6 +38,8 @@
 files		"../broadcom/bcm2835/files.bcm283x"
 files		"../nvidia/tegra124/files.tegra124"
 files		"../qemu/files.qemu"
+files		"../ti/files.ti"
+files		"../ti/am335x/files.am335x"
 
 options 	SOC_ALLWINNER_A20
 options 	SOC_ALLWINNER_A31
@@ -44,6 +47,7 @@
 options 	SOC_ALLWINNER_A83T
 options 	SOC_ALLWINNER_H3
 options 	SOC_BCM2836
+options		SOC_TI_AM335X
 
 options 	SCHED_ULE		# ULE scheduler
 options 	SMP			# Enable multiple cores
@@ -66,6 +70,9 @@
 options 	INTRNG
 device		gic
 
+# PMU support (for CCNT).
+device		pmu
+
 # ARM Generic Timer
 device		generic_timer
 
@@ -113,15 +120,30 @@
 device		bcm2835_bsc
 device		icee
 device		sy8106a			# SY8106A Buck Regulator
+device		ti_i2c
+device		am335x_pmic		# AM335x Power Management IC (TPC65217)
+device		am335x_rtc		# RTC support (power management only)
+#define 	am335x_dmtpps		# Pulse Per Second capture driver
 
 # GPIO
 device		gpio
+device		gpiobacklight
 device		gpioled
 device		gpioregulator
 
 # SPI
 device		spibus
 device		bcm2835_spi
+device		ti_spi
+
+# ADC support
+device		ti_adc
+
+# Watchdog support
+# If we don't enable the watchdog driver, the BealeBone could potentially
+# reboot automatically because the boot loader might have enabled the
+# watchdog.
+device		ti_wdt
 
 device		scbus			# SCSI bus (required for ATA/SCSI)
 device		da			# Direct Access (disks)
@@ -135,11 +157,16 @@
 device		ohci
 device		ehci
 device		dwcotg			# DWC OTG controller
+device		musb
 
 device		umass			# Disks/Mass storage - Requires scbus and da
 device		uhid			# "Human Interface Devices"
 device		ukbd			# Allow keyboard like HIDs to control console
 
+# Device mode support and USFS template
+device		usb_template    	# Control of the gadget
+device		usfs
+
 # Ethernet
 device		loop
 device		ether
@@ -170,6 +197,12 @@
 # Pinmux
 device		fdt_pinctrl
 
+# TI Programmable Realtime Unit support
+device		ti_pruss
+
+# Mailbox support
+device		ti_mbox
+
 # Extensible Firmware Interface
 options 	EFI
 
Index: sys/arm/include/cpu-v6.h
===================================================================
--- sys/arm/include/cpu-v6.h
+++ sys/arm/include/cpu-v6.h
@@ -111,15 +111,15 @@
 /* TLB */
 
 _WF0(_CP15_TLBIALL, CP15_TLBIALL)		/* Invalidate entire unified TLB */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 _WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS)		/* Invalidate entire unified TLB IS */
 #endif
 _WF1(_CP15_TLBIASID, CP15_TLBIASID(%0))		/* Invalidate unified TLB by ASID */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 _WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0))	/* Invalidate unified TLB by ASID IS */
 #endif
 _WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0))		/* Invalidate unified TLB by MVA, all ASID */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 _WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0))	/* Invalidate unified TLB by MVA, all ASID IS */
 #endif
 _WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0))		/* Invalidate unified TLB by MVA */
@@ -129,7 +129,7 @@
 /* Cache and Branch predictor */
 
 _WF0(_CP15_BPIALL, CP15_BPIALL)			/* Branch predictor invalidate all */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 _WF0(_CP15_BPIALLIS, CP15_BPIALLIS)		/* Branch predictor invalidate all IS */
 #endif
 _WF1(_CP15_BPIMVA, CP15_BPIMVA(%0))		/* Branch predictor invalidate by MVA */
@@ -143,7 +143,7 @@
 _WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0))		/* Data cache invalidate by MVA PoC */
 _WF1(_CP15_DCISW, CP15_DCISW(%0))		/* Data cache invalidate by set/way */
 _WF0(_CP15_ICIALLU, CP15_ICIALLU)		/* Instruction cache invalidate all PoU */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 _WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS)		/* Instruction cache invalidate all PoU IS */
 #endif
 _WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0))		/* Instruction cache invalidate */
@@ -345,10 +345,13 @@
 }
 
 /* Broadcasting operations. */
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 
-#if defined(CPU_CORTEXA8)
+#if defined(CPU_CORTEXA8) && \
+    (defined(CPU_CORTEXA_MP) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B))
 #define	ARM_HAVE_MP_EXTENSIONS	(cpuinfo.mp_ext != 0)
+#elif defined(CPU_CORTEXA8)
+#define	ARM_HAVE_MP_EXTENSIONS	0
 #else
 #define	ARM_HAVE_MP_EXTENSIONS	1
 #endif
@@ -410,14 +413,14 @@
 	}
 	dsb();
 }
-#else /* SMP */
+#else /* __ARM_ARCH < 7 */
 
 #define tlb_flush_all() 		tlb_flush_all_local()
 #define tlb_flush_all_ng() 		tlb_flush_all_ng_local()
 #define tlb_flush(va) 			tlb_flush_local(va)
 #define tlb_flush_range(va, size) 	tlb_flush_range_local(va, size)
 
-#endif /* SMP */
+#endif /* __ARM_ARCH < 7 */
 
 /*
  * Cache maintenance operations.
@@ -431,7 +434,7 @@
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 	if (ARM_HAVE_MP_EXTENSIONS) {
 		for ( ; va < eva; va += cpuinfo.dcache_line_size)
 			_CP15_DCCMVAU(va);
@@ -442,7 +445,7 @@
 			_CP15_DCCMVAC(va);
 	}
 	dsb();
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 	if (ARM_HAVE_MP_EXTENSIONS)
 		_CP15_ICIALLUIS();
 	else
@@ -456,7 +459,7 @@
 static __inline void
 icache_inv_all(void)
 {
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 	if (ARM_HAVE_MP_EXTENSIONS)
 		_CP15_ICIALLUIS();
 	else
@@ -470,7 +473,7 @@
 static __inline void
 bpb_inv_all(void)
 {
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 	if (ARM_HAVE_MP_EXTENSIONS)
 		_CP15_BPIALLIS();
 	else
@@ -488,7 +491,7 @@
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-#if __ARM_ARCH >= 7 && defined SMP
+#if __ARM_ARCH >= 7
 	if (ARM_HAVE_MP_EXTENSIONS) {
 		for ( ; va < eva; va += cpuinfo.dcache_line_size)
 			_CP15_DCCMVAU(va);
Index: sys/arm/include/sysreg.h
===================================================================
--- sys/arm/include/sysreg.h
+++ sys/arm/include/sysreg.h
@@ -140,7 +140,7 @@
 /*
  * CP15 C7 registers
  */
-#if __ARM_ARCH >= 7 && defined(SMP)
+#if __ARM_ARCH >= 7
 /* From ARMv7: */
 #define	CP15_ICIALLUIS		p15, 0, r0, c7, c1,  0 /* Instruction cache invalidate all PoU, IS */
 #define	CP15_BPIALLIS		p15, 0, r0, c7, c1,  6 /* Branch predictor invalidate all IS */
@@ -205,7 +205,7 @@
 /*
  * CP15 C8 registers
  */
-#if __ARM_ARCH >= 7 && defined(SMP)
+#if __ARM_ARCH >= 7
 /* From ARMv7: */
 #define	CP15_TLBIALLIS		p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
 #define	CP15_TLBIMVAIS(rr)	p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */