Index: sys/arm/arm/cpuinfo.c
===================================================================
--- sys/arm/arm/cpuinfo.c
+++ sys/arm/arm/cpuinfo.c
@@ -131,6 +131,8 @@
 	cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
 	cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
 	cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
+	/* mpidr */
+	cpuinfo.mp_ext = (cpuinfo.mpidr >> 31u) & 0x1;
 
 	/* L1 Cache sizes */
 	if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) {
Index: sys/arm/include/cpu-v6.h
===================================================================
--- sys/arm/include/cpu-v6.h
+++ sys/arm/include/cpu-v6.h
@@ -350,7 +350,10 @@
 {
 
 	dsb();
-	_CP15_TLBIALLIS();
+	if (cpuinfo.mp_ext)
+		_CP15_TLBIALL();
+	else
+		_CP15_TLBIALLIS();
 	dsb();
 }
 
@@ -359,7 +362,10 @@
 {
 
 	dsb();
-	_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
+	if (cpuinfo.mp_ext)
+		_CP15_TLBIASID(CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 	dsb();
 }
 
@@ -370,7 +376,10 @@
 	KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 
 	dsb();
-	_CP15_TLBIMVAAIS(va);
+	if (cpuinfo.mp_ext)
+		_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIMVAAIS(va);
 	dsb();
 }
 
@@ -384,8 +393,13 @@
 	    size));
 
 	dsb();
-	for (; va < eva; va += PAGE_SIZE)
-		_CP15_TLBIMVAAIS(va);
+	if (cpuinfo.mp_ext) {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	} else {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVAAIS(va);
+	}
 	dsb();
 }
 #else /* SMP */
@@ -409,19 +423,23 @@
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
-#endif
+	if (cpuinfo.mp_ext) {
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAU(va);
+	} else
+#endif
+	{
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (cpuinfo.mp_ext)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -431,10 +449,11 @@
 icache_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (cpuinfo.mp_ext)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -444,10 +463,11 @@
 bpb_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_BPIALLIS();
-#else
-	_CP15_BPIALL();
+	if (cpuinfo.mp_ext)
+		_CP15_BPIALLIS();
+	else
 #endif
+		_CP15_BPIALL();
 	dsb();
 	isb();
 }
@@ -460,12 +480,15 @@
 
 	dsb();
 	va &= ~cpuinfo.dcache_line_mask;
-	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
-#endif
+	if (cpuinfo.mp_ext) {
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAU(va);
+	} else
+#endif
+	{
+		for ( ; va < eva; va += cpuinfo.dcache_line_size)
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 }
Index: sys/arm/include/cpuinfo.h
===================================================================
--- sys/arm/include/cpuinfo.h
+++ sys/arm/include/cpuinfo.h
@@ -105,6 +105,9 @@
 	int dcache_line_mask;
 	int icache_line_size;
 	int icache_line_mask;
+
+	/* mpidr */
+	int mp_ext;
 };
 
 extern struct cpuinfo cpuinfo;