Index: sys/arm/include/cpu-v6.h
===================================================================
--- sys/arm/include/cpu-v6.h
+++ sys/arm/include/cpu-v6.h
@@ -345,12 +345,18 @@
 /* Broadcasting operations. */
 #if __ARM_ARCH >= 7 && defined SMP
 
+/* Used to detect SMP */
+extern int mp_ncpus;
+
 static __inline void
 tlb_flush_all(void)
 {
 
 	dsb();
-	_CP15_TLBIALLIS();
+	if (mp_ncpus == 1)
+		_CP15_TLBIALL();
+	else
+		_CP15_TLBIALLIS();
 	dsb();
 }
 
@@ -359,7 +365,10 @@
 {
 
 	dsb();
-	_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
+	if (mp_ncpus == 1)
+		_CP15_TLBIASID(CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
 	dsb();
 }
 
@@ -370,7 +379,10 @@
 	KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va));
 
 	dsb();
-	_CP15_TLBIMVAAIS(va);
+	if (mp_ncpus == 1)
+		_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	else
+		_CP15_TLBIMVAAIS(va);
 	dsb();
 }
 
@@ -384,8 +396,13 @@
 	    size));
 
 	dsb();
-	for (; va < eva; va += PAGE_SIZE)
-		_CP15_TLBIMVAAIS(va);
+	if (mp_ncpus == 1) {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVA(va | CPU_ASID_KERNEL);
+	} else {
+		for (; va < eva; va += PAGE_SIZE)
+			_CP15_TLBIMVAAIS(va);
+	}
 	dsb();
 }
 #else /* SMP */
@@ -411,17 +428,19 @@
 	va &= ~cpuinfo.dcache_line_mask;
 	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+		if (mp_ncpus > 1)
+			_CP15_DCCMVAU(va);
+		else
 #endif
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (mp_ncpus > 1)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -431,10 +450,11 @@
 icache_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_ICIALLUIS();
-#else
-	_CP15_ICIALLU();
+	if (mp_ncpus > 1)
+		_CP15_ICIALLUIS();
+	else
 #endif
+		_CP15_ICIALLU();
 	dsb();
 	isb();
 }
@@ -444,10 +464,11 @@
 bpb_inv_all(void)
 {
 #if __ARM_ARCH >= 7 && defined SMP
-	_CP15_BPIALLIS();
-#else
-	_CP15_BPIALL();
+	if (mp_ncpus > 1)
+		_CP15_BPIALLIS();
+	else
 #endif
+		_CP15_BPIALL();
 	dsb();
 	isb();
 }
@@ -462,10 +483,11 @@
 	va &= ~cpuinfo.dcache_line_mask;
 	for ( ; va < eva; va += cpuinfo.dcache_line_size) {
 #if __ARM_ARCH >= 7 && defined SMP
-		_CP15_DCCMVAU(va);
-#else
-		_CP15_DCCMVAC(va);
+		if (mp_ncpus > 1)
+			_CP15_DCCMVAU(va);
+		else
 #endif
+			_CP15_DCCMVAC(va);
 	}
 	dsb();
 }