Index: sys/mips/cavium/octeon_mp.c
===================================================================
--- sys/mips/cavium/octeon_mp.c
+++ sys/mips/cavium/octeon_mp.c
@@ -63,11 +63,19 @@
 }
 
 int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
 {
+
 	return (1);
 }
 
+int
+platform_ipi_softintr_num(void)
+{
+
+	return (-1);
+}
+
 void
 platform_init_ap(int cpuid)
 {
@@ -93,7 +101,7 @@
 	 */
 	ciu_int_mask = hard_int_mask(0);
 	clock_int_mask = hard_int_mask(5);
-	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+	ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
 	set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
 
 	mips_wbflush();
Index: sys/mips/gxemul/gxemul_machdep.c
===================================================================
--- sys/mips/gxemul/gxemul_machdep.c
+++ sys/mips/gxemul/gxemul_machdep.c
@@ -186,11 +186,19 @@
 }
 
 int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
 {
+
 	return (GXEMUL_MP_DEV_IPI_INTERRUPT - 2);
 }
 
+int
+platform_ipi_softintr_num(void)
+{
+
+	return (-1);
+}
+
 struct cpu_group *
 platform_smp_topo(void)
 {
@@ -206,7 +214,7 @@
 	 * Unmask the clock and ipi interrupts.
 	 */
 	clock_int_mask = hard_int_mask(5);
-	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+	ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
 	set_intr_mask(ipi_int_mask | clock_int_mask);
 }
 
Index: sys/mips/include/hwfunc.h
===================================================================
--- sys/mips/include/hwfunc.h
+++ sys/mips/include/hwfunc.h
@@ -67,7 +67,8 @@
  * This hardware interrupt is used to deliver IPIs exclusively and must
  * not be used for any other interrupt source.
  */
-int platform_ipi_intrnum(void);
+int platform_ipi_hardintr_num(void);
+int platform_ipi_softintr_num(void);
 
 /*
  * Trigger a IPI interrupt on 'cpuid'.
Index: sys/mips/mips/mp_machdep.c
===================================================================
--- sys/mips/mips/mp_machdep.c
+++ sys/mips/mips/mp_machdep.c
@@ -345,9 +345,15 @@
 	/*
 	 * IPI handler
 	 */
-	ipi_irq = platform_ipi_intrnum();
-	cpu_establish_softintr("ipi", mips_ipi_handler, NULL, NULL, ipi_irq,
-			       INTR_TYPE_MISC | INTR_EXCL, NULL);
+	ipi_irq = platform_ipi_hardintr_num();
+	if (ipi_irq != -1) {
+		cpu_establish_hardintr("ipi", mips_ipi_handler, NULL, NULL,
+		    ipi_irq, INTR_TYPE_MISC | INTR_EXCL, NULL);
+	} else {
+		ipi_irq = platform_ipi_softintr_num();
+		cpu_establish_softintr("ipi", mips_ipi_handler, NULL, NULL,
+		    ipi_irq, INTR_TYPE_MISC | INTR_EXCL, NULL);
+	}
 
 	atomic_store_rel_int(&aps_ready, 1);
 
Index: sys/mips/nlm/xlp_machdep.c
===================================================================
--- sys/mips/nlm/xlp_machdep.c
+++ sys/mips/nlm/xlp_machdep.c
@@ -687,18 +687,25 @@
 }
 
 int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
 {
 
 	return (IRQ_IPI);
 }
 
+int
+platform_ipi_softintr_num(void)
+{
+
+	return (-1);
+}
+
 void
 platform_ipi_send(int cpuid)
 {
 
 	nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
-	    platform_ipi_intrnum(), 0);
+	    platform_ipi_hardintr_num(), 0);
 }
 
 void
Index: sys/mips/rmi/xlr_machdep.c
===================================================================
--- sys/mips/rmi/xlr_machdep.c
+++ sys/mips/rmi/xlr_machdep.c
@@ -571,17 +571,24 @@
 }
 
 int
-platform_ipi_intrnum(void) 
+platform_ipi_hardintr_num(void)
 {
 
 	return (IRQ_IPI);
 }
 
+int
+platform_ipi_softintr_num(void)
+{
+
+	return (-1);
+}
+
 void
 platform_ipi_send(int cpuid)
 {
 
-	pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_intrnum());
+	pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_hardintr_num());
 }
 
 void
Index: sys/mips/sibyte/sb_machdep.c
===================================================================
--- sys/mips/sibyte/sb_machdep.c
+++ sys/mips/sibyte/sb_machdep.c
@@ -124,7 +124,7 @@
 		 * with any other interrupt source.
 		 */
 		if (intsrc == INTSRC_MAILBOX3) {
-			intrnum = platform_ipi_intrnum();
+			intrnum = platform_ipi_hardintr_num();
 			sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
 			sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
 		}
@@ -313,12 +313,19 @@
 }
 
 int
-platform_ipi_intrnum(void)
+platform_ipi_hardintr_num(void)
 {
 
 	return (4);
 }
 
+int
+platform_ipi_softintr_num(void)
+{
+
+	return (-1);
+}
+
 struct cpu_group *
 platform_smp_topo(void)
 {
@@ -344,7 +351,7 @@
 	 * Unmask the clock and ipi interrupts.
 	 */
 	clock_int_mask = hard_int_mask(5);
-	ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
+	ipi_int_mask = hard_int_mask(platform_ipi_hardintr_num());
 	set_intr_mask(ipi_int_mask | clock_int_mask);
 }
 
Index: sys/mips/sibyte/sb_scd.c
===================================================================
--- sys/mips/sibyte/sb_scd.c
+++ sys/mips/sibyte/sb_scd.c
@@ -207,7 +207,7 @@
 	 * Use a deterministic mapping for the remaining sources.
 	 */
 #ifdef SMP
-	KASSERT(platform_ipi_intrnum() == 4,
+	KASSERT(platform_ipi_hardintr_num() == 4,
 		("Unexpected interrupt number used for IPI"));
 	intrnum = intsrc % 4;
 #else