Index: sys/mips/conf/TP-MR3020
===================================================================
--- /dev/null
+++ sys/mips/conf/TP-MR3020
@@ -0,0 +1,58 @@
+#
+# TP Link MR3020 - an AR9331 based SoC wifi device.
+#
+# This is for the 32 RAM/4 flash part. There is little to no
+# chance that this will ever boot FreeBSD directly from the 3.5MB
+# of flash.  The kernel can fit into the space, but userland is just
+# too big even when stripped down to its limits.
+#
+# * AR9331 SoC
+# * 32MB RAM
+# * 4MB flash
+# * Integrated 1x1 2GHz wifi and 10/100 bridge
+# * USB powered
+# * USB storage
+#
+# $FreeBSD$
+#
+
+# Include the default AR933x parameters
+include	"AR933X_BASE"
+
+ident	TP-MR3020
+
+# Override hints with board values
+hints	"TP-MR3020.hints"
+
+# Board memory - 32MB
+options	AR71XX_REALMEM=(32*1024*1024)
+
+makeoptions	MODULES_OVERRIDE="random if_gif if_gre if_bridge bridgestp hwpmc"
+
+# i2c GPIO bus
+device	gpioiic
+device	iicbb
+device	iicbus
+device	iic
+
+# Options required for miiproxy and mdiobus
+options	ARGE_MDIO	# Export an MDIO bus separate from arge
+device	miiproxy	# MDIO bus <-> MII PHY rendezvous
+
+device	etherswitch
+device	arswitch
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options	AR71XX_ENV_UBOOT
+
+# Used for the static uboot partition map
+device	geom_map
+
+nodevice if_bridge
+nodevice bridgestp
+nodevice random
+
+# The 4MB of flash is too small to have a FreeBSD rootfs flashed to it.
+# Assume the user has a USB drive attached as a rootfs.
+options	ROOTDEVNAME=\"ufs:da0\"
Index: sys/mips/conf/TP-MR3020.hints
===================================================================
--- /dev/null
+++ sys/mips/conf/TP-MR3020.hints
@@ -0,0 +1,94 @@
+#
+# This file adds to the values in AR933X_BASE.hints
+#
+# $FreeBSD$
+
+# mdiobus on arge1
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x1a000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# There's no need to set the ar933x GMAC configuration bits.
+# This just creates a switch instance and correctly uses it.
+
+# Embedded Atheros Switch
+hint.arswitch.0.at="mdio0"
+
+# XXX this should really say it's an AR933x switch, as there
+# are some vlan specific differences here!
+hint.arswitch.0.is_7240=1
+hint.arswitch.0.numphys=4
+hint.arswitch.0.phy4cpu=1	# phy 4 is a "CPU" separate PHY
+hint.arswitch.0.is_rgmii=0
+hint.arswitch.0.is_gmii=1	# arge1 <-> switch PHY is GMII
+
+# arge0 - MII, autoneg, phy(4)
+hint.arge.0.phymask=0x10	# PHY4
+hint.arge.0.mdio=mdioproxy1	# .. off of the switch mdiobus
+
+# arge1 - GMII, 1000/full
+hint.arge.1.phymask=0x0		# No directly mapped PHYs
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+
+# Where the ART is - last 64k in the flash
+# 0x9fff1000 ?
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# The board 16MiB flash layout in uboot env:
+#
+# 256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)
+
+# However, it boots from 0x9f050000, which is the front of the flsah!
+# Thus the kernel/rootfs are switched around.
+
+# 256KB
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00040000
+hint.map.0.name="uboot"
+hint.map.0.readonly=1
+
+# 64KB
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00040000
+hint.map.1.end=0x00050000
+hint.map.1.name="uboot-env"
+hint.map.1.readonly=0
+
+# 2752KB
+hint.map.2.at="flash/spi0"
+hint.map.2.start=0x00050000
+hint.map.2.end=0x003e0000
+hint.map.2.name="kernel"
+hint.map.2.readonly=0
+
+# 64K NVRAM
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x003e0000
+hint.map.4.end=0x003f0000
+hint.map.4.name="cfg"
+hint.map.4.readonly=0
+
+# 64K ART
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x003f0000
+hint.map.5.end=0x00400000
+hint.map.5.name="art"
+hint.map.5.readonly=1
+
+# GPIO specific configuration block
+
+# Don't flip on anything that isn't already enabled.
+# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
+# not used here.
+hint.gpio.0.function_set=0x00000000
+hint.gpio.0.function_clear=0x00000000
+
+# These are the GPIO LEDs and buttons which can be software controlled.
+#hint.gpio.0.pinmask=0x001c02ae
+#hint.gpio.0.pinmask=0x00001803
+
+# XXX TODO: the button and LEDs!