Index: sys/arm/annapurna/alpine/alpine_pci.h =================================================================== --- /dev/null +++ sys/arm/annapurna/alpine/alpine_pci.h @@ -0,0 +1,38 @@ +/*- + * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef ALPINE_PCI_H_ +#define ALPINE_PCI_H_ + +#ifndef INTRNG +int al_msix_map_msi(int irq, uint64_t *addr, uint32_t *data); +int al_msix_alloc_msi(int count, int *irqs); +int al_msix_release_msi(int count, int *irqs); +#endif + +#endif /* ALPINE_PCI_H_ */ Index: sys/arm/annapurna/alpine/alpine_pci.c =================================================================== --- /dev/null +++ sys/arm/annapurna/alpine/alpine_pci.c @@ -0,0 +1,293 @@ +/*- + * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates + * All rights reserved. + * + * Developed by Semihalf. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Alpine PCI/PCI-Express controller driver. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "alpine_pci.h" +#include "pcib_if.h" + +#include "contrib/alpine-hal/al_hal_unit_adapter_regs.h" +#include "contrib/alpine-hal/al_hal_pcie.h" +#include "contrib/alpine-hal/al_hal_pcie_axi_reg.h" + +#define ANNAPURNA_VENDOR_ID 0x1c36 + +#define GIC_FDT_CELLS 3 +#define GIC_FIRST_SPI 32 + +/* Forward prototypes */ +static int al_pcib_probe(device_t); +static int al_pcib_attach(device_t); +static void al_pcib_fixup(device_t); + +#ifndef INTRNG +static int al_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); +static int al_pcib_alloc_msi(device_t, device_t, int, int, int *); +static int al_pcib_release_msi(device_t, device_t, int, int *); +static int al_pcib_alloc_msix(device_t, device_t, int *); +static int al_pcib_release_msix(device_t, device_t, int); +#else +static void al_pcib_destruct_map_data(struct intr_map_data *); +static struct intr_map_data * al_pcib_extend_resource(device_t, device_t, int, + int *, rman_res_t, rman_res_t, rman_res_t); +#endif + +static struct ofw_compat_data compat_data[] = { + {"annapurna-labs,al-internal-pcie", true}, + {"annapurna-labs,alpine-internal-pcie", true}, + {NULL, false} +}; + +/* + * Bus interface definitions. + */ +static device_method_t al_pcib_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, al_pcib_probe), + DEVMETHOD(device_attach, al_pcib_attach), + +#ifndef INTRNG + DEVMETHOD(pcib_alloc_msi, al_pcib_alloc_msi), + DEVMETHOD(pcib_release_msi, al_pcib_release_msi), + DEVMETHOD(pcib_map_msi, al_pcib_map_msi), + DEVMETHOD(pcib_alloc_msix, al_pcib_alloc_msix), + DEVMETHOD(pcib_release_msix, al_pcib_release_msix), +#else + DEVMETHOD(bus_extend_resource, al_pcib_extend_resource), + +#endif + DEVMETHOD_END +}; + +DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods, + sizeof(struct generic_pcie_softc), generic_pcie_driver); + +static devclass_t anpa_pcib_devclass; + +DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, anpa_pcib_devclass, 0, 0); +DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, anpa_pcib_devclass, 0, 0); + +static int +al_pcib_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, + "Annapurna-Labs Integrated Internal PCI-E Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +al_pcib_attach(device_t dev) +{ + int rv; + + rv = pci_host_generic_attach(dev); + + /* Annapurna quirk: configure vendor-specific registers */ + if (rv == 0) + al_pcib_fixup(dev); + + return (rv); +} + +static void +al_pcib_fixup(device_t dev) +{ + uint32_t val; + uint16_t vid; + uint8_t hdrtype; + int bus, slot, func, maxfunc; + + /* Fixup is only needed on bus 0 */ + bus = 0; + for (slot = 0; slot <= PCI_SLOTMAX; slot++) { + maxfunc = 0; + for (func = 0; func <= maxfunc; func++) { + hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func, + PCIR_HDRTYPE, 1); + + if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) + continue; + + if (func == 0 && (hdrtype & PCIM_MFDEV) != 0) + maxfunc = PCI_FUNCMAX; + + vid = PCIB_READ_CONFIG(dev, bus, slot, func, + PCIR_VENDOR, 2); + if (vid == ANNAPURNA_VENDOR_ID) { + val = PCIB_READ_CONFIG(dev, bus, slot, func, + AL_PCI_AXI_CFG_AND_CTR_0, 4); + val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK; + PCIB_WRITE_CONFIG(dev, bus, slot, func, + AL_PCI_AXI_CFG_AND_CTR_0, val, 4); + + val = PCIB_READ_CONFIG(dev, bus, slot, func, + AL_PCI_APP_CONTROL, 4); + val &= ~0xffff; + val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK; + PCIB_WRITE_CONFIG(dev, bus, slot, func, + AL_PCI_APP_CONTROL, val, 4); + } + } + } +} + +#ifndef INTRNG +static int +al_pcib_map_msi(device_t dev __unused, device_t child __unused, int irq, + uint64_t *addr, uint32_t *data) +{ + + return (al_msix_map_msi(irq, addr, data)); +} + +static int +al_pcib_alloc_msi(device_t dev __unused, device_t child __unused, int count, + int maxcount __unused, int *irqs) +{ + + return (al_msix_alloc_msi(count, irqs)); +} + +static int +al_pcib_release_msi(device_t dev __unused, device_t child __unused, + int count, int *irqs) +{ + + return (al_msix_release_msi(count, irqs)); +} + +static int +al_pcib_alloc_msix(device_t dev __unused, device_t child __unused, int *irq) +{ + + return (al_msix_alloc_msi(1, irq)); +} + +static int +al_pcib_release_msix(device_t dev __unused, device_t child __unused, int irq) +{ + + return (al_msix_release_msi(1, &irq)); +} +#else /* INTRNG */ +static void +al_pcib_destruct_map_data(struct intr_map_data *map_data) +{ + struct intr_map_data_fdt *fdt_map_data; + + KASSERT(map_data->type == INTR_MAP_DATA_FDT, + ("%s: bad map_data type %d", __func__, map_data->type)); + + fdt_map_data = (struct intr_map_data_fdt *)map_data; + free(fdt_map_data->cells, M_OFWPROP); + free(fdt_map_data, M_OFWPROP); +} + +static struct intr_map_data * +al_pcib_extend_resource(device_t dev, device_t child, int type, int *rid, + rman_res_t start, rman_res_t end, rman_res_t count) +{ + struct intr_map_data_fdt *fdt_data; + struct resource_list_entry *rle; + struct resource_list *rl; + phandle_t iparent; + pcell_t *cells; + + /* + * Alpine MSI-X interrupt controller works similarly to GICv2m - some + * range of SPI interrupts is reserved for MSI-X. These SPI interrupts + * need to be configured in GIC as edge trigger and high polarity. GIC + * fails to setup interrupt if its resource is not extended with FDT + * data. Prepare an FDT data struct with encoded trig/pol and SPI number + * to allow PIC_SETUP_INTR to succeed. + */ + + /* MSI-X interrupt resources have rid greater than 0 */ + if ((type != SYS_RES_IRQ) || (*rid == 0)) + goto generic; + + iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev)); + + /* Retrieve resource list entry and get IRQ# from 'start' field */ + rl = BUS_GET_RESOURCE_LIST(device_get_parent(child), child); + if (rl == NULL) + goto generic; + + rle = resource_list_find(rl, type, *rid); + if (rle == NULL) + goto generic; + + cells = malloc(GIC_FDT_CELLS * sizeof(*cells), M_OFWPROP, + M_WAITOK); + cells[0] = 0; /* Code for SPI interrupt */ + cells[1] = rle->start - GIC_FIRST_SPI; + cells[2] = 1; /* Code for edge trigger, high polarity */ + + fdt_data = malloc(sizeof(*fdt_data), M_OFWPROP, + M_WAITOK | M_ZERO); + fdt_data->hdr.type = INTR_MAP_DATA_FDT; + fdt_data->hdr.destruct = al_pcib_destruct_map_data; + fdt_data->iparent = iparent; + fdt_data->ncells = GIC_FDT_CELLS; + fdt_data->cells = cells; + + return ((struct intr_map_data *)fdt_data); + +generic: + return (bus_generic_extend_resource(dev, child, type, rid, start, end, + count)); +} +#endif Index: sys/arm/annapurna/alpine/files.alpine =================================================================== --- sys/arm/annapurna/alpine/files.alpine +++ sys/arm/annapurna/alpine/files.alpine @@ -6,6 +6,7 @@ arm/versatile/versatile_timer.c standard dev/uart/uart_dev_ns8250.c optional uart +arm/annapurna/alpine/alpine_pci.c optional pci arm/annapurna/alpine/common.c standard arm/annapurna/alpine/alpine_ccu.c standard arm/annapurna/alpine/alpine_nb_service.c standard Index: sys/arm/conf/ALPINE =================================================================== --- sys/arm/conf/ALPINE +++ sys/arm/conf/ALPINE @@ -63,6 +63,10 @@ # Serial ports device uart +# PCI/PCIE +device pci +device pci_host_generic + # Ethernet device ether device mii Index: sys/boot/fdt/dts/arm/annapurna-alpine.dts =================================================================== --- sys/boot/fdt/dts/arm/annapurna-alpine.dts +++ sys/boot/fdt/dts/arm/annapurna-alpine.dts @@ -175,6 +175,7 @@ device_type = "pci"; #size-cells = <2>; #address-cells = <3>; + reg = <0xfbc00000 0x100000>; interrupt-parent = <&MPIC>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter Index: sys/conf/files.arm64 =================================================================== --- sys/conf/files.arm64 +++ sys/conf/files.arm64 @@ -1,6 +1,7 @@ # $FreeBSD$ arm/annapurna/alpine/alpine_ccu.c optional soc_anpa_alpinev2 arm/annapurna/alpine/alpine_nb_service.c optional soc_anpa_alpinev2 +arm/annapurna/alpine/alpine_pci.c optional soc_anpa_alpinev2 pci fdt arm/arm/generic_timer.c standard arm/arm/gic.c optional intrng arm/arm/pmu.c standard