Index: share/man/man4/Makefile =================================================================== --- share/man/man4/Makefile +++ share/man/man4/Makefile @@ -79,6 +79,7 @@ bhndb.4 \ bktr.4 \ blackhole.4 \ + bnxt.4 \ bpf.4 \ bridge.4 \ bt.4 \ @@ -592,6 +593,7 @@ MLINKS+=bfe.4 if_bfe.4 MLINKS+=bge.4 if_bge.4 MLINKS+=bktr.4 brooktree.4 +MLINKS+=bnxt.4 if_bnxt.4 MLINKS+=bridge.4 if_bridge.4 MLINKS+=bwi.4 if_bwi.4 MLINKS+=bwn.4 if_bwn.4 Index: share/man/man4/bnxt.4 =================================================================== --- /dev/null +++ share/man/man4/bnxt.4 @@ -0,0 +1,222 @@ +.\" Copyright (c) 2016 Broadcom, All Rights Reserved. +.\" The term Broadcom refers to Broadcom Limited and/or its subsidiaries +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' +.\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +.\" THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd May 12, 2016 +.Dt BNXT 4 +.Os +.Sh NAME +.Nm bnxt +.Nd "Broadcom NetXtreme-C/NetXtreme-E Family Ethernet driver" +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device bnxt" +.Ed +.Pp +Alternatively, to load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +if_bnxt_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver provides support for various NICs based on the Broadcom BCM57301/2/4, +and BCM57402/4/6 Ethernet controller chips. +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh HARDWARE +The +.Nm +driver provides support for various NICs based on the Broadcom NetXtreme-C and +NetXtreme-E families of Gigabit Ethernet controller chips, including the +following: +.Pp +.Bl -bullet -compact +.It +Broadcom BCM57301 NetXtreme-C 10Gb Ethernet Controller +.It +Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet Controller +.It +Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet Controller +.It +Broadcom BCM57402 NetXtreme-E 10Gb Ethernet Controller +.It +Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet Controller +.It +Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet Controller +.It +Broadcom BCM57402 NetXtreme-E Partition +.It +Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet Controller +.It +Broadcom BCM57404 NetXtreme-E Partition +.It +Broadcom BCM57406 NetXtreme-E Partition +.It +Broadcom BCM57407 NetXtreme-E 25Gb Ethernet Controller +.It +Broadcom BCM57304 NetXtreme-C Virtual Function +.It +Broadcom BCM57404 NetXtreme-E Virtual Function +.El +.Sh SYSCTL VARIABLES +These variables must be set before loading the driver, either via +.Xr loader.conf 5 +or through the use of +.Xr kenv 1 . +These are provided by the +.Xr iflib 9 +framework, and might be better documented there. +.Bl -tag -width indent +.It Va dev.bnxt.X.iflib.override_nrxds +Override the number of RX descriptors for each queue. +The value is a comma separated list of three positive integers: the size of the +completion ring, +the size of the receive ring, and the size of the aggregation ring respectively. +The completion ring should be at least the size of the aggregation ring plus +four times the size of the receive ring. +These numbers must be powers of two, and zero means to use the default. +Defaults to 0,0,0. +.It Va dev.bnxt.X.iflib.override_ntxds +Override the number of TX descriptors for each queue. +The value is a comma separated list of two positive integers: the size of the +completion ring, and the size of the transmit ring respectively. +The completion ring should be at least twice the size of the transmit ring. +These numbers must be powers of two, and zero means to use the default. +Defaults to 0,0. +.It Va override_qs_enable +When set, allows the number of transmit and receive queues to be different. +If not set, the lower of the number of TX or RX queues will be used for both. +.It Va override_nrxqs +Set the number of RX queues. +If zero, the number of RX queues is derived from the number of cores on the +socket connected to the controller. +Defaults to 0. +.It Va override_ntxqs +Set the number of TX queues. +If zero, the number of TX queues is derived from the number of cores on the +socket connected to the controller. +.El +.Pp +These +.Xr sysctl 8 +variables can be changed at any time: +.Bl -tag -width indent +.It Va dev.bnxt.X.vlan_only +Require that incoming frames must have a VLAN tag on them that matches one that +is configured for the NIC. +Normally, both frames that have a matching VLAN tag and frames that have no +VLAN tag are accepted. +Defaults to 0. +.It Va dev.bnxt.X.vlan_strip +When non-zero the NIC strips VLAN tags on receive. +Defaults to 0. +.It Va dev.bnxt.X.rx_stall +Enable buffering rather than dropping frames when there are no available host +RX buffers for DMA. +Defaults to 0. +.It Va dev.bnxt.X.rss_type +Comma-separated list of RSS hash types to support. +Default is all types. +Defaults to ipv4,tcp_ipv4,udp_ipv4,ipv6,tcp_ipv6,udp_ipv6. +.It Va dev.bnxt.X.rss_key +Current RSS key. +Defaults to a randomly generated value which is generated for each device +during attach. +.It Va dev.bnxt.X.ver.hwrm_min_ver +Minimum HWRM (HardWare Resource Manager) firmware API to support. +If the firmware implements an older version, a warning will be printed, and the +firmware should be upgraded. +Defaults to 1.2.2. +.El +.Pp +These +.Xr sysctl 8 +variables are read-only: +.Bl -tag -width indent +.It Va dev.bnxt.X.if_name +Current interface name of the device. +This will normally be +.Va bnxtX , +but this can be changed using +.Cm ifconfig name . +This sysctl allows correlating an interface with a child of dev.bnxt. +.It Va dev.bnxt.X.nvram.* +Information about the NVRAM device which contains the device firmware. +.It Va dev.bnxt.X.ver.* +Version-related information about the device and firmware: +.It Va dev.bnxt.X.ver.hwrm_if +Supported HWRM API version of the currently running firmware. +.It Va dev.bnxt.X.ver.driver_hwrm_if +HWRM API version the driver was built to support. +.It Va dev.bnxt.X.hwstats.* +Per-queue statistics tracked by the hardware. +.It Va dev.bnxt.X.hwstats.rxq0.drop_pkts +Number of packets dropped by hardware on queue zero. +This number might seem high, but the count includes packets dropped due to +incorrect destination MAC, unsubscribed multicast address, and other normal +reasons to ignore Ethernet frames. +.El +.Sh DIAGNOSTICS +.Bl -diag +.It "bnxt%d: %s command returned %s error." +Device firmware rejected a command from the driver. +There might be a driver/firmware HWRM API mismatch. +.It "bnxt%d: Timeout sending %s (timeout: %d) seq %d\n" +Device firmware unresponsive. +A PCI device reset is likely needed. +.It "bnxt%d: Timeout sending %s (timeout: %d) msg {0x%x 0x%x} len:%d v: %d\n" +Partial firmware response. +A PCI device reset is likely needed. +.Pp +As of this writing, the system must be rebooted to initiate a PCI device reset. +.El +.Sh SEE ALSO +.Xr altq 4 , +.Xr arp 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr vlan 4 , +.Xr ifconfig 8 , +.Xr iflib 4 +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 12.0 . +.Sh AUTHORS +The +.Nm +driver was written by +.An Jack Vogel Aq Mt jfvogel@gmail.com . +and is currently maintained by +.An Stephen Hurd Aq Mt stephen.hurd@broadcom.com . Index: sys/boot/forth/loader.conf =================================================================== --- sys/boot/forth/loader.conf +++ sys/boot/forth/loader.conf @@ -312,6 +312,7 @@ if_bce_load="NO" # Broadcom NetXtreme II Gigabit Ethernet if_bfe_load="NO" # Broadcom BCM4401 if_bge_load="NO" # Broadcom BCM570x PCI Gigabit Ethernet +if_bnxt_load="NO" # Broadcom NetXtreme-C/NetXtreme-E if_bridge_load="NO" # if_bridge(4) devices if_bwi_load="NO" # Broadcom BCM53xx IEEE 802.11b/g wireness NICs if_bwn_load="NO" # Broadcom BCM43xx IEEE 802.11 wireless NICs Index: sys/conf/NOTES =================================================================== --- sys/conf/NOTES +++ sys/conf/NOTES @@ -1917,6 +1917,7 @@ device atphy # Attansic/Atheros F1 device axphy # Asix Semiconductor AX88x9x device bmtphy # Broadcom BCM5201/BCM5202 and 3Com 3c905C +device bnxt # Broadcom NetXtreme-C/NetXtreme-E device brgphy # Broadcom BCM54xx/57xx 1000baseTX device ciphy # Cicada/Vitesse CS/VSC8xxx device e1000phy # Marvell 88E1000 1000/100/10-BT @@ -1957,6 +1958,7 @@ # BCM570x family of controllers, including the 3Com 3c996-T, # the Netgear GA302T, the SysKonnect SK-9D21 and SK-9D41, and # the embedded gigE NICs on Dell PowerEdge 2550 servers. +# bnxt: Broadcom NetXtreme-C and NetXtreme-E PCIe 10/25/50G Ethernet adapters. # bxe: Broadcom NetXtreme II (BCM5771X/BCM578XX) PCIe 10Gb Ethernet # adapters. # bwi: Broadcom BCM430* and BCM431* family of wireless adapters. Index: sys/conf/files =================================================================== --- sys/conf/files +++ sys/conf/files @@ -1183,6 +1183,10 @@ dev/bktr/bktr_os.c optional bktr pci dev/bktr/bktr_tuner.c optional bktr pci dev/bktr/msp34xx.c optional bktr pci +dev/bnxt/bnxt_hwrm.c optional bnxt iflib pci +dev/bnxt/bnxt_sysctl.c optional bnxt iflib pci +dev/bnxt/bnxt_txrx.c optional bnxt iflib pci +dev/bnxt/if_bnxt.c optional bnxt iflib pci dev/buslogic/bt.c optional bt dev/buslogic/bt_eisa.c optional bt eisa dev/buslogic/bt_isa.c optional bt isa Index: sys/dev/bnxt/bnxt.h =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt.h @@ -0,0 +1,569 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#ifndef _BNXT_H +#define _BNXT_H + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "hsi_struct_def.h" + +/* PCI IDs */ +#define BROADCOM_VENDOR_ID 0x14E4 + +#define BCM57301 0x16c8 +#define BCM57302 0x16c9 +#define BCM57304 0x16ca +#define BCM57402 0x16d0 +#define BCM57404 0x16d1 +#define BCM57406 0x16d2 +#define BCM57402_NPAR 0x16d4 +#define BCM57407 0x16d5 +#define BCM57404_NPAR 0x16e7 +#define BCM57406_NPAR 0x16e8 +#define BCM57407_SFP 0x16e9 +#define BCM57304_VF 0x16cb +#define BCM57404_VF 0x16d3 + +#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ + CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ + CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) + +#define BNXT_MAX_MTU 9000 + +/* Completion related defines */ +#define CMP_VALID(cmp, v_bit) \ + ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) + +#define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ + if (__predict_false(++(cons) == (ring)->ring_size)) \ + ((cons) = 0, (v_bit) = !v_bit); \ +} while (0) + +#define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ + 0 : idx + 1) + +#define CMPL_PREFETCH_NEXT(cpr, idx) \ + __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ + (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ + ((cpr)->ring.ring_size - 1)]) + +/* + * If we update the index, a write barrier is needed after the write to ensure + * the completion ring has space before the RX/TX ring does. Since we can't + * make the RX and AG doorbells covered by the same barrier without remapping + * MSI-X vectors, we create the barrier over the enture doorbell bar. + * TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells + * for a single ring group. + * + * A barrier of just the size of the write is used to ensure the ordering + * remains correct and no writes are lost. + */ +#define BNXT_CP_DISABLE_DB(ring) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, 0, \ + (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ + htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_MASK)); \ +} while (0) + +#define BNXT_CP_ENABLE_DB(ring) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, 0, \ + (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ + htole32(CMPL_DOORBELL_KEY_CMPL)); \ +} while (0) + +#define BNXT_CP_IDX_ENABLE_DB(ring, cons) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ + htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ + (cons))); \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, 0, \ + (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ +} while (0) + +#define BNXT_CP_IDX_DISABLE_DB(ring, cons) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, \ + htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \ + CMPL_DOORBELL_MASK | (cons))); \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, 0, \ + (ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \ +} while (0) + +#define BNXT_TX_DB(ring, idx) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4( \ + (ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, \ + (ring)->doorbell, htole32(TX_DOORBELL_KEY_TX | (idx))); \ +} while (0) + +#define BNXT_RX_DB(ring, idx) do { \ + bus_space_barrier((ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \ + BUS_SPACE_BARRIER_WRITE); \ + bus_space_write_4( \ + (ring)->softc->doorbell_bar.tag, \ + (ring)->softc->doorbell_bar.handle, \ + (ring)->doorbell, htole32(RX_DOORBELL_KEY_RX | (idx))); \ +} while (0) + +/* Lock macros */ +#define BNXT_HWRM_LOCK_INIT(_softc, _name) \ + mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) +#define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) +#define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) +#define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) +#define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ + MA_OWNED) + +/* Chip info */ +#define BNXT_TSO_SIZE UINT16_MAX + +/* NVRAM access */ +enum bnxt_nvm_directory_type { + BNX_DIR_TYPE_UNUSED = 0, + BNX_DIR_TYPE_PKG_LOG = 1, + BNX_DIR_TYPE_UPDATE = 2, + BNX_DIR_TYPE_CHIMP_PATCH = 3, + BNX_DIR_TYPE_BOOTCODE = 4, + BNX_DIR_TYPE_VPD = 5, + BNX_DIR_TYPE_EXP_ROM_MBA = 6, + BNX_DIR_TYPE_AVS = 7, + BNX_DIR_TYPE_PCIE = 8, + BNX_DIR_TYPE_PORT_MACRO = 9, + BNX_DIR_TYPE_APE_FW = 10, + BNX_DIR_TYPE_APE_PATCH = 11, + BNX_DIR_TYPE_KONG_FW = 12, + BNX_DIR_TYPE_KONG_PATCH = 13, + BNX_DIR_TYPE_BONO_FW = 14, + BNX_DIR_TYPE_BONO_PATCH = 15, + BNX_DIR_TYPE_TANG_FW = 16, + BNX_DIR_TYPE_TANG_PATCH = 17, + BNX_DIR_TYPE_BOOTCODE_2 = 18, + BNX_DIR_TYPE_CCM = 19, + BNX_DIR_TYPE_PCI_CFG = 20, + BNX_DIR_TYPE_TSCF_UCODE = 21, + BNX_DIR_TYPE_ISCSI_BOOT = 22, + BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, + BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, + BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, + BNX_DIR_TYPE_EXT_PHY = 27, + BNX_DIR_TYPE_SHARED_CFG = 40, + BNX_DIR_TYPE_PORT_CFG = 41, + BNX_DIR_TYPE_FUNC_CFG = 42, + BNX_DIR_TYPE_MGMT_CFG = 48, + BNX_DIR_TYPE_MGMT_DATA = 49, + BNX_DIR_TYPE_MGMT_WEB_DATA = 50, + BNX_DIR_TYPE_MGMT_WEB_META = 51, + BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, + BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 +}; + +enum bnxnvm_pkglog_field_index { + BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, + BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, + BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, + BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, + BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, + BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, + BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 +}; + +#define BNX_DIR_ORDINAL_FIRST 0 +#define BNX_DIR_EXT_NONE 0 + +struct bnxt_bar_info { + struct resource *res; + bus_space_tag_t tag; + bus_space_handle_t handle; + bus_size_t size; + int rid; +}; + +struct bnxt_link_info { + uint8_t media_type; + uint8_t transceiver; + uint8_t phy_addr; + uint8_t phy_link_status; + uint8_t wire_speed; + uint8_t loop_back; + uint8_t link_up; + uint8_t last_link_up; + uint8_t duplex; + uint8_t last_duplex; + uint8_t pause; + uint8_t last_pause; + uint8_t auto_pause; + uint8_t force_pause; + uint8_t duplex_setting; + uint8_t auto_mode; +#define PHY_VER_LEN 3 + uint8_t phy_ver[PHY_VER_LEN]; + uint8_t phy_type; + uint16_t link_speed; + uint16_t support_speeds; + uint16_t auto_link_speeds; + uint16_t auto_link_speed; + uint16_t force_link_speed; + uint32_t preemphasis; + + /* copy of requested setting */ + uint8_t autoneg; +#define BNXT_AUTONEG_SPEED 1 +#define BNXT_AUTONEG_FLOW_CTRL 2 + uint8_t req_duplex; + uint8_t req_flow_ctrl; + uint16_t req_link_speed; +}; + +enum bnxt_cp_type { + BNXT_DEFAULT, + BNXT_TX, + BNXT_RX, + BNXT_SHARED +}; + +struct bnxt_cos_queue { + uint8_t id; + uint8_t profile; +}; + +struct bnxt_func_info { + uint32_t fw_fid; + uint8_t mac_addr[ETHER_ADDR_LEN]; + uint16_t max_rsscos_ctxs; + uint16_t max_cp_rings; + uint16_t max_tx_rings; + uint16_t max_rx_rings; + uint16_t max_hw_ring_grps; + uint16_t max_irqs; + uint16_t max_l2_ctxs; + uint16_t max_vnics; + uint16_t max_stat_ctxs; +}; + +struct bnxt_pf_info { +#define BNXT_FIRST_PF_FID 1 +#define BNXT_FIRST_VF_FID 128 + uint8_t port_id; + uint32_t first_vf_id; + uint16_t active_vfs; + uint16_t max_vfs; + uint32_t max_encap_records; + uint32_t max_decap_records; + uint32_t max_tx_em_flows; + uint32_t max_tx_wm_flows; + uint32_t max_rx_em_flows; + uint32_t max_rx_wm_flows; + unsigned long *vf_event_bmap; + uint16_t hwrm_cmd_req_pages; + void *hwrm_cmd_req_addr[4]; + bus_addr_t hwrm_cmd_req_dma_addr[4]; +}; + +struct bnxt_vf_info { + uint16_t fw_fid; + uint8_t mac_addr[ETHER_ADDR_LEN]; + uint16_t max_rsscos_ctxs; + uint16_t max_cp_rings; + uint16_t max_tx_rings; + uint16_t max_rx_rings; + uint16_t max_hw_ring_grps; + uint16_t max_l2_ctxs; + uint16_t max_irqs; + uint16_t max_vnics; + uint16_t max_stat_ctxs; + uint32_t vlan; +#define BNXT_VF_QOS 0x1 +#define BNXT_VF_SPOOFCHK 0x2 +#define BNXT_VF_LINK_FORCED 0x4 +#define BNXT_VF_LINK_UP 0x8 + uint32_t flags; + uint32_t func_flags; /* func cfg flags */ + uint32_t min_tx_rate; + uint32_t max_tx_rate; + void *hwrm_cmd_req_addr; + bus_addr_t hwrm_cmd_req_dma_addr; +}; + +#define BNXT_FLAG_VF (1<<1) + +#define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) +#define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) + +struct bnxt_vlan_tag { + SLIST_ENTRY(bnxt_vlan_tag) next; + uint16_t tpid; + uint16_t tag; +}; + +struct bnxt_vnic_info { + uint16_t id; + uint16_t def_ring_grp; + uint16_t cos_rule; + uint16_t lb_rule; + uint16_t mru; + + uint32_t rx_mask; + bool vlan_only; + struct iflib_dma_info mc_list; + int mc_list_count; +#define BNXT_MAX_MC_ADDRS 16 + + uint32_t flags; +#define BNXT_VNIC_FLAG_DEFAULT 0x01 +#define BNXT_VNIC_FLAG_BD_STALL 0x02 +#define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 + + uint64_t filter_id; + uint32_t flow_id; + + uint16_t rss_id; + uint32_t rss_hash_type; + uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; + struct iflib_dma_info rss_hash_key_tbl; + struct iflib_dma_info rss_grp_tbl; + SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; + struct iflib_dma_info vlan_tag_list; +}; + +struct bnxt_grp_info { + uint16_t stats_ctx; + uint16_t grp_id; + uint16_t rx_ring_id; + uint16_t cp_ring_id; + uint16_t ag_ring_id; +}; + +struct bnxt_ring { + uint64_t paddr; + vm_offset_t doorbell; + caddr_t vaddr; + struct bnxt_softc *softc; + uint32_t ring_size; /* Must be a power of two */ + uint16_t id; /* Logical ID */ + uint16_t phys_id; +}; + +struct bnxt_cp_ring { + struct bnxt_ring ring; + struct if_irq irq; + uint32_t cons; + bool v_bit; /* Value of valid bit */ + struct ctx_hw_stats *stats; + uint32_t stats_ctx_id; + uint32_t last_idx; /* Used by RX rings only + * set to the last read pidx + */ +}; + +struct bnxt_full_tpa_start { + struct rx_tpa_start_cmpl low; + struct rx_tpa_start_cmpl_hi high; +}; + +/* All the version information for the part */ +#define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ +#define BNXT_NAME_SIZE 17 +struct bnxt_ver_info { + uint8_t hwrm_if_major; + uint8_t hwrm_if_minor; + uint8_t hwrm_if_update; + char hwrm_if_ver[BNXT_VERSTR_SIZE]; + char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; + char hwrm_fw_ver[BNXT_VERSTR_SIZE]; + char mgmt_fw_ver[BNXT_VERSTR_SIZE]; + char netctrl_fw_ver[BNXT_VERSTR_SIZE]; + char roce_fw_ver[BNXT_VERSTR_SIZE]; + char phy_ver[BNXT_VERSTR_SIZE]; + char pkg_ver[64]; + + char hwrm_fw_name[BNXT_NAME_SIZE]; + char mgmt_fw_name[BNXT_NAME_SIZE]; + char netctrl_fw_name[BNXT_NAME_SIZE]; + char roce_fw_name[BNXT_NAME_SIZE]; + char phy_vendor[BNXT_NAME_SIZE]; + char phy_partnumber[BNXT_NAME_SIZE]; + + uint16_t chip_num; + uint8_t chip_rev; + uint8_t chip_metal; + uint8_t chip_bond_id; + uint8_t chip_type; + + uint8_t hwrm_min_major; + uint8_t hwrm_min_minor; + uint8_t hwrm_min_update; + + struct sysctl_ctx_list ver_ctx; + struct sysctl_oid *ver_oid; +}; + +struct bnxt_nvram_info { + uint16_t mfg_id; + uint16_t device_id; + uint32_t sector_size; + uint32_t size; + uint32_t reserved_size; + uint32_t available_size; + + struct sysctl_ctx_list nvm_ctx; + struct sysctl_oid *nvm_oid; +}; + +struct bnxt_softc { + device_t dev; + if_ctx_t ctx; + if_softc_ctx_t scctx; + if_shared_ctx_t sctx; + struct ifmedia *media; + + struct bnxt_bar_info hwrm_bar; + struct bnxt_bar_info doorbell_bar; + struct bnxt_link_info link_info; +#define BNXT_FLAG_NPAR 1 + uint32_t flags; + uint32_t total_msix; + + struct bnxt_func_info func; + struct bnxt_pf_info pf; + struct bnxt_vf_info vf; + + uint16_t hwrm_cmd_seq; + uint32_t hwrm_cmd_timeo; /* milliseconds */ + struct iflib_dma_info hwrm_cmd_resp; + /* Interrupt info for HWRM */ + struct if_irq irq; + struct mtx hwrm_lock; + uint16_t hwrm_max_req_len; + +#define BNXT_MAX_QUEUE 8 + uint8_t max_tc; + struct bnxt_cos_queue q_info[BNXT_MAX_QUEUE]; + + struct iflib_dma_info hw_rx_port_stats; + struct iflib_dma_info hw_tx_port_stats; + struct rx_port_stats *rx_port_stats; + struct tx_port_stats *tx_port_stats; + + int num_cp_rings; + + struct bnxt_ring *tx_rings; + struct bnxt_cp_ring *tx_cp_rings; + struct iflib_dma_info tx_stats; + int ntxqsets; + + struct bnxt_vnic_info vnic_info; + struct bnxt_ring *ag_rings; + struct bnxt_ring *rx_rings; + struct bnxt_cp_ring *rx_cp_rings; + struct bnxt_grp_info *grp_info; + struct iflib_dma_info rx_stats; + int nrxqsets; + + struct bnxt_cp_ring def_cp_ring; + struct iflib_dma_info def_cp_ring_mem; + struct grouptask def_cp_task; + + struct sysctl_ctx_list hw_stats; + struct sysctl_oid *hw_stats_oid; + + struct bnxt_full_tpa_start *tpa_start; + struct bnxt_ver_info *ver_info; + struct bnxt_nvram_info *nvm_info; +}; + +struct bnxt_filter_info { + STAILQ_ENTRY(bnxt_filter_info) next; + uint64_t fw_l2_filter_id; +#define INVALID_MAC_INDEX ((uint16_t)-1) + uint16_t mac_index; + + /* Filter Characteristics */ + uint32_t flags; + uint32_t enables; + uint8_t l2_addr[ETHER_ADDR_LEN]; + uint8_t l2_addr_mask[ETHER_ADDR_LEN]; + uint16_t l2_ovlan; + uint16_t l2_ovlan_mask; + uint16_t l2_ivlan; + uint16_t l2_ivlan_mask; + uint8_t t_l2_addr[ETHER_ADDR_LEN]; + uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; + uint16_t t_l2_ovlan; + uint16_t t_l2_ovlan_mask; + uint16_t t_l2_ivlan; + uint16_t t_l2_ivlan_mask; + uint8_t tunnel_type; + uint16_t mirror_vnic_id; + uint32_t vni; + uint8_t pri_hint; + uint64_t l2_filter_id_hint; +}; + +/* Function declarations */ +void bnxt_report_link(struct bnxt_softc *softc); +bool bnxt_check_hwrm_version(struct bnxt_softc *softc); + +#endif /* _BNXT_H */ Index: sys/dev/bnxt/bnxt_hwrm.h =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_hwrm.h @@ -0,0 +1,103 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#ifndef _BNXT_HWRM_H +#define _BNXT_HWRM_H + +/* HWRM Function Prototypes */ +int bnxt_alloc_hwrm_dma_mem(struct bnxt_softc *softc); +void bnxt_free_hwrm_dma_mem(struct bnxt_softc *softc); +int bnxt_hwrm_ring_alloc(struct bnxt_softc *softc, uint8_t type, + struct bnxt_ring *ring, uint16_t cmpl_ring_id, uint32_t stat_ctx_id, + bool irq); +int bnxt_hwrm_ver_get(struct bnxt_softc *softc); +int bnxt_hwrm_queue_qportcfg(struct bnxt_softc *softc); +int bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *softc); +int bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown); +int bnxt_hwrm_func_qcaps(struct bnxt_softc *softc); +int bnxt_hwrm_func_reset(struct bnxt_softc *softc); +int bnxt_hwrm_set_link_setting(struct bnxt_softc *, bool set_pause, + bool set_eee); +int bnxt_hwrm_set_pause(struct bnxt_softc *softc); +int bnxt_hwrm_vnic_ctx_alloc(struct bnxt_softc *softc, uint16_t *ctx_id); +int bnxt_hwrm_vnic_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); +int bnxt_hwrm_stat_ctx_alloc(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr, + uint64_t paddr); +int bnxt_hwrm_ring_grp_alloc(struct bnxt_softc *softc, + struct bnxt_grp_info *grp); +int bnxt_hwrm_vnic_alloc(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); +int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt_softc *softc, + struct bnxt_vnic_info *vnic); +int bnxt_hwrm_set_filter(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic); +int bnxt_hwrm_rss_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic, + uint32_t hash_type); +int bnxt_hwrm_func_cfg(struct bnxt_softc *softc); +int bnxt_hwrm_vnic_tpa_cfg(struct bnxt_softc *softc, + struct bnxt_vnic_info *vnic, uint32_t flags); +int bnxt_hwrm_nvm_find_dir_entry(struct bnxt_softc *softc, uint16_t type, + uint16_t *ordinal, uint16_t ext, uint16_t *index, bool use_index, + uint8_t search_opt, uint32_t *data_length, uint32_t *item_length, + uint32_t *fw_ver); +int bnxt_hwrm_nvm_read(struct bnxt_softc *softc, uint16_t index, + uint32_t offset, uint32_t length, struct iflib_dma_info *data); +int bnxt_hwrm_nvm_modify(struct bnxt_softc *softc, uint16_t index, + uint32_t offset, void *data, bool cpyin, uint32_t length); +int bnxt_hwrm_fw_reset(struct bnxt_softc *softc, uint8_t processor, + uint8_t *selfreset); +int bnxt_hwrm_fw_qstatus(struct bnxt_softc *softc, uint8_t type, + uint8_t *selfreset); +int bnxt_hwrm_nvm_write(struct bnxt_softc *softc, void *data, bool cpyin, + uint16_t type, uint16_t ordinal, uint16_t ext, uint16_t attr, + uint16_t option, uint32_t data_length, bool keep, uint32_t *item_length, + uint16_t *index); +int bnxt_hwrm_nvm_erase_dir_entry(struct bnxt_softc *softc, uint16_t index); +int bnxt_hwrm_nvm_get_dir_info(struct bnxt_softc *softc, uint32_t *entries, + uint32_t *entry_length); +int bnxt_hwrm_nvm_get_dir_entries(struct bnxt_softc *softc, + uint32_t *entries, uint32_t *entry_length, struct iflib_dma_info *dma_data); +int bnxt_hwrm_nvm_get_dev_info(struct bnxt_softc *softc, uint16_t *mfg_id, + uint16_t *device_id, uint32_t *sector_size, uint32_t *nvram_size, + uint32_t *reserved_size, uint32_t *available_size); +int bnxt_hwrm_nvm_install_update(struct bnxt_softc *softc, + uint32_t install_type, uint64_t *installed_items, uint8_t *result, + uint8_t *problem_item, uint8_t *reset_required); +int bnxt_hwrm_nvm_verify_update(struct bnxt_softc *softc, uint16_t type, + uint16_t ordinal, uint16_t ext); +int bnxt_hwrm_fw_get_time(struct bnxt_softc *softc, uint16_t *year, + uint8_t *month, uint8_t *day, uint8_t *hour, uint8_t *minute, + uint8_t *second, uint16_t *millisecond, uint16_t *zone); +int bnxt_hwrm_fw_set_time(struct bnxt_softc *softc, uint16_t year, + uint8_t month, uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, + uint16_t millisecond, uint16_t zone); +int bnxt_hwrm_port_phy_qcfg(struct bnxt_softc *softc); + +#endif Index: sys/dev/bnxt/bnxt_hwrm.c =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_hwrm.c @@ -0,0 +1,1486 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include + +#include "bnxt.h" +#include "bnxt_hwrm.h" +#include "hsi_struct_def.h" + +static int bnxt_hwrm_err_map(uint16_t err); +static inline int _is_valid_ether_addr(uint8_t *); +static inline void get_random_ether_addr(uint8_t *); +static void bnxt_hwrm_set_link_common(struct bnxt_softc *softc, + struct hwrm_port_phy_cfg_input *req); +static void bnxt_hwrm_set_pause_common(struct bnxt_softc *softc, + struct hwrm_port_phy_cfg_input *req); +static void bnxt_hwrm_set_eee(struct bnxt_softc *softc, + struct hwrm_port_phy_cfg_input *req); +static int _hwrm_send_message(struct bnxt_softc *, void *, uint32_t); +static int hwrm_send_message(struct bnxt_softc *, void *, uint32_t); +static void bnxt_hwrm_cmd_hdr_init(struct bnxt_softc *, void *, uint16_t); + +/* NVRam stuff has a five minute timeout */ +#define BNXT_NVM_TIMEO (5 * 60 * 1000) + +static int +bnxt_hwrm_err_map(uint16_t err) +{ + int rc; + + switch (err) { + case HWRM_ERR_CODE_SUCCESS: + return 0; + case HWRM_ERR_CODE_INVALID_PARAMS: + case HWRM_ERR_CODE_INVALID_FLAGS: + case HWRM_ERR_CODE_INVALID_ENABLES: + return EINVAL; + case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED: + return EACCES; + case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR: + return ENOMEM; + case HWRM_ERR_CODE_CMD_NOT_SUPPORTED: + return ENOSYS; + case HWRM_ERR_CODE_FAIL: + return EIO; + case HWRM_ERR_CODE_HWRM_ERROR: + case HWRM_ERR_CODE_UNKNOWN_ERR: + default: + return EDOOFUS; + } + + return rc; +} + +int +bnxt_alloc_hwrm_dma_mem(struct bnxt_softc *softc) +{ + int rc; + + rc = iflib_dma_alloc(softc->ctx, PAGE_SIZE, &softc->hwrm_cmd_resp, + BUS_DMA_NOWAIT); + return rc; +} + +void +bnxt_free_hwrm_dma_mem(struct bnxt_softc *softc) +{ + if (softc->hwrm_cmd_resp.idi_vaddr) + iflib_dma_free(&softc->hwrm_cmd_resp); + softc->hwrm_cmd_resp.idi_vaddr = NULL; + return; +} + +static void +bnxt_hwrm_cmd_hdr_init(struct bnxt_softc *softc, void *request, + uint16_t req_type) +{ + struct input *req = request; + + req->req_type = htole16(req_type); + req->cmpl_ring = 0xffff; + req->target_id = 0xffff; + req->resp_addr = htole64(softc->hwrm_cmd_resp.idi_paddr); +} + +static int +_hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len) +{ + struct input *req = msg; + struct hwrm_err_output *resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + uint32_t *data = msg; + int i; + uint16_t cp_ring_id; + uint8_t *valid; + uint16_t err; + + /* TODO: DMASYNC in here. */ + req->seq_id = htole16(softc->hwrm_cmd_seq++); + memset(resp, 0, PAGE_SIZE); + cp_ring_id = le16toh(req->cmpl_ring); + + /* Write request msg to hwrm channel */ + for (i = 0; i < msg_len; i += 4) { + bus_space_write_4(softc->hwrm_bar.tag, + softc->hwrm_bar.handle, + i, *data); + data++; + } + + /* Clear to the end of the request buffer */ + for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4) + bus_space_write_4(softc->hwrm_bar.tag, softc->hwrm_bar.handle, + i, 0); + + /* Ring channel doorbell */ + bus_space_write_4(softc->hwrm_bar.tag, + softc->hwrm_bar.handle, + 0x100, htole32(1)); + + /* Check if response len is updated */ + for (i = 0; i < softc->hwrm_cmd_timeo; i++) { + if (resp->resp_len && resp->resp_len <= 4096) + break; + DELAY(1000); + } + if (i >= softc->hwrm_cmd_timeo) { + device_printf(softc->dev, + "Timeout sending %s: (timeout: %u) seq: %d\n", + GET_HWRM_REQ_TYPE(req->req_type), softc->hwrm_cmd_timeo, + le16toh(req->seq_id)); + return ETIMEDOUT; + } + /* Last byte of resp contains the valid key */ + valid = (uint8_t *)resp + resp->resp_len - 1; + for (i = 0; i < softc->hwrm_cmd_timeo; i++) { + if (*valid == HWRM_RESP_VALID_KEY) + break; + DELAY(1000); + } + if (i >= softc->hwrm_cmd_timeo) { + device_printf(softc->dev, "Timeout sending %s: " + "(timeout: %u) msg {0x%x 0x%x} len:%d v: %d\n", + GET_HWRM_REQ_TYPE(req->req_type), + softc->hwrm_cmd_timeo, le16toh(req->req_type), + le16toh(req->seq_id), msg_len, + *valid); + return ETIMEDOUT; + } + + err = le16toh(resp->error_code); + if (err) { + /* HWRM_ERR_CODE_FAIL is a "normal" error, don't log */ + if (err != HWRM_ERR_CODE_FAIL) { + device_printf(softc->dev, + "%s command returned %s error.\n", + GET_HWRM_REQ_TYPE(req->req_type), + GET_HWRM_ERROR_CODE(err)); + } + return bnxt_hwrm_err_map(err); + } + + return 0; +} + +static int +hwrm_send_message(struct bnxt_softc *softc, void *msg, uint32_t msg_len) +{ + int rc; + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, msg, msg_len); + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_queue_qportcfg(struct bnxt_softc *softc) +{ + struct hwrm_queue_qportcfg_input req = {0}; + struct hwrm_queue_qportcfg_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + + int rc = 0; + uint8_t *qptr; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_QUEUE_QPORTCFG); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto qportcfg_exit; + + if (!resp->max_configurable_queues) { + rc = -EINVAL; + goto qportcfg_exit; + } + softc->max_tc = resp->max_configurable_queues; + if (softc->max_tc > BNXT_MAX_QUEUE) + softc->max_tc = BNXT_MAX_QUEUE; + + qptr = &resp->queue_id0; + for (int i = 0; i < softc->max_tc; i++) { + softc->q_info[i].id = *qptr++; + softc->q_info[i].profile = *qptr++; + } + +qportcfg_exit: + BNXT_HWRM_UNLOCK(softc); + return (rc); +} + + +int +bnxt_hwrm_ver_get(struct bnxt_softc *softc) +{ + struct hwrm_ver_get_input req = {0}; + struct hwrm_ver_get_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + const char nastr[] = ""; + const char naver[] = ""; + + softc->hwrm_max_req_len = HWRM_MAX_REQ_LEN; + softc->hwrm_cmd_timeo = 1000; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VER_GET); + + req.hwrm_intf_maj = HWRM_VERSION_MAJOR; + req.hwrm_intf_min = HWRM_VERSION_MINOR; + req.hwrm_intf_upd = HWRM_VERSION_UPDATE; + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + snprintf(softc->ver_info->hwrm_if_ver, BNXT_VERSTR_SIZE, "%d.%d.%d", + resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd); + softc->ver_info->hwrm_if_major = resp->hwrm_intf_maj; + softc->ver_info->hwrm_if_minor = resp->hwrm_intf_min; + softc->ver_info->hwrm_if_update = resp->hwrm_intf_upd; + snprintf(softc->ver_info->hwrm_fw_ver, BNXT_VERSTR_SIZE, "%d.%d.%d", + resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld); + strlcpy(softc->ver_info->driver_hwrm_if_ver, HWRM_VERSION_STR, + BNXT_VERSTR_SIZE); + strlcpy(softc->ver_info->hwrm_fw_name, resp->hwrm_fw_name, + BNXT_NAME_SIZE); + + if (resp->mgmt_fw_maj == 0 && resp->mgmt_fw_min == 0 && + resp->mgmt_fw_bld == 0) { + strlcpy(softc->ver_info->mgmt_fw_ver, naver, BNXT_VERSTR_SIZE); + strlcpy(softc->ver_info->mgmt_fw_name, nastr, BNXT_NAME_SIZE); + } + else { + snprintf(softc->ver_info->mgmt_fw_ver, BNXT_VERSTR_SIZE, + "%d.%d.%d", resp->mgmt_fw_maj, resp->mgmt_fw_min, + resp->mgmt_fw_bld); + strlcpy(softc->ver_info->mgmt_fw_name, resp->mgmt_fw_name, + BNXT_NAME_SIZE); + } + if (resp->netctrl_fw_maj == 0 && resp->netctrl_fw_min == 0 && + resp->netctrl_fw_bld == 0) { + strlcpy(softc->ver_info->netctrl_fw_ver, naver, + BNXT_VERSTR_SIZE); + strlcpy(softc->ver_info->netctrl_fw_name, nastr, + BNXT_NAME_SIZE); + } + else { + snprintf(softc->ver_info->netctrl_fw_ver, BNXT_VERSTR_SIZE, + "%d.%d.%d", resp->netctrl_fw_maj, resp->netctrl_fw_min, + resp->netctrl_fw_bld); + strlcpy(softc->ver_info->netctrl_fw_name, resp->netctrl_fw_name, + BNXT_NAME_SIZE); + } + if (resp->roce_fw_maj == 0 && resp->roce_fw_min == 0 && + resp->roce_fw_bld == 0) { + strlcpy(softc->ver_info->roce_fw_ver, naver, BNXT_VERSTR_SIZE); + strlcpy(softc->ver_info->roce_fw_name, nastr, BNXT_NAME_SIZE); + } + else { + snprintf(softc->ver_info->roce_fw_ver, BNXT_VERSTR_SIZE, + "%d.%d.%d", resp->roce_fw_maj, resp->roce_fw_min, + resp->roce_fw_bld); + strlcpy(softc->ver_info->roce_fw_name, resp->roce_fw_name, + BNXT_NAME_SIZE); + } + softc->ver_info->chip_num = le16toh(resp->chip_num); + softc->ver_info->chip_rev = resp->chip_rev; + softc->ver_info->chip_metal = resp->chip_metal; + softc->ver_info->chip_bond_id = resp->chip_bond_id; + softc->ver_info->chip_type = resp->chip_platform_type; + + if (resp->max_req_win_len) + softc->hwrm_max_req_len = le16toh(resp->max_req_win_len); + if (resp->def_req_timeout) + softc->hwrm_cmd_timeo = le16toh(resp->def_req_timeout); + +fail: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_func_drv_rgtr(struct bnxt_softc *softc) +{ + struct hwrm_func_drv_rgtr_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_DRV_RGTR); + + req.enables = htole32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER | + HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE); + req.os_type = htole16(HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD); + + req.ver_maj = __FreeBSD_version / 100000; + req.ver_min = (__FreeBSD_version / 1000) % 100; + req.ver_upd = (__FreeBSD_version / 100) % 10; + + return hwrm_send_message(softc, &req, sizeof(req)); +} + + +int +bnxt_hwrm_func_drv_unrgtr(struct bnxt_softc *softc, bool shutdown) +{ + struct hwrm_func_drv_unrgtr_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_DRV_UNRGTR); + if (shutdown == true) + req.flags |= + HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN; + return hwrm_send_message(softc, &req, sizeof(req)); +} + + +static inline int +_is_valid_ether_addr(uint8_t *addr) +{ + char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; + + if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) + return (FALSE); + + return (TRUE); +} + +static inline void +get_random_ether_addr(uint8_t *addr) +{ + uint8_t temp[ETHER_ADDR_LEN]; + + arc4rand(&temp, sizeof(temp), 0); + temp[0] &= 0xFE; + temp[0] |= 0x02; + bcopy(temp, addr, sizeof(temp)); +} + +int +bnxt_hwrm_func_qcaps(struct bnxt_softc *softc) +{ + int rc = 0; + struct hwrm_func_qcaps_input req = {0}; + struct hwrm_func_qcaps_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + struct bnxt_func_info *func = &softc->func; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_QCAPS); + req.fid = htole16(0xffff); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + func->fw_fid = le16toh(resp->fid); + memcpy(func->mac_addr, resp->mac_address, ETHER_ADDR_LEN); + func->max_rsscos_ctxs = le16toh(resp->max_rsscos_ctx); + func->max_cp_rings = le16toh(resp->max_cmpl_rings); + func->max_tx_rings = le16toh(resp->max_tx_rings); + func->max_rx_rings = le16toh(resp->max_rx_rings); + func->max_hw_ring_grps = le32toh(resp->max_hw_ring_grps); + if (!func->max_hw_ring_grps) + func->max_hw_ring_grps = func->max_tx_rings; + func->max_l2_ctxs = le16toh(resp->max_l2_ctxs); + func->max_vnics = le16toh(resp->max_vnics); + func->max_stat_ctxs = le16toh(resp->max_stat_ctx); + if (BNXT_PF(softc)) { + struct bnxt_pf_info *pf = &softc->pf; + + pf->port_id = le16toh(resp->port_id); + pf->first_vf_id = le16toh(resp->first_vf_id); + pf->max_vfs = le16toh(resp->max_vfs); + pf->max_encap_records = le32toh(resp->max_encap_records); + pf->max_decap_records = le32toh(resp->max_decap_records); + pf->max_tx_em_flows = le32toh(resp->max_tx_em_flows); + pf->max_tx_wm_flows = le32toh(resp->max_tx_wm_flows); + pf->max_rx_em_flows = le32toh(resp->max_rx_em_flows); + pf->max_rx_wm_flows = le32toh(resp->max_rx_wm_flows); + } + if (!_is_valid_ether_addr(func->mac_addr)) { + device_printf(softc->dev, "Invalid ethernet address, generating random locally administered address"); + get_random_ether_addr(func->mac_addr); + } + +fail: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_func_reset(struct bnxt_softc *softc) +{ + struct hwrm_func_reset_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_RESET); + req.enables = 0; + + return hwrm_send_message(softc, &req, sizeof(req)); +} + +static void +bnxt_hwrm_set_link_common(struct bnxt_softc *softc, + struct hwrm_port_phy_cfg_input *req) +{ + uint8_t autoneg = softc->link_info.autoneg; + uint16_t fw_link_speed = softc->link_info.req_link_speed; + + if (autoneg & BNXT_AUTONEG_SPEED) { + req->auto_mode |= + HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS; + + req->enables |= + htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE); + req->flags |= + htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG); + } else { + req->force_link_speed = htole16(fw_link_speed); + req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE); + } + + /* tell chimp that the setting takes effect immediately */ + req->flags |= htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY); +} + + +static void +bnxt_hwrm_set_pause_common(struct bnxt_softc *softc, + struct hwrm_port_phy_cfg_input *req) +{ + if (softc->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { + req->auto_pause = + HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE; + if (softc->link_info.req_flow_ctrl & + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX) + req->auto_pause |= + HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; + if (softc->link_info.req_flow_ctrl & + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX) + req->auto_pause |= + HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; + req->enables |= + htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE); + } else { + if (softc->link_info.req_flow_ctrl & + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX) + req->force_pause |= + HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; + if (softc->link_info.req_flow_ctrl & + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX) + req->force_pause |= + HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; + req->enables |= + htole32(HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE); + req->auto_pause = req->force_pause; + req->enables |= htole32( + HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE); + } +} + + +/* JFV this needs interface connection */ +static void +bnxt_hwrm_set_eee(struct bnxt_softc *softc, struct hwrm_port_phy_cfg_input *req) +{ + /* struct ethtool_eee *eee = &softc->eee; */ + bool eee_enabled = false; + + if (eee_enabled) { +#if 0 + uint16_t eee_speeds; + uint32_t flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE; + + if (eee->tx_lpi_enabled) + flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI; + + req->flags |= htole32(flags); + eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised); + req->eee_link_speed_mask = htole16(eee_speeds); + req->tx_lpi_timer = htole32(eee->tx_lpi_timer); +#endif + } else { + req->flags |= + htole32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE); + } +} + + +int +bnxt_hwrm_set_link_setting(struct bnxt_softc *softc, bool set_pause, + bool set_eee) +{ + struct hwrm_port_phy_cfg_input req = {0}; + + if (softc->flags & BNXT_FLAG_NPAR) + return ENOTSUP; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_CFG); + if (set_pause) + bnxt_hwrm_set_pause_common(softc, &req); + + bnxt_hwrm_set_link_common(softc, &req); + if (set_eee) + bnxt_hwrm_set_eee(softc, &req); + return hwrm_send_message(softc, &req, sizeof(req)); +} + + +int +bnxt_hwrm_set_pause(struct bnxt_softc *softc) +{ + struct hwrm_port_phy_cfg_input req = {0}; + int rc; + + if (softc->flags & BNXT_FLAG_NPAR) + return ENOTSUP; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_CFG); + bnxt_hwrm_set_pause_common(softc, &req); + + if (softc->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) + bnxt_hwrm_set_link_common(softc, &req); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (!rc && !(softc->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { + /* since changing of pause setting doesn't trigger any link + * change event, the driver needs to update the current pause + * result upon successfully return of the phy_cfg command */ + softc->link_info.pause = + softc->link_info.force_pause = softc->link_info.req_flow_ctrl; + softc->link_info.auto_pause = 0; + bnxt_report_link(softc); + } + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_vnic_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) +{ + struct hwrm_vnic_cfg_input req = {0}; + struct hwrm_vnic_cfg_output *resp; + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_CFG); + + if (vnic->flags & BNXT_VNIC_FLAG_DEFAULT) + req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT); + if (vnic->flags & BNXT_VNIC_FLAG_BD_STALL) + req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE); + if (vnic->flags & BNXT_VNIC_FLAG_VLAN_STRIP) + req.flags |= htole32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE); + req.enables = htole32(HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP | + HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE | + HWRM_VNIC_CFG_INPUT_ENABLES_MRU); + req.vnic_id = htole16(vnic->id); + req.dflt_ring_grp = htole16(vnic->def_ring_grp); + req.rss_rule = htole16(vnic->rss_id); + req.cos_rule = htole16(vnic->cos_rule); + req.lb_rule = htole16(vnic->lb_rule); + req.mru = htole16(vnic->mru); + + return hwrm_send_message(softc, &req, sizeof(req)); +} + +int +bnxt_hwrm_vnic_alloc(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) +{ + struct hwrm_vnic_alloc_input req = {0}; + struct hwrm_vnic_alloc_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + + if (vnic->id != (uint16_t)HWRM_NA_SIGNATURE) { + device_printf(softc->dev, + "Attempt to re-allocate vnic %04x\n", vnic->id); + return EDOOFUS; + } + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_ALLOC); + + if (vnic->flags & BNXT_VNIC_FLAG_DEFAULT) + req.flags = htole32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + vnic->id = le32toh(resp->vnic_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + return (rc); +} + +int +bnxt_hwrm_vnic_ctx_alloc(struct bnxt_softc *softc, uint16_t *ctx_id) +{ + struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; + struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + + if (*ctx_id != (uint16_t)HWRM_NA_SIGNATURE) { + device_printf(softc->dev, + "Attempt to re-allocate vnic ctx %04x\n", *ctx_id); + return EDOOFUS; + } + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + *ctx_id = le32toh(resp->rss_cos_lb_ctx_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + return (rc); +} + +int +bnxt_hwrm_ring_grp_alloc(struct bnxt_softc *softc, struct bnxt_grp_info *grp) +{ + struct hwrm_ring_grp_alloc_input req = {0}; + struct hwrm_ring_grp_alloc_output *resp; + int rc = 0; + + if (grp->grp_id != (uint16_t)HWRM_NA_SIGNATURE) { + device_printf(softc->dev, + "Attempt to re-allocate ring group %04x\n", grp->grp_id); + return EDOOFUS; + } + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_GRP_ALLOC); + req.cr = htole16(grp->cp_ring_id); + req.rr = htole16(grp->rx_ring_id); + req.ar = htole16(grp->ag_ring_id); + req.sc = htole16(grp->stats_ctx); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + grp->grp_id = le32toh(resp->ring_group_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +/* + * Ring allocation message to the firmware + */ +int +bnxt_hwrm_ring_alloc(struct bnxt_softc *softc, uint8_t type, + struct bnxt_ring *ring, uint16_t cmpl_ring_id, uint32_t stat_ctx_id, + bool irq) +{ + struct hwrm_ring_alloc_input req = {0}; + struct hwrm_ring_alloc_output *resp; + int rc; + + if (ring->phys_id != (uint16_t)HWRM_NA_SIGNATURE) { + device_printf(softc->dev, + "Attempt to re-allocate ring %04x\n", ring->phys_id); + return EDOOFUS; + } + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_RING_ALLOC); + req.enables = htole32(0); + req.fbo = htole32(0); + + if (stat_ctx_id != HWRM_NA_SIGNATURE) { + req.enables |= htole32( + HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID); + req.stat_ctx_id = htole32(stat_ctx_id); + } + req.ring_type = type; + req.page_tbl_addr = htole64(ring->paddr); + req.length = htole32(ring->ring_size); + req.logical_id = htole16(ring->id); + req.cmpl_ring_id = htole16(cmpl_ring_id); + req.queue_id = htole16(softc->q_info[0].id); +#if 0 + /* MODE_POLL appears to crash the firmware */ + if (irq) + req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX; + else + req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_POLL; +#else + req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX; +#endif + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + ring->phys_id = le16toh(resp->ring_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_stat_ctx_alloc(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr, + uint64_t paddr) +{ + struct hwrm_stat_ctx_alloc_input req = {0}; + struct hwrm_stat_ctx_alloc_output *resp; + int rc = 0; + + if (cpr->stats_ctx_id != HWRM_NA_SIGNATURE) { + device_printf(softc->dev, + "Attempt to re-allocate stats ctx %08x\n", + cpr->stats_ctx_id); + return EDOOFUS; + } + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_STAT_CTX_ALLOC); + + req.update_period_ms = htole32(1000); + req.stats_dma_addr = htole64(paddr); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + cpr->stats_ctx_id = le32toh(resp->stat_ctx_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + + return rc; +} + +int +bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt_softc *softc, + struct bnxt_vnic_info *vnic) +{ + struct hwrm_cfa_l2_set_rx_mask_input req = {0}; + struct bnxt_vlan_tag *tag; + uint32_t *tags; + uint32_t num_vlan_tags = 0;; + uint32_t i; + uint32_t mask = vnic->rx_mask; + int rc; + + SLIST_FOREACH(tag, &vnic->vlan_tags, next) + num_vlan_tags++; + + if (num_vlan_tags) { + if (!(mask & + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN)) { + if (!vnic->vlan_only) + mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN; + else + mask |= + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY; + } + if (vnic->vlan_tag_list.idi_vaddr) { + iflib_dma_free(&vnic->vlan_tag_list); + vnic->vlan_tag_list.idi_vaddr = NULL; + } + rc = iflib_dma_alloc(softc->ctx, 4 * num_vlan_tags, + &vnic->vlan_tag_list, BUS_DMA_NOWAIT); + if (rc) + return rc; + tags = (uint32_t *)vnic->vlan_tag_list.idi_vaddr; + + i = 0; + SLIST_FOREACH(tag, &vnic->vlan_tags, next) { + tags[i] = htole32((tag->tpid << 16) | tag->tag); + i++; + } + } + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_CFA_L2_SET_RX_MASK); + + req.vnic_id = htole32(vnic->id); + req.mask = htole32(mask); + req.mc_tbl_addr = htole64(vnic->mc_list.idi_paddr); + req.num_mc_entries = htole32(vnic->mc_list_count); + req.vlan_tag_tbl_addr = htole64(vnic->vlan_tag_list.idi_paddr); + req.num_vlan_tags = htole32(num_vlan_tags); + return hwrm_send_message(softc, &req, sizeof(req)); +} + + +int +bnxt_hwrm_set_filter(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic) +{ + struct hwrm_cfa_l2_filter_alloc_input req = {0}; + struct hwrm_cfa_l2_filter_alloc_output *resp; + uint32_t enables = 0; + int rc = 0; + + if (vnic->filter_id != -1) { + device_printf(softc->dev, + "Attempt to re-allocate l2 ctx filter\n"); + return EDOOFUS; + } + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_CFA_L2_FILTER_ALLOC); + + req.flags = htole32(HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX); + enables = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR + | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK + | HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID; + req.enables = htole32(enables); + req.dst_id = htole16(vnic->id); + memcpy(req.l2_addr, if_getlladdr(iflib_get_ifp(softc->ctx)), + ETHER_ADDR_LEN); + memset(&req.l2_addr_mask, 0xff, sizeof(req.l2_addr_mask)); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto fail; + + vnic->filter_id = le64toh(resp->l2_filter_id); + vnic->flow_id = le64toh(resp->flow_id); + +fail: + BNXT_HWRM_UNLOCK(softc); + return (rc); +} + +int +bnxt_hwrm_rss_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic, + uint32_t hash_type) +{ + struct hwrm_vnic_rss_cfg_input req = {0}; + struct hwrm_vnic_rss_cfg_output *resp; + + resp = (void *)softc->hwrm_cmd_resp.idi_vaddr; + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_RSS_CFG); + + req.hash_type = htole32(hash_type); + req.ring_grp_tbl_addr = htole64(vnic->rss_grp_tbl.idi_paddr); + req.hash_key_tbl_addr = htole64(vnic->rss_hash_key_tbl.idi_paddr); + req.rss_ctx_idx = htole16(vnic->rss_id); + + return hwrm_send_message(softc, &req, sizeof(req)); +} + +int +bnxt_hwrm_func_cfg(struct bnxt_softc *softc) +{ + struct hwrm_func_cfg_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FUNC_CFG); + + req.fid = 0xffff; + req.enables = htole32(HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR); + + req.async_event_cr = softc->def_cp_ring.ring.phys_id; + + return hwrm_send_message(softc, &req, sizeof(req)); +} + +int +bnxt_hwrm_vnic_tpa_cfg(struct bnxt_softc *softc, struct bnxt_vnic_info *vnic, + uint32_t flags) +{ + struct hwrm_vnic_tpa_cfg_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_VNIC_TPA_CFG); + + req.flags = htole32(flags); + req.vnic_id = htole16(vnic->id); + req.enables = htole32(HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS | + HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS | + /* HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER | */ + HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN); + /* TODO: Calculate this based on ring size? */ + req.max_agg_segs = htole16(3); + /* Base this in the allocated TPA start size... */ + req.max_aggs = htole16(2); + /* + * TODO: max_agg_timer? + * req.mag_agg_timer = htole32(XXX); + */ + req.min_agg_len = htole32(0); + + return hwrm_send_message(softc, &req, sizeof(req)); +} + +int +bnxt_hwrm_nvm_find_dir_entry(struct bnxt_softc *softc, uint16_t type, + uint16_t *ordinal, uint16_t ext, uint16_t *index, bool use_index, + uint8_t search_opt, uint32_t *data_length, uint32_t *item_length, + uint32_t *fw_ver) +{ + struct hwrm_nvm_find_dir_entry_input req = {0}; + struct hwrm_nvm_find_dir_entry_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc = 0; + uint32_t old_timeo; + + MPASS(ordinal); + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_FIND_DIR_ENTRY); + if (use_index) { + req.enables = htole32( + HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID); + req.dir_idx = htole16(*index); + } + req.dir_type = htole16(type); + req.dir_ordinal = htole16(*ordinal); + req.dir_ext = htole16(ext); + req.opt_ordinal = search_opt; + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + if (rc) + goto exit; + + if (item_length) + *item_length = le32toh(resp->dir_item_length); + if (data_length) + *data_length = le32toh(resp->dir_data_length); + if (fw_ver) + *fw_ver = le32toh(resp->fw_ver); + *ordinal = le16toh(resp->dir_ordinal); + if (index) + *index = le16toh(resp->dir_idx); + +exit: + BNXT_HWRM_UNLOCK(softc); + return (rc); +} + +int +bnxt_hwrm_nvm_read(struct bnxt_softc *softc, uint16_t index, uint32_t offset, + uint32_t length, struct iflib_dma_info *data) +{ + struct hwrm_nvm_read_input req = {0}; + int rc; + uint32_t old_timeo; + + if (length > data->idi_size) { + rc = EINVAL; + goto exit; + } + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_READ); + req.host_dest_addr = htole64(data->idi_paddr); + req.dir_idx = htole16(index); + req.offset = htole32(offset); + req.len = htole32(length); + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + BNXT_HWRM_UNLOCK(softc); + if (rc) + goto exit; + bus_dmamap_sync(data->idi_tag, data->idi_map, BUS_DMASYNC_POSTREAD); + + goto exit; + +exit: + return rc; +} + +int +bnxt_hwrm_nvm_modify(struct bnxt_softc *softc, uint16_t index, uint32_t offset, + void *data, bool cpyin, uint32_t length) +{ + struct hwrm_nvm_modify_input req = {0}; + struct iflib_dma_info dma_data; + int rc; + uint32_t old_timeo; + + if (length == 0 || !data) + return EINVAL; + rc = iflib_dma_alloc(softc->ctx, length, &dma_data, + BUS_DMA_NOWAIT); + if (rc) + return ENOMEM; + if (cpyin) { + rc = copyin(data, dma_data.idi_vaddr, length); + if (rc) + goto exit; + } + else + memcpy(dma_data.idi_vaddr, data, length); + bus_dmamap_sync(dma_data.idi_tag, dma_data.idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_MODIFY); + req.host_src_addr = htole64(dma_data.idi_paddr); + req.dir_idx = htole16(index); + req.offset = htole32(offset); + req.len = htole32(length); + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + BNXT_HWRM_UNLOCK(softc); + +exit: + iflib_dma_free(&dma_data); + return rc; +} + +int +bnxt_hwrm_fw_reset(struct bnxt_softc *softc, uint8_t processor, + uint8_t *selfreset) +{ + struct hwrm_fw_reset_input req = {0}; + struct hwrm_fw_reset_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + + MPASS(selfreset); + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_RESET); + req.embedded_proc_type = processor; + req.selfrst_status = *selfreset; + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto exit; + *selfreset = resp->selfrst_status; + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_fw_qstatus(struct bnxt_softc *softc, uint8_t type, uint8_t *selfreset) +{ + struct hwrm_fw_qstatus_input req = {0}; + struct hwrm_fw_qstatus_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + + MPASS(selfreset); + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_QSTATUS); + req.embedded_proc_type = type; + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto exit; + *selfreset = resp->selfrst_status; + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_nvm_write(struct bnxt_softc *softc, void *data, bool cpyin, + uint16_t type, uint16_t ordinal, uint16_t ext, uint16_t attr, + uint16_t option, uint32_t data_length, bool keep, uint32_t *item_length, + uint16_t *index) +{ + struct hwrm_nvm_write_input req = {0}; + struct hwrm_nvm_write_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + struct iflib_dma_info dma_data; + int rc; + uint32_t old_timeo; + + if (data_length) { + rc = iflib_dma_alloc(softc->ctx, data_length, &dma_data, + BUS_DMA_NOWAIT); + if (rc) + return ENOMEM; + if (cpyin) { + rc = copyin(data, dma_data.idi_vaddr, data_length); + if (rc) + goto early_exit; + } + else + memcpy(dma_data.idi_vaddr, data, data_length); + bus_dmamap_sync(dma_data.idi_tag, dma_data.idi_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + else + dma_data.idi_paddr = 0; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_WRITE); + + req.host_src_addr = htole64(dma_data.idi_paddr); + req.dir_type = htole16(type); + req.dir_ordinal = htole16(ordinal); + req.dir_ext = htole16(ext); + req.dir_attr = htole16(attr); + req.dir_data_length = htole32(data_length); + req.option = htole16(option); + if (keep) { + req.flags = + htole16(HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG); + } + if (item_length) + req.dir_item_length = htole32(*item_length); + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + if (rc) + goto exit; + if (item_length) + *item_length = le32toh(resp->dir_item_length); + if (index) + *index = le16toh(resp->dir_idx); + +exit: + BNXT_HWRM_UNLOCK(softc); +early_exit: + if (data_length) + iflib_dma_free(&dma_data); + return rc; +} + +int +bnxt_hwrm_nvm_erase_dir_entry(struct bnxt_softc *softc, uint16_t index) +{ + struct hwrm_nvm_erase_dir_entry_input req = {0}; + uint32_t old_timeo; + int rc; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_ERASE_DIR_ENTRY); + req.dir_idx = htole16(index); + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_nvm_get_dir_info(struct bnxt_softc *softc, uint32_t *entries, + uint32_t *entry_length) +{ + struct hwrm_nvm_get_dir_info_input req = {0}; + struct hwrm_nvm_get_dir_info_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + uint32_t old_timeo; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DIR_INFO); + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + if (rc) + goto exit; + + if (entries) + *entries = le32toh(resp->entries); + if (entry_length) + *entry_length = le32toh(resp->entry_length); + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_nvm_get_dir_entries(struct bnxt_softc *softc, uint32_t *entries, + uint32_t *entry_length, struct iflib_dma_info *dma_data) +{ + struct hwrm_nvm_get_dir_entries_input req = {0}; + uint32_t ent; + uint32_t ent_len; + int rc; + uint32_t old_timeo; + + if (!entries) + entries = &ent; + if (!entry_length) + entry_length = &ent_len; + + rc = bnxt_hwrm_nvm_get_dir_info(softc, entries, entry_length); + if (rc) + goto exit; + if (*entries * *entry_length > dma_data->idi_size) { + rc = EINVAL; + goto exit; + } + + /* + * TODO: There's a race condition here that could blow up DMA memory... + * we need to allocate the max size, not the currently in use + * size. The command should totally have a max size here. + */ + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DIR_ENTRIES); + req.host_dest_addr = htole64(dma_data->idi_paddr); + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + BNXT_HWRM_UNLOCK(softc); + if (rc) + goto exit; + bus_dmamap_sync(dma_data->idi_tag, dma_data->idi_map, + BUS_DMASYNC_POSTWRITE); + +exit: + return rc; +} + +int +bnxt_hwrm_nvm_get_dev_info(struct bnxt_softc *softc, uint16_t *mfg_id, + uint16_t *device_id, uint32_t *sector_size, uint32_t *nvram_size, + uint32_t *reserved_size, uint32_t *available_size) +{ + struct hwrm_nvm_get_dev_info_input req = {0}; + struct hwrm_nvm_get_dev_info_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + uint32_t old_timeo; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_GET_DEV_INFO); + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + if (rc) + goto exit; + + if (mfg_id) + *mfg_id = le16toh(resp->manufacturer_id); + if (device_id) + *device_id = le16toh(resp->device_id); + if (sector_size) + *sector_size = le32toh(resp->sector_size); + if (nvram_size) + *nvram_size = le32toh(resp->nvram_size); + if (reserved_size) + *reserved_size = le32toh(resp->reserved_size); + if (available_size) + *available_size = le32toh(resp->available_size); + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_nvm_install_update(struct bnxt_softc *softc, + uint32_t install_type, uint64_t *installed_items, uint8_t *result, + uint8_t *problem_item, uint8_t *reset_required) +{ + struct hwrm_nvm_install_update_input req = {0}; + struct hwrm_nvm_install_update_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + uint32_t old_timeo; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_INSTALL_UPDATE); + req.install_type = htole32(install_type); + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + if (rc) + goto exit; + + if (installed_items) + *installed_items = le32toh(resp->installed_items); + if (result) + *result = resp->result; + if (problem_item) + *problem_item = resp->problem_item; + if (reset_required) + *reset_required = resp->reset_required; + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_nvm_verify_update(struct bnxt_softc *softc, uint16_t type, + uint16_t ordinal, uint16_t ext) +{ + struct hwrm_nvm_verify_update_input req = {0}; + uint32_t old_timeo; + int rc; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_NVM_VERIFY_UPDATE); + + req.dir_type = htole16(type); + req.dir_ordinal = htole16(ordinal); + req.dir_ext = htole16(ext); + + BNXT_HWRM_LOCK(softc); + old_timeo = softc->hwrm_cmd_timeo; + softc->hwrm_cmd_timeo = BNXT_NVM_TIMEO; + rc = _hwrm_send_message(softc, &req, sizeof(req)); + softc->hwrm_cmd_timeo = old_timeo; + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_fw_get_time(struct bnxt_softc *softc, uint16_t *year, uint8_t *month, + uint8_t *day, uint8_t *hour, uint8_t *minute, uint8_t *second, + uint16_t *millisecond, uint16_t *zone) +{ + struct hwrm_fw_get_time_input req = {0}; + struct hwrm_fw_get_time_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_GET_TIME); + + BNXT_HWRM_LOCK(softc); + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto exit; + + if (year) + *year = le16toh(resp->year); + if (month) + *month = resp->month; + if (day) + *day = resp->day; + if (hour) + *hour = resp->hour; + if (minute) + *minute = resp->minute; + if (second) + *second = resp->second; + if (millisecond) + *millisecond = le16toh(resp->millisecond); + if (zone) + *zone = le16toh(resp->zone); + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} + +int +bnxt_hwrm_fw_set_time(struct bnxt_softc *softc, uint16_t year, uint8_t month, + uint8_t day, uint8_t hour, uint8_t minute, uint8_t second, + uint16_t millisecond, uint16_t zone) +{ + struct hwrm_fw_set_time_input req = {0}; + + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_FW_SET_TIME); + + req.year = htole16(year); + req.month = month; + req.day = day; + req.hour = hour; + req.minute = minute; + req.second = second; + req.millisecond = htole16(millisecond); + req.zone = htole16(zone); + return hwrm_send_message(softc, &req, sizeof(req)); +} + +int +bnxt_hwrm_port_phy_qcfg(struct bnxt_softc *softc) +{ + struct bnxt_link_info *link_info = &softc->link_info; + struct hwrm_port_phy_qcfg_input req = {0}; + struct hwrm_port_phy_qcfg_output *resp = + (void *)softc->hwrm_cmd_resp.idi_vaddr; + int rc = 0; + + BNXT_HWRM_LOCK(softc); + bnxt_hwrm_cmd_hdr_init(softc, &req, HWRM_PORT_PHY_QCFG); + + rc = _hwrm_send_message(softc, &req, sizeof(req)); + if (rc) + goto exit; + + link_info->phy_link_status = resp->link; + link_info->duplex = resp->duplex; + link_info->pause = resp->pause; + link_info->auto_mode = resp->auto_mode; + link_info->auto_pause = resp->auto_pause; + link_info->force_pause = resp->force_pause; + link_info->duplex_setting = resp->duplex; + if (link_info->phy_link_status == HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) + link_info->link_speed = le16toh(resp->link_speed); + else + link_info->link_speed = 0; + link_info->force_link_speed = le16toh(resp->force_link_speed); + link_info->auto_link_speed = le16toh(resp->auto_link_speed); + link_info->support_speeds = le16toh(resp->support_speeds); + link_info->auto_link_speeds = le16toh(resp->auto_link_speed_mask); + link_info->preemphasis = le32toh(resp->preemphasis); + link_info->phy_ver[0] = resp->phy_maj; + link_info->phy_ver[1] = resp->phy_min; + link_info->phy_ver[2] = resp->phy_bld; + snprintf(softc->ver_info->phy_ver, sizeof(softc->ver_info->phy_ver), + "%d.%d.%d", link_info->phy_ver[0], link_info->phy_ver[1], + link_info->phy_ver[2]); + strlcpy(softc->ver_info->phy_vendor, resp->phy_vendor_name, + BNXT_NAME_SIZE); + strlcpy(softc->ver_info->phy_partnumber, resp->phy_vendor_partnumber, + BNXT_NAME_SIZE); + link_info->media_type = resp->media_type; + link_info->phy_type = resp->phy_type; + link_info->transceiver = resp->xcvr_pkg_type; + link_info->phy_addr = resp->eee_config_phy_addr & + HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK; + +exit: + BNXT_HWRM_UNLOCK(softc); + return rc; +} Index: sys/dev/bnxt/bnxt_ioctl.h =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_ioctl.h @@ -0,0 +1,193 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#ifndef _BNXT_IOCTL_H +#define _BNXT_IOCTL_H + +enum bnxt_ioctl_type { + BNXT_HWRM_NVM_FIND_DIR_ENTRY, + BNXT_HWRM_NVM_READ, + BNXT_HWRM_FW_RESET, + BNXT_HWRM_FW_QSTATUS, + BNXT_HWRM_NVM_WRITE, + BNXT_HWRM_NVM_ERASE_DIR_ENTRY, + BNXT_HWRM_NVM_GET_DIR_INFO, + BNXT_HWRM_NVM_GET_DIR_ENTRIES, + BNXT_HWRM_NVM_MODIFY, + BNXT_HWRM_NVM_VERIFY_UPDATE, + BNXT_HWRM_NVM_INSTALL_UPDATE, + BNXT_HWRM_FW_GET_TIME, + BNXT_HWRM_FW_SET_TIME, +}; + +struct bnxt_ioctl_header { + enum bnxt_ioctl_type type; + int rc; +}; + +struct bnxt_ioctl_hwrm_nvm_find_dir_entry { + struct bnxt_ioctl_header hdr; + uint32_t data_length; + uint32_t fw_ver; + uint32_t item_length; + uint16_t ext; + uint16_t index; + uint16_t ordinal; + uint16_t type; + uint8_t search_opt; + bool use_index; +}; + +struct bnxt_ioctl_hwrm_nvm_read { + struct bnxt_ioctl_header hdr; + uint8_t *data; + uint32_t length; + uint32_t offset; + uint16_t index; +}; + +struct bnxt_ioctl_hwrm_fw_reset { + struct bnxt_ioctl_header hdr; + uint8_t processor; + uint8_t selfreset; +}; + +struct bnxt_ioctl_hwrm_fw_qstatus { + struct bnxt_ioctl_header hdr; + uint8_t processor; + uint8_t selfreset; +}; + +struct bnxt_ioctl_hwrm_nvm_write { + struct bnxt_ioctl_header hdr; + uint8_t *data; + uint32_t data_length; + uint32_t item_length; + uint16_t attr; + uint16_t ext; + uint16_t index; + uint16_t option; + uint16_t ordinal; + uint16_t type; + bool keep; +}; + +struct bnxt_ioctl_hwrm_nvm_erase_dir_entry { + struct bnxt_ioctl_header hdr; + enum bnxt_ioctl_type type; + int rc; + uint16_t index; +}; + +struct bnxt_ioctl_hwrm_nvm_get_dir_info { + struct bnxt_ioctl_header hdr; + uint32_t entries; + uint32_t entry_length; +}; + +struct bnxt_ioctl_hwrm_nvm_get_dir_entries { + struct bnxt_ioctl_header hdr; + uint8_t *data; + size_t max_size; + uint32_t entries; + uint32_t entry_length; +}; + +struct bnxt_ioctl_hwrm_nvm_install_update { + struct bnxt_ioctl_header hdr; + uint64_t installed_items; + uint32_t install_type; + uint8_t problem_item; + uint8_t reset_required; + uint8_t result; +}; + +struct bnxt_ioctl_hwrm_nvm_verify_update { + struct bnxt_ioctl_header hdr; + uint16_t ext; + uint16_t ordinal; + uint16_t type; +}; + +struct bnxt_ioctl_hwrm_nvm_modify { + struct bnxt_ioctl_header hdr; + uint8_t *data; + uint32_t length; + uint32_t offset; + uint16_t index; +}; + +struct bnxt_ioctl_hwrm_fw_get_time { + struct bnxt_ioctl_header hdr; + uint16_t millisecond; + uint16_t year; + uint16_t zone; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t month; + uint8_t second; +}; + +struct bnxt_ioctl_hwrm_fw_set_time { + struct bnxt_ioctl_header hdr; + uint16_t millisecond; + uint16_t year; + uint16_t zone; + uint8_t day; + uint8_t hour; + uint8_t minute; + uint8_t month; + uint8_t second; +}; + +/* IOCTL interface */ +struct bnxt_ioctl_data { + union { + struct bnxt_ioctl_header hdr; + struct bnxt_ioctl_hwrm_nvm_find_dir_entry find; + struct bnxt_ioctl_hwrm_nvm_read read; + struct bnxt_ioctl_hwrm_fw_reset reset; + struct bnxt_ioctl_hwrm_fw_qstatus status; + struct bnxt_ioctl_hwrm_nvm_write write; + struct bnxt_ioctl_hwrm_nvm_erase_dir_entry erase; + struct bnxt_ioctl_hwrm_nvm_get_dir_info dir_info; + struct bnxt_ioctl_hwrm_nvm_get_dir_entries dir_entries; + struct bnxt_ioctl_hwrm_nvm_install_update install; + struct bnxt_ioctl_hwrm_nvm_verify_update verify; + struct bnxt_ioctl_hwrm_nvm_modify modify; + struct bnxt_ioctl_hwrm_fw_get_time get_time; + struct bnxt_ioctl_hwrm_fw_set_time set_time; + }; +}; + +#endif Index: sys/dev/bnxt/bnxt_sysctl.h =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_sysctl.h @@ -0,0 +1,42 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "bnxt.h" + +int bnxt_init_sysctl_ctx(struct bnxt_softc *softc); +int bnxt_free_sysctl_ctx(struct bnxt_softc *softc); +int bnxt_create_tx_sysctls(struct bnxt_softc *softc, int txr); +int bnxt_create_rx_sysctls(struct bnxt_softc *softc, int rxr); +int bnxt_create_ver_sysctls(struct bnxt_softc *softc); +int bnxt_create_nvram_sysctls(struct bnxt_nvram_info *ni); +int bnxt_create_config_sysctls_pre(struct bnxt_softc *softc); +int bnxt_create_config_sysctls_post(struct bnxt_softc *softc); Index: sys/dev/bnxt/bnxt_sysctl.c =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_sysctl.c @@ -0,0 +1,619 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +#include "bnxt.h" +#include "bnxt_hwrm.h" +#include "bnxt_sysctl.h" + +static int bnxt_vlan_only_sysctl(SYSCTL_HANDLER_ARGS); +/* + * We want to create: + * dev.bnxt.0.hwstats.txq0 + * dev.bnxt.0.hwstats.txq0.txmbufs + * dev.bnxt.0.hwstats.rxq0 + * dev.bnxt.0.hwstats.txq0.rxmbufs + * so the hwstats ctx list needs to be created in attach_post and populated + * during init. + * + * Then, it needs to be cleaned up in stop. + */ + +int +bnxt_init_sysctl_ctx(struct bnxt_softc *softc) +{ + struct sysctl_ctx_list *ctx; + + sysctl_ctx_init(&softc->hw_stats); + ctx = device_get_sysctl_ctx(softc->dev); + softc->hw_stats_oid = SYSCTL_ADD_NODE(ctx, + SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, + "hwstats", CTLFLAG_RD, 0, "hardware statistics"); + if (!softc->hw_stats_oid) { + sysctl_ctx_free(&softc->hw_stats); + return ENOMEM; + } + + sysctl_ctx_init(&softc->ver_info->ver_ctx); + ctx = device_get_sysctl_ctx(softc->dev); + softc->ver_info->ver_oid = SYSCTL_ADD_NODE(ctx, + SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, + "ver", CTLFLAG_RD, 0, "hardware/firmware version information"); + if (!softc->ver_info->ver_oid) { + sysctl_ctx_free(&softc->ver_info->ver_ctx); + return ENOMEM; + } + + sysctl_ctx_init(&softc->nvm_info->nvm_ctx); + ctx = device_get_sysctl_ctx(softc->dev); + softc->nvm_info->nvm_oid = SYSCTL_ADD_NODE(ctx, + SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev)), OID_AUTO, + "nvram", CTLFLAG_RD, 0, "nvram information"); + if (!softc->nvm_info->nvm_oid) { + sysctl_ctx_free(&softc->nvm_info->nvm_ctx); + return ENOMEM; + } + + return 0; +} + +int +bnxt_free_sysctl_ctx(struct bnxt_softc *softc) +{ + int orc; + int rc = 0; + + if (softc->hw_stats_oid != NULL) { + orc = sysctl_ctx_free(&softc->hw_stats); + if (orc) + rc = orc; + else + softc->hw_stats_oid = NULL; + } + if (softc->ver_info->ver_oid != NULL) { + orc = sysctl_ctx_free(&softc->ver_info->ver_ctx); + if (orc) + rc = orc; + else + softc->ver_info->ver_oid = NULL; + } + if (softc->nvm_info->nvm_oid != NULL) { + orc = sysctl_ctx_free(&softc->nvm_info->nvm_ctx); + if (orc) + rc = orc; + else + softc->nvm_info->nvm_oid = NULL; + } + + return rc; +} + +int +bnxt_create_tx_sysctls(struct bnxt_softc *softc, int txr) +{ + struct sysctl_oid *oid; + struct ctx_hw_stats *tx_stats = (void *)softc->tx_stats.idi_vaddr; + char name[32]; + char desc[64]; + + sprintf(name, "txq%d", txr); + sprintf(desc, "transmit queue %d", txr); + oid = SYSCTL_ADD_NODE(&softc->hw_stats, + SYSCTL_CHILDREN(softc->hw_stats_oid), OID_AUTO, name, CTLFLAG_RD, 0, + desc); + if (!oid) + return ENOMEM; + + + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "ucast_pkts", CTLFLAG_RD, &tx_stats[txr].tx_ucast_pkts, + "unicast packets sent"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "mcast_pkts", CTLFLAG_RD, &tx_stats[txr].tx_mcast_pkts, + "multicast packets sent"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "bcast_pkts", CTLFLAG_RD, &tx_stats[txr].tx_bcast_pkts, + "broadcast packets sent"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "discard_pkts", CTLFLAG_RD, + &tx_stats[txr].tx_discard_pkts, "discarded transmit packets"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "drop_pkts", CTLFLAG_RD, &tx_stats[txr].tx_drop_pkts, + "dropped transmit packets"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "ucast_bytes", CTLFLAG_RD, &tx_stats[txr].tx_ucast_bytes, + "unicast bytes sent"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "mcast_bytes", CTLFLAG_RD, &tx_stats[txr].tx_mcast_bytes, + "multicast bytes sent"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "bcast_bytes", CTLFLAG_RD, &tx_stats[txr].tx_bcast_bytes, + "broadcast bytes sent"); + + return 0; +} + +int +bnxt_create_rx_sysctls(struct bnxt_softc *softc, int rxr) +{ + struct sysctl_oid *oid; + struct ctx_hw_stats *rx_stats = (void *)softc->rx_stats.idi_vaddr; + char name[32]; + char desc[64]; + + sprintf(name, "rxq%d", rxr); + sprintf(desc, "receive queue %d", rxr); + oid = SYSCTL_ADD_NODE(&softc->hw_stats, + SYSCTL_CHILDREN(softc->hw_stats_oid), OID_AUTO, name, CTLFLAG_RD, 0, + desc); + if (!oid) + return ENOMEM; + + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "ucast_pkts", CTLFLAG_RD, &rx_stats[rxr].rx_ucast_pkts, + "unicast packets received"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "mcast_pkts", CTLFLAG_RD, &rx_stats[rxr].rx_mcast_pkts, + "multicast packets received"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "bcast_pkts", CTLFLAG_RD, &rx_stats[rxr].rx_bcast_pkts, + "broadcast packets received"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "discard_pkts", CTLFLAG_RD, + &rx_stats[rxr].rx_discard_pkts, "discarded receive packets"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "drop_pkts", CTLFLAG_RD, &rx_stats[rxr].rx_drop_pkts, + "dropped receive packets"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "ucast_bytes", CTLFLAG_RD, &rx_stats[rxr].rx_ucast_bytes, + "unicast bytes received"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "mcast_bytes", CTLFLAG_RD, &rx_stats[rxr].rx_mcast_bytes, + "multicast bytes received"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "bcast_bytes", CTLFLAG_RD, &rx_stats[rxr].rx_bcast_bytes, + "broadcast bytes received"); + + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "tpa_pkts", CTLFLAG_RD, &rx_stats[rxr].tpa_pkts, + "TPA packets"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "tpa_bytes", CTLFLAG_RD, &rx_stats[rxr].tpa_bytes, + "TPA bytes"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "tpa_events", CTLFLAG_RD, &rx_stats[rxr].tpa_events, + "TPA events"); + SYSCTL_ADD_QUAD(&softc->hw_stats, SYSCTL_CHILDREN(oid), OID_AUTO, + "tpa_aborts", CTLFLAG_RD, &rx_stats[rxr].tpa_aborts, + "TPA aborts"); + + return 0; +} + +static char *bnxt_chip_type[] = { + "ASIC", + "FPGA", + "Palladium", + "Unknown" +}; +#define MAX_CHIP_TYPE 3 + +static int +bnxt_package_ver_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct bnxt_softc *softc = arg1; + struct iflib_dma_info dma_data; + char *pkglog = NULL; + char *p; + char *next; + char unk[] = ""; + char *buf = unk; + int rc; + int field; + uint16_t ordinal = BNX_DIR_ORDINAL_FIRST; + uint16_t index; + uint32_t data_len; + + rc = bnxt_hwrm_nvm_find_dir_entry(softc, BNX_DIR_TYPE_PKG_LOG, + &ordinal, BNX_DIR_EXT_NONE, &index, false, + HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ, + &data_len, NULL, NULL); + dma_data.idi_vaddr = NULL; + if (rc == 0 && data_len) { + rc = iflib_dma_alloc(softc->ctx, data_len, &dma_data, + BUS_DMA_NOWAIT); + if (rc == 0) { + rc = bnxt_hwrm_nvm_read(softc, index, 0, data_len, + &dma_data); + if (rc == 0) { + pkglog = dma_data.idi_vaddr; + /* NULL terminate (removes last \n) */ + pkglog[data_len-1] = 0; + + /* Set p = start of last line */ + p = strrchr(pkglog, '\n'); + if (p == NULL) + p = pkglog; + + /* Now find the correct tab delimited field */ + for (field = 0, next = p, + p = strsep(&next, "\t"); + field < + BNX_PKG_LOG_FIELD_IDX_PKG_VERSION && p; + p = strsep(&next, "\t")) { + field++; + } + if (field == BNX_PKG_LOG_FIELD_IDX_PKG_VERSION) + buf = p; + } + } + else + dma_data.idi_vaddr = NULL; + } + + rc = sysctl_handle_string(oidp, buf, 0, req); + if (dma_data.idi_vaddr) + iflib_dma_free(&dma_data); + return rc; +} + +static int +bnxt_hwrm_min_ver_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct bnxt_softc *softc = arg1; + char buf[16]; + uint8_t newver[3]; + int rc; + + sprintf(buf, "%hhu.%hhu.%hhu", softc->ver_info->hwrm_min_major, + softc->ver_info->hwrm_min_minor, softc->ver_info->hwrm_min_update); + + rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); + if (rc || req->newptr == NULL) + return rc; + if (sscanf(buf, "%hhu.%hhu.%hhu%*c", &newver[0], &newver[1], + &newver[2]) != 3) + return EINVAL; + softc->ver_info->hwrm_min_major = newver[0]; + softc->ver_info->hwrm_min_minor = newver[1]; + softc->ver_info->hwrm_min_update = newver[2]; + bnxt_check_hwrm_version(softc); + + return rc; +} + +int +bnxt_create_ver_sysctls(struct bnxt_softc *softc) +{ + struct bnxt_ver_info *vi = softc->ver_info; + struct sysctl_oid *oid = vi->ver_oid; + + if (!oid) + return ENOMEM; + + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "hwrm_if", CTLFLAG_RD, vi->hwrm_if_ver, 0, + "HWRM interface version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "driver_hwrm_if", CTLFLAG_RD, vi->driver_hwrm_if_ver, 0, + "HWRM firmware version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "hwrm_fw", CTLFLAG_RD, vi->hwrm_fw_ver, 0, + "HWRM firmware version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "mgmt_fw", CTLFLAG_RD, vi->mgmt_fw_ver, 0, + "management firmware version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "netctrl_fw", CTLFLAG_RD, vi->netctrl_fw_ver, 0, + "network control firmware version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "roce_fw", CTLFLAG_RD, vi->roce_fw_ver, 0, + "RoCE firmware version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "phy", CTLFLAG_RD, vi->phy_ver, 0, + "PHY version"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "hwrm_fw_name", CTLFLAG_RD, vi->hwrm_fw_name, 0, + "HWRM firmware name"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "mgmt_fw_name", CTLFLAG_RD, vi->mgmt_fw_name, 0, + "management firmware name"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "netctrl_fw_name", CTLFLAG_RD, vi->netctrl_fw_name, 0, + "network control firmware name"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "roce_fw_name", CTLFLAG_RD, vi->roce_fw_name, 0, + "RoCE firmware name"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "phy_vendor", CTLFLAG_RD, vi->phy_vendor, 0, + "PHY vendor name"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "phy_partnumber", CTLFLAG_RD, vi->phy_partnumber, 0, + "PHY vendor part number"); + SYSCTL_ADD_U16(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "chip_num", CTLFLAG_RD, &vi->chip_num, 0, "chip number"); + SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "chip_rev", CTLFLAG_RD, &vi->chip_rev, 0, "chip revision"); + SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "chip_metal", CTLFLAG_RD, &vi->chip_metal, 0, "chip metal number"); + SYSCTL_ADD_U8(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "chip_bond_id", CTLFLAG_RD, &vi->chip_bond_id, 0, + "chip bond id"); + SYSCTL_ADD_STRING(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "chip_type", CTLFLAG_RD, vi->chip_type > MAX_CHIP_TYPE ? + bnxt_chip_type[MAX_CHIP_TYPE] : bnxt_chip_type[vi->chip_type], 0, + "RoCE firmware name"); + SYSCTL_ADD_PROC(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "package_ver", CTLTYPE_STRING|CTLFLAG_RD, softc, 0, + bnxt_package_ver_sysctl, "A", + "currently installed package version"); + SYSCTL_ADD_PROC(&vi->ver_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "hwrm_min_ver", CTLTYPE_STRING|CTLFLAG_RWTUN, softc, 0, + bnxt_hwrm_min_ver_sysctl, "A", + "minimum hwrm API vesion to support"); + + return 0; +} + +int +bnxt_create_nvram_sysctls(struct bnxt_nvram_info *ni) +{ + struct sysctl_oid *oid = ni->nvm_oid; + + if (!oid) + return ENOMEM; + + SYSCTL_ADD_U16(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "mfg_id", CTLFLAG_RD, &ni->mfg_id, 0, "manufacturer id"); + SYSCTL_ADD_U16(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "device_id", CTLFLAG_RD, &ni->device_id, 0, "device id"); + SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "sector_size", CTLFLAG_RD, &ni->sector_size, 0, "sector size"); + SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "size", CTLFLAG_RD, &ni->size, 0, "nvram total size"); + SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "reserved_size", CTLFLAG_RD, &ni->reserved_size, 0, + "total reserved space"); + SYSCTL_ADD_U32(&ni->nvm_ctx, SYSCTL_CHILDREN(oid), OID_AUTO, + "available_size", CTLFLAG_RD, &ni->available_size, 0, + "total available space"); + + return 0; +} + +static int +bnxt_rss_key_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct bnxt_softc *softc = arg1; + char buf[HW_HASH_KEY_SIZE*2+1] = {0}; + char *p; + int i; + int rc; + + for (p = buf, i=0; ivnic_info.rss_hash_key[i]); + + rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); + if (rc || req->newptr == NULL) + return rc; + + if (strspn(buf, "0123456789abcdefABCDEF") != (HW_HASH_KEY_SIZE * 2)) + return EINVAL; + + for (p = buf, i=0; ivnic_info.rss_hash_key[i]) != 1) + return EINVAL; + p += 2; + } + + if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) + bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, + softc->vnic_info.rss_hash_type); + + return rc; +} + +static const char *bnxt_hash_types[] = {"ipv4", "tcp_ipv4", "udp_ipv4", "ipv6", + "tcp_ipv6", "udp_ipv6", NULL}; + +static int bnxt_get_rss_type_str_bit(char *str) +{ + int i; + + for (i=0; bnxt_hash_types[i]; i++) + if (strcmp(bnxt_hash_types[i], str) == 0) + return i; + + return -1; +} + +static int +bnxt_rss_type_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct bnxt_softc *softc = arg1; + char buf[256] = {0}; + char *p; + char *next; + int rc; + int type; + int bit; + + for (type = softc->vnic_info.rss_hash_type; type; + type &= ~(1<= sizeof(bnxt_hash_types) / sizeof(const char *)) + continue; + if (type != softc->vnic_info.rss_hash_type) + strcat(buf, ","); + strcat(buf, bnxt_hash_types[bit]); + } + + rc = sysctl_handle_string(oidp, buf, sizeof(buf), req); + if (rc || req->newptr == NULL) + return rc; + + for (type = 0, next = buf, p = strsep(&next, " ,"); p; + p = strsep(&next, " ,")) { + bit = bnxt_get_rss_type_str_bit(p); + if (bit == -1) + return EINVAL; + type |= 1<vnic_info.rss_hash_type) { + softc->vnic_info.rss_hash_type = type; + if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) + bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, + softc->vnic_info.rss_hash_type); + } + + return rc; +} + +static int +bnxt_rx_stall_sysctl(SYSCTL_HANDLER_ARGS) { + struct bnxt_softc *softc = arg1; + int rc; + int val; + + if (softc == NULL) + return EBUSY; + + val = (bool)(softc->vnic_info.flags & BNXT_VNIC_FLAG_BD_STALL); + rc = sysctl_handle_int(oidp, &val, 0, req); + if (rc || !req->newptr) + return rc; + + if (val) + softc->vnic_info.flags |= BNXT_VNIC_FLAG_BD_STALL; + else + softc->vnic_info.flags &= ~BNXT_VNIC_FLAG_BD_STALL; + + if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) + rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); + + return rc; +} + +static int +bnxt_vlan_strip_sysctl(SYSCTL_HANDLER_ARGS) { + struct bnxt_softc *softc = arg1; + int rc; + int val; + + if (softc == NULL) + return EBUSY; + + val = (bool)(softc->vnic_info.flags & BNXT_VNIC_FLAG_VLAN_STRIP); + rc = sysctl_handle_int(oidp, &val, 0, req); + if (rc || !req->newptr) + return rc; + + if (val) + softc->vnic_info.flags |= BNXT_VNIC_FLAG_VLAN_STRIP; + else + softc->vnic_info.flags &= ~BNXT_VNIC_FLAG_VLAN_STRIP; + + if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) + rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); + + return rc; +} + +int +bnxt_create_config_sysctls_pre(struct bnxt_softc *softc) +{ + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(softc->dev); + struct sysctl_oid_list *children; + + children = SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev));; + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rss_key", + CTLTYPE_STRING|CTLFLAG_RWTUN, softc, 0, bnxt_rss_key_sysctl, "A", + "RSS key"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rss_type", + CTLTYPE_STRING|CTLFLAG_RWTUN, softc, 0, bnxt_rss_type_sysctl, "A", + "RSS type bits"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_stall", + CTLTYPE_INT|CTLFLAG_RWTUN, softc, 0, bnxt_rx_stall_sysctl, "I", + "buffer rx packets in hardware until the host posts new buffers"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "vlan_strip", + CTLTYPE_INT|CTLFLAG_RWTUN, softc, 0, bnxt_vlan_strip_sysctl, "I", + "strip VLAN tag in the RX path"); + SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "if_name", CTLFLAG_RD, + iflib_get_ifp(softc->ctx)->if_xname, 0, "interface name"); + + return 0; +} + +static int +bnxt_vlan_only_sysctl(SYSCTL_HANDLER_ARGS) { + struct bnxt_softc *softc = arg1; + int rc; + int val; + + if (softc == NULL) + return EBUSY; + + val = softc->vnic_info.vlan_only; + rc = sysctl_handle_int(oidp, &val, 0, req); + if (rc || !req->newptr) + return rc; + + if (val) + val = 1; + + if (val != softc->vnic_info.vlan_only) { + softc->vnic_info.vlan_only = val; + if (if_getdrvflags(iflib_get_ifp(softc->ctx)) & IFF_DRV_RUNNING) + rc = bnxt_hwrm_cfa_l2_set_rx_mask(softc, + &softc->vnic_info); + } + + return rc; +} + +int +bnxt_create_config_sysctls_post(struct bnxt_softc *softc) +{ + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(softc->dev); + struct sysctl_oid_list *children; + + children = SYSCTL_CHILDREN(device_get_sysctl_tree(softc->dev));; + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "vlan_only", + CTLTYPE_INT|CTLFLAG_RWTUN, softc, 0, bnxt_vlan_only_sysctl, "I", + "require vlan tag on received packets when vlan is enabled"); + + return 0; +} Index: sys/dev/bnxt/bnxt_txrx.c =================================================================== --- /dev/null +++ sys/dev/bnxt/bnxt_txrx.c @@ -0,0 +1,639 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include "opt_inet.h" +#include "opt_inet6.h" +#include "opt_rss.h" + +#include "bnxt.h" + +/* + * Function prototypes + */ + +static int bnxt_isc_txd_encap(void *sc, if_pkt_info_t pi); +static void bnxt_isc_txd_flush(void *sc, uint16_t txqid, uint32_t pidx); +static int bnxt_isc_txd_credits_update(void *sc, uint16_t txqid, uint32_t cidx, + bool clear); + +static void bnxt_isc_rxd_refill(void *sc, uint16_t rxqid, uint8_t flid, + uint32_t pidx, uint64_t *paddrs, caddr_t *vaddrs, uint16_t count, + uint16_t buf_size); +static void bnxt_isc_rxd_flush(void *sc, uint16_t rxqid, uint8_t flid, + uint32_t pidx); +static int bnxt_isc_rxd_available(void *sc, uint16_t rxqid, uint32_t idx, + int budget); +static int bnxt_isc_rxd_pkt_get(void *sc, if_rxd_info_t ri); + +static int bnxt_intr(void *sc); + +struct if_txrx bnxt_txrx = { + bnxt_isc_txd_encap, + bnxt_isc_txd_flush, + bnxt_isc_txd_credits_update, + bnxt_isc_rxd_available, + bnxt_isc_rxd_pkt_get, + bnxt_isc_rxd_refill, + bnxt_isc_rxd_flush, + bnxt_intr +}; + +/* + * Device Dependent Packet Transmit and Receive Functions + */ + +static const uint16_t bnxt_tx_lhint[] = { + TX_BD_SHORT_FLAGS_LHINT_LT512, + TX_BD_SHORT_FLAGS_LHINT_LT1K, + TX_BD_SHORT_FLAGS_LHINT_LT2K, + TX_BD_SHORT_FLAGS_LHINT_LT2K, + TX_BD_SHORT_FLAGS_LHINT_GTE2K, +}; + +static int +bnxt_isc_txd_encap(void *sc, if_pkt_info_t pi) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_ring *txr = &softc->tx_rings[pi->ipi_qsidx]; + struct tx_bd_long *tbd; + struct tx_bd_long_hi *tbdh; + bool need_hi = false; + uint16_t flags_type; + uint16_t lflags; + uint32_t cfa_meta; + int seg = 0; + + /* If we have offloads enabled, we need to use two BDs. */ + if ((pi->ipi_csum_flags & (CSUM_OFFLOAD | CSUM_TSO | CSUM_IP)) || + pi->ipi_mflags & M_VLANTAG) + need_hi = true; + + pi->ipi_new_pidx = pi->ipi_pidx; + tbd = &((struct tx_bd_long *)txr->vaddr)[pi->ipi_new_pidx]; + pi->ipi_ndescs = 0; + /* No need to byte-swap the opaque value */ + tbd->opaque = ((pi->ipi_nsegs + need_hi) << 24) | pi->ipi_new_pidx; + tbd->len = htole16(pi->ipi_segs[seg].ds_len); + tbd->addr = htole64(pi->ipi_segs[seg++].ds_addr); + flags_type = ((pi->ipi_nsegs + need_hi) << + TX_BD_SHORT_FLAGS_BD_CNT_SFT) & TX_BD_SHORT_FLAGS_BD_CNT_MASK; + if (pi->ipi_len >= 2048) + flags_type |= TX_BD_SHORT_FLAGS_LHINT_GTE2K; + else + flags_type |= bnxt_tx_lhint[pi->ipi_len >> 9]; + + if (need_hi) { + flags_type |= TX_BD_LONG_TYPE_TX_BD_LONG; + + pi->ipi_new_pidx = RING_NEXT(txr, pi->ipi_new_pidx); + tbdh = &((struct tx_bd_long_hi *)txr->vaddr)[pi->ipi_new_pidx]; + tbdh->mss = htole16(pi->ipi_tso_segsz); + tbdh->hdr_size = htole16((pi->ipi_ehdrlen + pi->ipi_ip_hlen + + pi->ipi_tcp_hlen) >> 1); + tbdh->cfa_action = 0; + lflags = 0; + cfa_meta = 0; + if (pi->ipi_mflags & M_VLANTAG) { + /* TODO: Do we need to byte-swap the vtag here? */ + cfa_meta = TX_BD_LONG_CFA_META_KEY_VLAN_TAG | + pi->ipi_vtag; + cfa_meta |= TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; + } + tbdh->cfa_meta = htole32(cfa_meta); + if (pi->ipi_csum_flags & CSUM_TSO) { + lflags |= TX_BD_LONG_LFLAGS_LSO | + TX_BD_LONG_LFLAGS_T_IPID; + } + else if(pi->ipi_csum_flags & CSUM_OFFLOAD) { + lflags |= TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM | + TX_BD_LONG_LFLAGS_IP_CHKSUM; + } + else if(pi->ipi_csum_flags & CSUM_IP) { + lflags |= TX_BD_LONG_LFLAGS_IP_CHKSUM; + } + tbdh->lflags = htole16(lflags); + } + else { + flags_type |= TX_BD_SHORT_TYPE_TX_BD_SHORT; + } + + for (; seg < pi->ipi_nsegs; seg++) { + tbd->flags_type = htole16(flags_type); + pi->ipi_new_pidx = RING_NEXT(txr, pi->ipi_new_pidx); + tbd = &((struct tx_bd_long *)txr->vaddr)[pi->ipi_new_pidx]; + tbd->len = htole16(pi->ipi_segs[seg].ds_len); + tbd->addr = htole64(pi->ipi_segs[seg].ds_addr); + flags_type = TX_BD_SHORT_TYPE_TX_BD_SHORT; + } + flags_type |= TX_BD_SHORT_FLAGS_PACKET_END; + tbd->flags_type = htole16(flags_type); + pi->ipi_new_pidx = RING_NEXT(txr, pi->ipi_new_pidx); + + return 0; +} + +static void +bnxt_isc_txd_flush(void *sc, uint16_t txqid, uint32_t pidx) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_ring *tx_ring = &softc->tx_rings[txqid]; + + /* pidx is what we last set ipi_new_pidx to */ + BNXT_TX_DB(tx_ring, pidx); + /* TODO: Cumulus+ doesn't need the double doorbell */ + BNXT_TX_DB(tx_ring, pidx); + return; +} + +static int +bnxt_isc_txd_credits_update(void *sc, uint16_t txqid, uint32_t idx, bool clear) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_cp_ring *cpr = &softc->tx_cp_rings[txqid]; + struct tx_cmpl *cmpl = (struct tx_cmpl *)cpr->ring.vaddr; + int avail = 0; + uint32_t cons = cpr->cons; + bool v_bit = cpr->v_bit; + bool last_v_bit; + uint32_t last_cons; + uint16_t type; + uint16_t err; + + for (;;) { + last_cons = cons; + last_v_bit = v_bit; + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmpl[cons], v_bit)) + goto done; + + type = cmpl[cons].flags_type & TX_CMPL_TYPE_MASK; + switch (type) { + case TX_CMPL_TYPE_TX_L2: + err = (le16toh(cmpl[cons].errors_v) & + TX_CMPL_ERRORS_BUFFER_ERROR_MASK) >> + TX_CMPL_ERRORS_BUFFER_ERROR_SFT; + if (err) + device_printf(softc->dev, + "TX completion error %u\n", err); + /* No need to byte-swap the opaque value */ + avail += cmpl[cons].opaque >> 24; + /* + * If we're not clearing, iflib only cares if there's + * at least one buffer. Don't scan the whole ring in + * this case. + */ + if (!clear) + goto done; + break; + default: + if (type & 1) { + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + if (!CMP_VALID(&cmpl[cons], v_bit)) + goto done; + } + device_printf(softc->dev, + "Unhandled TX completion type %u\n", type); + break; + } + } +done: + + if (clear && avail) { + cpr->cons = last_cons; + cpr->v_bit = last_v_bit; + BNXT_CP_IDX_DISABLE_DB(&cpr->ring, cpr->cons); + } + + return avail; +} + +static void +bnxt_isc_rxd_refill(void *sc, uint16_t rxqid, uint8_t flid, + uint32_t pidx, uint64_t *paddrs, + caddr_t *vaddrs, uint16_t count, uint16_t len) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_ring *rx_ring; + struct rx_prod_pkt_bd *rxbd; + uint16_t type; + uint16_t i; + + if (flid == 0) { + rx_ring = &softc->rx_rings[rxqid]; + type = RX_PROD_PKT_BD_TYPE_RX_PROD_PKT; + } + else { + rx_ring = &softc->ag_rings[rxqid]; + type = RX_PROD_AGG_BD_TYPE_RX_PROD_AGG; + } + rxbd = (void *)rx_ring->vaddr; + + for (i=0; iring_size) + pidx = 0; + } + return; +} + +static void +bnxt_isc_rxd_flush(void *sc, uint16_t rxqid, uint8_t flid, + uint32_t pidx) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_ring *rx_ring; + + if (flid == 0) + rx_ring = &softc->rx_rings[rxqid]; + else + rx_ring = &softc->ag_rings[rxqid]; + + /* + * We *must* update the completion ring before updating the RX ring + * or we will overrun the completion ring and the device will wedge for + * RX. + */ + if (softc->rx_cp_rings[rxqid].cons != UINT32_MAX) + BNXT_CP_IDX_DISABLE_DB(&softc->rx_cp_rings[rxqid].ring, + softc->rx_cp_rings[rxqid].cons); + /* We're given the last filled RX buffer here, not the next empty one */ + BNXT_RX_DB(rx_ring, RING_NEXT(rx_ring, pidx)); + /* TODO: Cumulus+ doesn't need the double doorbell */ + BNXT_RX_DB(rx_ring, RING_NEXT(rx_ring, pidx)); + return; +} + +static int +bnxt_isc_rxd_available(void *sc, uint16_t rxqid, uint32_t idx, int budget) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_cp_ring *cpr = &softc->rx_cp_rings[rxqid]; + struct rx_pkt_cmpl *rcp; + struct rx_tpa_start_cmpl *rtpa; + struct rx_tpa_end_cmpl *rtpae; + struct cmpl_base *cmp = (struct cmpl_base *)cpr->ring.vaddr; + int avail = 0; + uint32_t cons = cpr->cons; + bool v_bit = cpr->v_bit; + uint8_t ags; + int i; + uint16_t type; + uint8_t agg_id; + + for (;;) { + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + + type = le16toh(cmp[cons].type) & CMPL_BASE_TYPE_MASK; + switch (type) { + case CMPL_BASE_TYPE_RX_L2: + rcp = (void *)&cmp[cons]; + ags = (rcp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK) >> + RX_PKT_CMPL_AGG_BUFS_SFT; + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + + /* Now account for all the AG completions */ + for (i=0; iring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + } + avail++; + break; + case CMPL_BASE_TYPE_RX_TPA_END: + rtpae = (void *)&cmp[cons]; + ags = (rtpae->agg_bufs_v1 & + RX_TPA_END_CMPL_AGG_BUFS_MASK) >> + RX_TPA_END_CMPL_AGG_BUFS_SFT; + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + /* Now account for all the AG completions */ + for (i=0; iring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + } + avail++; + break; + case CMPL_BASE_TYPE_RX_TPA_START: + rtpa = (void *)&cmp[cons]; + agg_id = (rtpa->agg_id & + RX_TPA_START_CMPL_AGG_ID_MASK) >> + RX_TPA_START_CMPL_AGG_ID_SFT; + softc->tpa_start[agg_id].low = *rtpa; + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + softc->tpa_start[agg_id].high = + ((struct rx_tpa_start_cmpl_hi *)cmp)[cons]; + break; + case CMPL_BASE_TYPE_RX_AGG: + break; + default: + device_printf(softc->dev, + "Unhandled completion type %d on RXQ %d\n", + type, rxqid); + + /* Odd completion types use two completions */ + if (type & 1) { + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + CMPL_PREFETCH_NEXT(cpr, cons); + + if (!CMP_VALID(&cmp[cons], v_bit)) + goto cmpl_invalid; + } + break; + } + if (avail > budget) + break; + } +cmpl_invalid: + + return avail; +} + +static int +bnxt_pkt_get_l2(struct bnxt_softc *softc, if_rxd_info_t ri, + struct bnxt_cp_ring *cpr, uint16_t flags_type) +{ + struct rx_pkt_cmpl *rcp; + struct rx_pkt_cmpl_hi *rcph; + struct rx_abuf_cmpl *acp; + uint32_t flags2; + uint32_t errors; + uint8_t ags; + int i; + + rcp = &((struct rx_pkt_cmpl *)cpr->ring.vaddr)[cpr->cons]; + + /* Extract from the first 16-byte BD */ + if (flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID) { + ri->iri_flowid = le32toh(rcp->rss_hash); + /* + * TODO: Extract something useful from rcp->rss_hash_type + * (undocumented) + * May be documented in the "LSI ES" + * also check the firmware code. + */ + ri->iri_rsstype = M_HASHTYPE_OPAQUE; + } + else { + ri->iri_rsstype = M_HASHTYPE_NONE; + } + ags = (rcp->agg_bufs_v1 & RX_PKT_CMPL_AGG_BUFS_MASK) >> + RX_PKT_CMPL_AGG_BUFS_SFT; + ri->iri_nfrags = ags + 1; + /* No need to byte-swap the opaque value */ + ri->iri_frags[0].irf_flid = (rcp->opaque >> 16) & 0xff; + ri->iri_frags[0].irf_idx = rcp->opaque & 0xffff; + ri->iri_frags[0].irf_len = le16toh(rcp->len); + ri->iri_len = le16toh(rcp->len); + + /* Now the second 16-byte BD */ + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + rcph = &((struct rx_pkt_cmpl_hi *)cpr->ring.vaddr)[cpr->cons]; + + flags2 = le32toh(rcph->flags2); + errors = le16toh(rcph->errors_v2); + if ((flags2 & RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK) == + RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) { + ri->iri_flags |= M_VLANTAG; + /* TODO: Should this be the entire 16-bits? */ + ri->iri_vtag = le32toh(rcph->metadata) & + (RX_PKT_CMPL_METADATA_VID_MASK | RX_PKT_CMPL_METADATA_DE | + RX_PKT_CMPL_METADATA_PRI_MASK); + } + if (flags2 & RX_PKT_CMPL_FLAGS2_IP_CS_CALC) { + ri->iri_csum_flags |= CSUM_IP_CHECKED; + if (!(errors & RX_PKT_CMPL_ERRORS_IP_CS_ERROR)) + ri->iri_csum_flags |= CSUM_IP_VALID; + } + if (flags2 & RX_PKT_CMPL_FLAGS2_L4_CS_CALC) { + ri->iri_csum_flags |= CSUM_L4_CALC; + if (!(errors & RX_PKT_CMPL_ERRORS_L4_CS_ERROR)) { + ri->iri_csum_flags |= CSUM_L4_VALID; + ri->iri_csum_data = 0xffff; + } + } + + /* And finally the ag ring stuff. */ + for (i=1; i < ri->iri_nfrags; i++) { + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + acp = &((struct rx_abuf_cmpl *)cpr->ring.vaddr)[cpr->cons]; + + /* No need to byte-swap the opaque value */ + ri->iri_frags[i].irf_flid = (acp->opaque >> 16 & 0xff); + ri->iri_frags[i].irf_idx = acp->opaque & 0xffff; + ri->iri_frags[i].irf_len = le16toh(acp->len); + ri->iri_len += le16toh(acp->len); + } + + return 0; +} + +static int +bnxt_pkt_get_tpa(struct bnxt_softc *softc, if_rxd_info_t ri, + struct bnxt_cp_ring *cpr, uint16_t flags_type) +{ + struct rx_tpa_end_cmpl *agend = + &((struct rx_tpa_end_cmpl *)cpr->ring.vaddr)[cpr->cons]; + struct rx_tpa_end_cmpl_hi *agendh; + struct rx_abuf_cmpl *acp; + struct bnxt_full_tpa_start *tpas; + uint32_t flags2; + uint8_t ags; + uint8_t agg_id; + int i; + + /* Get the agg_id */ + agg_id = (agend->agg_id & RX_TPA_END_CMPL_AGG_ID_MASK) >> + RX_TPA_END_CMPL_AGG_ID_SFT; + tpas = &softc->tpa_start[agg_id]; + + /* Extract from the first 16-byte BD */ + if (le16toh(tpas->low.flags_type) & RX_TPA_START_CMPL_FLAGS_RSS_VALID) { + ri->iri_flowid = le32toh(tpas->low.rss_hash); + /* + * TODO: Extract something useful from tpas->low.rss_hash_type + * (undocumented) + * May be documented in the "LSI ES" + * also check the firmware code. + */ + ri->iri_rsstype = M_HASHTYPE_OPAQUE; + } + else { + ri->iri_rsstype = M_HASHTYPE_NONE; + } + ags = (agend->agg_bufs_v1 & RX_TPA_END_CMPL_AGG_BUFS_MASK) >> + RX_TPA_END_CMPL_AGG_BUFS_SFT; + ri->iri_nfrags = ags + 1; + /* No need to byte-swap the opaque value */ + ri->iri_frags[0].irf_flid = (tpas->low.opaque >> 16) & 0xff; + ri->iri_frags[0].irf_idx = tpas->low.opaque & 0xffff; + ri->iri_frags[0].irf_len = le16toh(tpas->low.len); + ri->iri_len = le16toh(tpas->low.len); + + /* Now the second 16-byte BD */ + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + agendh = &((struct rx_tpa_end_cmpl_hi *)cpr->ring.vaddr)[cpr->cons]; + + flags2 = le32toh(tpas->high.flags2); + if ((flags2 & RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK) == + RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN) { + ri->iri_flags |= M_VLANTAG; + /* TODO: Should this be the entire 16-bits? */ + ri->iri_vtag = le32toh(tpas->high.metadata) & + (RX_TPA_START_CMPL_METADATA_VID_MASK | + RX_TPA_START_CMPL_METADATA_DE | + RX_TPA_START_CMPL_METADATA_PRI_MASK); + } + if (flags2 & RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC) { + ri->iri_csum_flags |= CSUM_IP_CHECKED; + ri->iri_csum_flags |= CSUM_IP_VALID; + } + if (flags2 & RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC) { + ri->iri_csum_flags |= CSUM_L4_CALC; + ri->iri_csum_flags |= CSUM_L4_VALID; + ri->iri_csum_data = 0xffff; + } + + /* Now the ag ring stuff. */ + for (i=1; i < ri->iri_nfrags; i++) { + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + acp = &((struct rx_abuf_cmpl *)cpr->ring.vaddr)[cpr->cons]; + + /* No need to byte-swap the opaque value */ + ri->iri_frags[i].irf_flid = (acp->opaque >> 16) & 0xff; + ri->iri_frags[i].irf_idx = acp->opaque & 0xffff; + ri->iri_frags[i].irf_len = le16toh(acp->len); + ri->iri_len += le16toh(acp->len); + } + + /* And finally, the empty BD at the end... */ + ri->iri_nfrags++; + /* No need to byte-swap the opaque value */ + ri->iri_frags[i].irf_flid = (agend->opaque >> 16) % 0xff; + ri->iri_frags[i].irf_idx = agend->opaque & 0xffff; + ri->iri_frags[i].irf_len = le16toh(agend->len); + ri->iri_len += le16toh(agend->len); + + return 0; +} + +/* If we return anything but zero, iflib will assert... */ +static int +bnxt_isc_rxd_pkt_get(void *sc, if_rxd_info_t ri) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + struct bnxt_cp_ring *cpr = &softc->rx_cp_rings[ri->iri_qsidx]; + struct cmpl_base *cmp; + uint16_t flags_type; + uint16_t type; + + for (;;) { + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + CMPL_PREFETCH_NEXT(cpr, cpr->cons); + cmp = &((struct cmpl_base *)cpr->ring.vaddr)[cpr->cons]; + + flags_type = le16toh(cmp->type); + type = flags_type & CMPL_BASE_TYPE_MASK; + + switch (type) { + case CMPL_BASE_TYPE_RX_L2: + return bnxt_pkt_get_l2(softc, ri, cpr, flags_type); + case CMPL_BASE_TYPE_RX_TPA_END: + return bnxt_pkt_get_tpa(softc, ri, cpr, flags_type); + case CMPL_BASE_TYPE_RX_TPA_START: + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, ri->iri_cidx); + CMPL_PREFETCH_NEXT(cpr, cpr->cons); + break; + default: + device_printf(softc->dev, + "Unhandled completion type %d on RXQ %d get\n", + type, ri->iri_qsidx); + if (type & 1) { + NEXT_CP_CONS_V(&cpr->ring, cpr->cons, + cpr->v_bit); + ri->iri_cidx = RING_NEXT(&cpr->ring, + ri->iri_cidx); + CMPL_PREFETCH_NEXT(cpr, cpr->cons); + } + break; + } + } + + return 0; +} + +static int +bnxt_intr(void *sc) +{ + struct bnxt_softc *softc = (struct bnxt_softc *)sc; + + device_printf(softc->dev, "STUB: %s @ %s:%d\n", __func__, __FILE__, __LINE__); + return ENOSYS; +} Index: sys/dev/bnxt/convert_hsi.pl =================================================================== --- /dev/null +++ sys/dev/bnxt/convert_hsi.pl @@ -0,0 +1,353 @@ +#!/usr/bin/env perl + +my $do_decode = 0; + +if (! -f $ARGV[0]) { + print "Input file not specified (should be path to hsi_struct_defs.h)\n"; + exit 1; +} + +if (!open(IN, "<", $ARGV[0])) { + print "Failure to open input file\n"; + exit 1; +} + +if (!open(OUT, ">", "hsi_struct_def.h")) { + print "Failure to open output file\n"; + exit 1; +} + +$/=undef; +my $header = ; +close IN; + +print OUT <", "hsi_struct_decode.c")) { + print "Failure to open decoder output file\n"; + exit 1; + } + + print OUT <", "hsi_struct_decode.h")) { + print "Failure to open decoder output header file\n"; + exit 1; + } + + print HDR <\n#include \n#include \n#include \"hsi_struct_def_dpdk.h\"\n#include \"hsi_struct_decode.h\"\n#include \"hsi_struct_decode.h\"\n\n"; + print HDR "#ifdef HSI_DEBUG\n#include \"hsi_struct_def_dpdk.h\"\n\n"; + + my $hdr_defs = ''; + + sub print_single_val + { + my $field=shift; + my $type=shift; + my $max_field_len=shift; + my $name = shift; + my $macroshash = shift; + my %macros = %$macroshash; + $macrosref = shift; + my @macros = @$macrosref; + $macrosref = shift; + my @fields = @$macrosref; + + if ($type eq 'uint32_t') { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = 0x%%08\"PRIX32\"\\n\", data->$field);\n",$max_field_len,$field; + } + elsif ($type eq 'uint16_t') { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = 0x%%04\"PRIX16\"\\n\", data->$field);\n",$max_field_len,$field; + } + elsif ($type eq 'uint8_t') { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = 0x%%02\"PRIX8\"\\n\", data->$field);\n",$max_field_len,$field; + } + elsif ($type eq 'uint64_t') { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = 0x%%016\"PRIX64\"\\n\", data->$field);\n",$max_field_len,$field; + } + elsif ($type eq 'char') { + if ($field =~ s/\[([0-9]+)\]//) { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = \\\"%%.$1s\\\"\\n\", data->$field);\n",$max_field_len,$field; + } + else { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s = 0x%%02\"PRIX8\"\\n\", data->$field);\n",$max_field_len,$field; + } + } + else { + print "Unhandled type: '$type'\n"; + } + + my $macro_prefix = uc($name).'_'.uc($field).'_'; + # Special handling for the common flags_type field + $macro_prefix =~ s/FLAGS_TYPE_$/FLAGS_/ if ($field eq 'flags_type'); + # Special handling for _hi types + $macro_prefix =~ s/_HI_/_/ if ($name =~ /_hi$/); + + $macro_prefix =~ s/\[[0-9]+\]//; + my %vmacros; + my $vmacros_have_mask = 0; + my @vmacros; + my %subfields; + my $all_single_bits=1; + MACRO: + foreach my $macro (@macros) { + if ($macro =~ /^$macro_prefix(.*)_MASK$/) { + my $macro = $&; + my $maskdef = $macros{$macro}; + my $subfield = $1; + my $subfield_value = "(data->$field & $macro)"; + if (defined $macros{"$macro_prefix$subfield\_SFT"}) { + $subfield_value = "($subfield_value >> $macro_prefix$subfield\_SFT)"; + } + $maskdef =~ s/[x0 ]//g; + if ($type eq 'uint64_t') { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s $subfield = %%0*\" PRIX64 \"\\n\", %u, $subfield_value);\n", $max_field_len, '', length($maskdef); + } + else { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s $subfield = %%0*X\\n\", %u, $subfield_value);\n", $max_field_len, '', length($maskdef); + } + delete $$macroshash{$macro}; + } + elsif ($macro =~ /^$macro_prefix(.*)_SFT$/) { + delete $$macroshash{$macro}; + } + elsif ($macro =~ /^$macro_prefix\MASK$/) { + $vmacros_have_mask = 1; + delete $$macroshash{$macro}; + } + elsif ($macro =~ /^$macro_prefix(.*)$/) { + my $macro = $&; + my $subfield = $1; + + # Check for longer fields with the same base... ie: link and link_speed + foreach my $extra_field (@fields) { + next if ($extra_field eq $field); + if ($extra_field =~ /^$field/) { + my $extra_prefix = uc($name).'_'.uc($extra_field).'_'; + next MACRO if ($macro =~ /^$extra_prefix/); + } + } + + push @vmacros, $macro; + my $macroeval = $macros{$macro}; + $macroeval =~ s/UINT32_C\((.*?)\)/$1/g; + $vmacros{$macro} = eval("$macroeval"); + $subfields{$macro} = $subfield; + + $all_single_bits = 0 if ($vmacros{$macro} & ($vmacros{$macro}-1)); + $all_single_bits = 0 if ($vmacros{$macro} == 0); + } + } + if ($all_single_bits) { + foreach my $macro (@vmacros) { + my $subfield_value = "(data->$field & $macro)"; + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s $subfields{$macro} : %%s\\n\", $subfield_value?\"ON\":\"OFF\");\n", $max_field_len, ''; + delete $$macroshash{$macro}; + } + } + else { + printf OUT "\tRTE_LOG(DEBUG, PMD, \" % *s Value : %%s\\n\",\n", $max_field_len, ''; + foreach my $macro (@vmacros) { + my $subfield_value = "data->$field"; + $subfield_value = "($subfield_value & $macro_prefix\MASK)" if $vmacros_have_mask; + print OUT "\t\t$subfield_value == $macro ? \"$subfields{$macro}\" :\n"; + delete $$macroshash{$macro}; + } + print OUT "\t\t\"Unknown\");\n"; + } + } + + while ($header =~ /^typedef\s+struct\s+(.*?)\s+{(.*?)^}/msg) { + my ($name,$def) = ($1, $2); + my @fields=(); + my %type=(); + my @macros=(); + my %macros=(); + my $max_field_len=0; + + # First, pull out all the fields in order... + while($def =~ /^\s*([^\s#\/]+?)\s+([^;\/\s]+?)\s*;/mg) { + my ($type, $name) = ($1, $2); + push @fields, $name; + $type{$name}=$type; + $max_field_len = length($name) if length($name) > $max_field_len; + } + # Now, pull out the macros... + while($def =~ /^\s*\#define\s+([^\s]+?)\s+(.*?)\s*$/mg) { + push @macros, $1; + $macros{$1}=$2; + } + + # Now, generate code to print the struct... + print OUT "void decode_$name(const char *string __rte_unused, struct $name *data) {\n\tRTE_LOG(DEBUG, PMD, \"$name\\n\");\n"; + print HDR "void decode_$name(const char *string __rte_unused, struct $name *data);\n"; + $hdr_defs .= "#define decode_$name(x, y) {}\n"; + foreach my $field (@fields) { + if ($field =~ /\[([0-9]+)\]/) { + if ($type{$field} eq 'char') { + print_single_val($field, $type{$field}, $max_field_len, $name, \%macros, \@macros, \@fields); + } + else { + foreach my $idx (0..$1-1) { + my $item = $field; + $item =~ s/\[[0-9]+\]/[$idx]/; + print_single_val($item, $type{$field}, $max_field_len, $name, \%macros, \@macros, \@fields); + } + } + } + else { + print_single_val($field, $type{$field}, $max_field_len, $name, \%macros, \@macros, \@fields); + } + } + # print "Unhandled macros:\n",join("\n", keys %macros),"\n" if (keys %macros > 0); + print OUT "}\n\n"; + } + print OUT "#endif\n"; + + print HDR "#else\n"; + print HDR $hdr_defs; + print HDR "#endif\n"; + close OUT; + close HDR; +} Index: sys/dev/bnxt/hsi_struct_def.h =================================================================== --- /dev/null +++ sys/dev/bnxt/hsi_struct_def.h @@ -0,0 +1,17585 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2014-2015 Broadcom Corporation. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/**************************************************************************** + * Copyright(c) 2001-2016 Broadcom Corporation, all rights reserved + * Proprietary and Confidential Information. + * + * This source file is the property of Broadcom Corporation, and + * may not be copied or distributed in any isomorphic form without + * the prior written consent of Broadcom Corporation. + * + * Name: hsi_struct_def_external.h + * + * Description: Definition of HSI data structures + * + * Date: 07/26/16 21:30:37 + * + * Note: This file is scripted generated by hsi_decode.py. + * DO NOT modify this file manually !!!! + * + ****************************************************************************/ +#ifndef _HSI_STRUCT_DEF_EXTERNAL_H_ +#define _HSI_STRUCT_DEF_EXTERNAL_H_ + +/* + * per-context HW statistics -- chip view + * Reference to stat_ctx_stat_xxx for + */ + +struct ctx_hw_stats { + uint64_t rx_ucast_pkts; + uint64_t rx_mcast_pkts; + uint64_t rx_bcast_pkts; + uint64_t rx_discard_pkts; + uint64_t rx_drop_pkts; + uint64_t rx_ucast_bytes; + uint64_t rx_mcast_bytes; + uint64_t rx_bcast_bytes; + uint64_t tx_ucast_pkts; + uint64_t tx_mcast_pkts; + uint64_t tx_bcast_pkts; + uint64_t tx_discard_pkts; + uint64_t tx_drop_pkts; + uint64_t tx_ucast_bytes; + uint64_t tx_mcast_bytes; + uint64_t tx_bcast_bytes; + uint64_t tpa_pkts; + uint64_t tpa_bytes; + uint64_t tpa_events; + uint64_t tpa_aborts; +} __attribute__((packed)); + +/* BD Ring Structures */ +/* + * Description: This structure is used to inform the NIC of a location for and + * an aggregation buffer that will be used for packet data that is received. An + * aggregation buffer creates a different kind of completion operation for a + * packet where a variable number of BDs may be used to place the packet in the + * host. RX Rings that have aggregation buffers are known as aggregation rings + * and must contain only aggregation buffers. + */ +/* + * Note: BD Ring structures are written by the driver to TX Rings and RX Rings + * to indicate to the chip there is more buffer space in the host that needs to + * be transmitted or is available for receive data. + */ +/* BD Base (8 bytes) */ + +struct bd_base { + uint8_t type; + /* This value identifies the type of buffer descriptor. */ + #define BD_BASE_TYPE_MASK UINT32_C(0x3f) + #define BD_BASE_TYPE_SFT 0 + /* + * Indicates that this BD is 16B long and is used for normal L2 + * packet transmission. + */ + #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0) + /* + * Indicates that this BD is 1BB long and is an empty TX BD. Not + * valid for use by the driver. + */ + #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1) + /* + * Indicates that this BD is 16B long and is an RX Producer (ie. + * empty) buffer descriptor. + */ + #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4) + /* + * Indicates that this BD is 16B long and is an RX Producer + * Buffer BD. + */ + #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5) + /* + * Indicates that this BD is 16B long and is an RX Producer + * Assembly Buffer Descriptor. + */ + #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6) + /* + * Indicates that this BD is 32B long and is used for normal L2 + * packet transmission. + */ + #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10) + uint8_t unused_1[7]; +} __attribute__((packed)); + +/* Short TX BD (16 bytes) */ + +struct tx_bd_short { + uint16_t flags_type; + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_SHORT_TYPE_SFT 0 + /* + * Indicates that this BD is 16B long and is used for normal L2 + * packet transmission. + */ + #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0) + /* + * If set to 1, the packet ends with the data in the buffer pointed to + * by this descriptor. This flag must be valid on every BD. + */ + #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40) + /* + * If set to 1, the device will not generate a completion for this + * transmit packet unless there is an error in it's processing. If this + * bit is set to 0, then the packet will be completed normally. This bit + * must be valid only on the first BD of a packet. + */ + #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80) + /* + * This value indicates how many 16B BD locations are consumed in the + * ring by this packet. A value of 1 indicates that this BD is the only + * BD (and that the it is a short BD). A value of 3 indicates either 3 + * short BDs or 1 long BD and one short BD in the packet. A value of 0 + * indicates that there are 32 BD locations in the packet (the maximum). + * This field is valid only on the first BD of a packet. + */ + #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8 + /* + * This value is a hint for the length of the entire packet. It is used + * by the chip to optimize internal processing. The packet will be + * dropped if the hint is too short. This field is valid only on the + * first BD of a packet. + */ + #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000) + #define TX_BD_SHORT_FLAGS_LHINT_SFT 13 + /* indicates packet length < 512B */ + #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13) + /* indicates 512 <= packet length < 1KB */ + #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13) + /* indicates 1KB <= packet length < 2KB */ + #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13) + /* indicates packet length >= 2KB */ + #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13) + #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K + /* + * If set to 1, the device immediately updates the Send Consumer Index + * after the buffer associated with this descriptor has been transferred + * via DMA to NIC memory from host memory. An interrupt may or may not + * be generated according to the state of the interrupt avoidance + * mechanisms. If this bit is set to 0, then the Consumer Index is only + * updated as soon as one of the host interrupt coalescing conditions + * has been met. This bit must be valid on the first BD of a packet. + */ + #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000) + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_SHORT_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length of the host physical buffer this BD describes in + * bytes. This field must be valid on all BDs of a packet. + */ + uint32_t opaque; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with the + * transmit BD. This field must be valid on the first BD of a packet. + */ + uint64_t addr; + /* + * This is the host physical address for the portion of the packet + * described by this TX BD. This value must be valid on all BDs of a + * packet. + */ +} __attribute__((packed)); + +/* Long TX BD (32 bytes split to 2 16-byte struct) */ + +struct tx_bd_long { + uint16_t flags_type; + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_LONG_TYPE_SFT 0 + /* + * Indicates that this BD is 32B long and is used for normal L2 + * packet transmission. + */ + #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10) + /* + * If set to 1, the packet ends with the data in the buffer pointed to + * by this descriptor. This flag must be valid on every BD. + */ + #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40) + /* + * If set to 1, the device will not generate a completion for this + * transmit packet unless there is an error in it's processing. If this + * bit is set to 0, then the packet will be completed normally. This bit + * must be valid only on the first BD of a packet. + */ + #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80) + /* + * This value indicates how many 16B BD locations are consumed in the + * ring by this packet. A value of 1 indicates that this BD is the only + * BD (and that the it is a short BD). A value of 3 indicates either 3 + * short BDs or 1 long BD and one short BD in the packet. A value of 0 + * indicates that there are 32 BD locations in the packet (the maximum). + * This field is valid only on the first BD of a packet. + */ + #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8 + /* + * This value is a hint for the length of the entire packet. It is used + * by the chip to optimize internal processing. The packet will be + * dropped if the hint is too short. This field is valid only on the + * first BD of a packet. + */ + #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000) + #define TX_BD_LONG_FLAGS_LHINT_SFT 13 + /* indicates packet length < 512B */ + #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13) + /* indicates 512 <= packet length < 1KB */ + #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13) + /* indicates 1KB <= packet length < 2KB */ + #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13) + /* indicates packet length >= 2KB */ + #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13) + #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K + /* + * If set to 1, the device immediately updates the Send Consumer Index + * after the buffer associated with this descriptor has been transferred + * via DMA to NIC memory from host memory. An interrupt may or may not + * be generated according to the state of the interrupt avoidance + * mechanisms. If this bit is set to 0, then the Consumer Index is only + * updated as soon as one of the host interrupt coalescing conditions + * has been met. This bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000) + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0) + #define TX_BD_LONG_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length of the host physical buffer this BD describes in + * bytes. This field must be valid on all BDs of a packet. + */ + uint32_t opaque; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with the + * transmit BD. This field must be valid on the first BD of a packet. + */ + uint64_t addr; + /* + * This is the host physical address for the portion of the packet + * described by this TX BD. This value must be valid on all BDs of a + * packet. + */ +} __attribute__((packed)); + +/* last 16 bytes of Long TX BD */ + +struct tx_bd_long_hi { + uint16_t lflags; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + /* + * If set to 1, the controller replaces the TCP/UPD checksum fields of + * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the + * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP + * checksum for the packet associated with this descriptor. The flag is + * ignored if the LSO flag is set. This bit must be valid on the first + * BD of a packet. + */ + #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the normal + * packets, or the inner IP checksum of the encapsulated packets with + * the hardware calculated IP checksum for the packet associated with + * this descriptor. This bit must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC to the + * end of the frame. This bit must be valid on the first BD of a packet. + * Packet must be 64B or longer when this flag is set. It is not useful + * to use this bit with any form of TX offload such as CSO or LSO. The + * intent is that the packet from the host already has a valid Ethernet + * CRC on the packet. + */ + #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, the device will record the time at which the packet was + * actually transmitted at the TX MAC. This bit must be valid on the + * first BD of a packet. + */ + #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8) + /* + * If set to 1, The controller replaces the tunnel IP checksum field + * with hardware calculated IP checksum for the IP header of the packet + * associated with this descriptor. For outer UDP checksum, global outer + * UDP checksum TE_NIC register needs to be enabled. If the global outer + * UDP checksum TE_NIC register bit is set, outer UDP checksum will be + * calculated for the following cases: 1. Packets with tcp_udp_chksum + * flag set to offload checksum for inner packet AND the inner packet is + * TCP/UDP. If the inner packet is ICMP for example (non-TCP/UDP), even + * if the tcp_udp_chksum is set, the outer UDP checksum will not be + * calculated. 2. Packets with lso flag set which implies inner TCP + * checksum calculation as part of LSO operation. + */ + #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, the device will treat this packet with LSO(Large Send + * Offload) processing for both normal or encapsulated packets, which is + * a form of TCP segmentation. When this bit is 1, the hdr_size and mss + * fields must be valid. The driver doesn't need to set t_ip_chksum, + * ip_chksum, and tcp_udp_chksum flags since the controller will replace + * the appropriate checksum fields for segmented packets. When this bit + * is 1, the hdr_size and mss fields must be valid. + */ + #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20) + /* + * If set to zero when LSO is '1', then the IPID will be treated as a + * 16b number and will be wrapped if it exceeds a value of 0xffff. If + * set to one when LSO is '1', then the IPID will be treated as a 15b + * number and will be wrapped if it exceeds a value 0f 0x7fff. + */ + #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40) + /* + * If set to zero when LSO is '1', then the IPID of the tunnel IP header + * will not be modified during LSO operations. If set to one when LSO is + * '1', then the IPID of the tunnel IP header will be incremented for + * each subsequent segment of an LSO operation. The flag is ignored if + * the LSO packet is a normal (non-tunneled) TCP packet. + */ + #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80) + /* + * If set to '1', then the RoCE ICRC will be appended to the packet. + * Packet must be a valid RoCE format packet. + */ + #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the packet. + * Packet must be a valid FCoE format packet. + */ + #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200) + uint16_t hdr_size; + /* + * When LSO is '1', this field must contain the offset of the TCP + * payload from the beginning of the packet in as 16b words. In case of + * encapsulated/tunneling packet, this field contains the offset of the + * inner TCP payload from beginning of the packet as 16-bit words. This + * value must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff) + #define TX_BD_LONG_HDR_SIZE_SFT 0 + uint32_t mss; + /* + * This is the MSS value that will be used to do the LSO processing. The + * value is the length in bytes of the TCP payload for each segment + * generated by the LSO operation. This value must be valid on the first + * BD of a packet. + */ + #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff) + #define TX_BD_LONG_MSS_SFT 0 + uint16_t unused_2; + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. Set this + * value to zero if no CFA action is desired. This value must be valid + * on the first BD of a packet. + */ + uint32_t cfa_meta; + /* + * This value is action meta-data that defines CFA edit operations that + * are done in addition to any action editing. + */ + /* When key=1, This is the VLAN tag VID value. */ + #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed on the packet. + * This value must be valid on the first BD of a packet. + */ + #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define TX_BD_LONG_CFA_META_KEY_SFT 28 + /* No editing */ + #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12] + * - PRI/DE value. - meta[11:0] - VID value. + */ + #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG +} __attribute__((packed)); + +/* Empty TX BD (16 bytes) */ + +struct tx_bd_empty { + uint8_t type; + /* This value identifies the type of buffer descriptor. */ + #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f) + #define TX_BD_EMPTY_TYPE_SFT 0 + /* + * Indicates that this BD is 1BB long and is an empty TX BD. Not + * valid for use by the driver. + */ + #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1) + uint8_t unused_1[3]; + uint8_t unused_2; + uint8_t unused_3[3]; + uint64_t unused_4; +} __attribute__((packed)); + +/* RX Producer Packet BD (16 bytes) */ + +struct rx_prod_pkt_bd { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f) + #define RX_PROD_PKT_BD_TYPE_SFT 0 + /* + * Indicates that this BD is 16B long and is an RX Producer (ie. + * empty) buffer descriptor. + */ + #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4) + /* + * If set to 1, the packet will be placed at the address plus 2B. The 2 + * Bytes of padding will be written as zero. + */ + /* + * This is intended to be used when the host buffer is cache-line + * aligned to produce packets that are easy to parse in host memory + * while still allowing writes to be cache line aligned. + */ + #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40) + /* + * If set to 1, the packet write will be padded out to the nearest + * cache-line with zero value padding. + */ + /* + * If receive buffers start/end on cache-line boundaries, this feature + * will ensure that all data writes on the PCI bus start/end on cache + * line boundaries. + */ + #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80) + /* + * This value is the number of additional buffers in the ring that + * describe the buffer space to be consumed for the this packet. If the + * value is zero, then the packet must fit within the space described by + * this BD. If this value is 1 or more, it indicates how many additional + * "buffer" BDs are in the ring immediately following this BD to be used + * for the same network packet. Even if the packet to be placed does not + * need all the additional buffers, they will be consumed anyway. + */ + #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300) + #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8 + #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PROD_PKT_BD_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length in Bytes of the host physical buffer where data + * for the packet may be placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provided end on a host cache line. + */ + uint32_t opaque; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with this + * receive buffer set. + */ + uint64_t addr; + /* + * This is the host physical address where data for the packet may by + * placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provide start on a host cache line. + */ +} __attribute__((packed)); + +/* RX Producer Buffer BD (16 bytes) */ + +struct rx_prod_bfr_bd { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f) + #define RX_PROD_BFR_BD_TYPE_SFT 0 + /* + * Indicates that this BD is 16B long and is an RX Producer + * Buffer BD. + */ + #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5) + #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PROD_BFR_BD_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length in Bytes of the host physical buffer where data + * for the packet may be placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provided end on a host cache line. + */ + uint32_t opaque; + /* This field is not used. */ + uint64_t addr; + /* + * This is the host physical address where data for the packet may by + * placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provide start on a host cache line. + */ +} __attribute__((packed)); + +/* RX Producer Aggregation BD (16 bytes) */ + +struct rx_prod_agg_bd { + uint16_t flags_type; + /* This value identifies the type of buffer descriptor. */ + #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f) + #define RX_PROD_AGG_BD_TYPE_SFT 0 + /* + * Indicates that this BD is 16B long and is an RX Producer + * Assembly Buffer Descriptor. + */ + #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6) + /* + * If set to 1, the packet write will be padded out to the nearest + * cache-line with zero value padding. + */ + /* + * If receive buffers start/end on cache-line boundaries, this feature + * will ensure that all data writes on the PCI bus end on cache line + * boundaries. + */ + #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40) + #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PROD_AGG_BD_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length in Bytes of the host physical buffer where data + * for the packet may be placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provided end on a host cache line. + */ + uint32_t opaque; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with this + * receive assembly buffer. + */ + uint64_t addr; + /* + * This is the host physical address where data for the packet may by + * placed in host memory. + */ + /* + * While this is a Byte resolution value, it is often advantageous to + * ensure that the buffers provide start on a host cache line. + */ +} __attribute__((packed)); + +/* Completion Ring Structures */ +/* Note: This structure is used by the HWRM to communicate HWRM Error. */ +/* Base Completion Record (16 bytes) */ + +struct cmpl_base { + uint16_t type; + /* unused is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f) + #define CMPL_BASE_TYPE_SFT 0 + /* TX L2 completion: Completion of TX packet. Length = 16B */ + #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0) + /* RX L2 completion: Completion of and L2 RX packet. Length = 32B */ + #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11) + /* + * RX Aggregation Buffer completion : Completion of an L2 + * aggregation buffer in support of TPA, HDS, or Jumbo packet + * completion. Length = 16B + */ + #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12) + /* + * RX L2 TPA Start Completion: Completion at the beginning of a + * TPA operation. Length = 32B + */ + #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13) + /* + * RX L2 TPA End Completion: Completion at the end of a TPA + * operation. Length = 32B + */ + #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15) + /* + * Statistics Ejection Completion: Completion of statistics data + * ejection buffer. Length = 16B + */ + #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a) + /* HWRM Command Completion: Completion of an HWRM command. */ + #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20) + /* Forwarded HWRM Request */ + #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22) + /* Forwarded HWRM Response */ + #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24) + /* HWRM Asynchronous Event Information */ + #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* CQ Notification */ + #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30) + /* SRQ Threshold Event */ + #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32) + /* DBQ Threshold Event */ + #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34) + /* QP Async Notification */ + #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38) + /* Function Async Notification */ + #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a) + /* unused is 10 b */ + uint16_t info1; + /* info1 is 16 b */ + uint32_t info2; + /* info2 is 32 b */ + uint32_t info3_v; + /* info3 is 31 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define CMPL_BASE_V UINT32_C(0x1) + /* info3 is 31 b */ + #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe) + #define CMPL_BASE_INFO3_SFT 1 + uint32_t info4; + /* info4 is 32 b */ +} __attribute__((packed)); + +/* TX Completion Record (16 bytes) */ + +struct tx_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define TX_CMPL_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_TYPE_SFT 0 + /* TX L2 completion: Completion of TX packet. Length = 16B */ + #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0) + /* + * When this bit is '1', it indicates a packet that has an error of some + * type. Type of error is indicated in error_flags. + */ + #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet completed was + * transmitted using the push acceleration data provided by the driver. + * When this bit is '0', it indicates that the packet had not push + * acceleration data written or was executed as a normal packet even + * though push data was provided. + */ + #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80) + #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define TX_CMPL_FLAGS_SFT 6 + uint16_t unused_0; + /* unused1 is 16 b */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the first TX BD of this + * transmitted packet. + */ + uint16_t errors_v; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define TX_CMPL_V UINT32_C(0x1) + /* + * This error indicates that there was some sort of problem with the BDs + * for the packet. + */ + #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No error */ + #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1) + /* Bad Format: BDs were not formatted correctly. */ + #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1) + #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT + /* + * When this bit is '1', it indicates that the length of the packet was + * zero. No packet was transmitted. + */ + #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) + /* + * When this bit is '1', it indicates that the packet was longer than + * the programmed limit in TDI. No packet was transmitted. + */ + #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + /* + * When this bit is '1', it indicates that one or more of the BDs + * associated with this packet generated a PCI error. This probably + * means the address was not valid. + */ + #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40) + /* + * When this bit is '1', it indicates that the packet was longer than + * indicated by the hint. No packet was transmitted. + */ + #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + /* + * When this bit is '1', it indicates that the packet was dropped due to + * Poison TLP error on one or more of the TLPs in the PXP completion. + */ + #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define TX_CMPL_ERRORS_SFT 1 + uint16_t unused_1; + /* unused2 is 16 b */ + uint32_t unused_2; + /* unused3 is 32 b */ +} __attribute__((packed)); + +/* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */ + +struct rx_pkt_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_PKT_CMPL_TYPE_SFT 0 + /* RX L2 completion: Completion of and L2 RX packet. Length = 32B */ + #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11) + /* + * When this bit is '1', it indicates a packet that has an error of some + * type. Type of error is indicated in error_flags. + */ + #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7 + /* Normal: Packet was placed using normal algorithm. */ + #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7) + /* Jumbo: Packet was placed using jumbo algorithm. */ + #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: Packet was placed using Header/Data + * separation algorithm. The separation location is indicated by + * the itype field. + */ + #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7) + #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_CMPL_FLAGS_PLACEMENT_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + /* + * This value indicates what the inner packet determined for the packet + * was. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12 + /* Not Known: Indicates that the packet type was not known. */ + #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12) + /* + * IP Packet: Indicates that the packet was an IP packet, but + * further classification was not possible. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12) + /* + * TCP Packet: Indicates that the packet was IP and TCP. This + * indicates that the payload_offset field is valid. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12) + /* + * UDP Packet: Indicates that the packet was IP and UDP. This + * indicates that the payload_offset field is valid. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12) + /* + * FCoE Packet: Indicates that the packet was recognized as a + * FCoE. This also indicates that the payload_offset field is + * valid. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12) + /* + * RoCE Packet: Indicates that the packet was recognized as a + * RoCE. This also indicates that the payload_offset field is + * valid. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12) + /* + * ICMP Packet: Indicates that the packet was recognized as + * ICMP. This indicates that the payload_offset field is valid. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12) + /* + * PtP packet wo/timestamp: Indicates that the packet was + * recognized as a PtP packet. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12) + /* + * PtP packet w/timestamp: Indicates that the packet was + * recognized as a PtP packet and that a timestamp was taken for + * the packet. + */ + #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12) + #define RX_PKT_CMPL_FLAGS_ITYPE_LAST RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP + #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_PKT_CMPL_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length of the data for the packet stored in the buffer(s) + * identified by the opaque value. This includes the packet BD and any + * associated buffer BDs. This does not include the the length of any + * data places in aggregation BDs. + */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint8_t agg_bufs_v1; + /* unused1 is 2 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_PKT_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this packet. If the + * value is zero, then the packet is completely contained in the buffer + * space provided for the packet in the RX ring. + */ + #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e) + #define RX_PKT_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 2 b */ + uint8_t rss_hash_type; + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + */ + uint8_t payload_offset; + /* + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. A value of zero indicates that header is + * 256B into the packet. + */ + uint8_t unused_1; + /* unused2 is 8 b */ + uint32_t rss_hash; + /* + * This value is the RSS hash value calculated for the packet based on + * the mode bits and key value in the VNIC. + */ +} __attribute__((packed)); + +/* last 16 bytes of RX Packet Completion Record */ + +struct rx_pkt_cmpl_hi { + uint32_t flags2; + /* + * This indicates that the ip checksum was calculated for the inner + * packet and that the ip_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + /* + * This indicates that the TCP, UDP or ICMP checksum was calculated for + * the inner packet and that the l4_cs_error field indicates if there + * was an error. + */ + #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + /* + * This indicates that the ip checksum was calculated for the tunnel + * header and that the t_ip_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + /* + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the t_l4_cs_error field indicates if there was an + * error. + */ + #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata informtaion. Value is zero. */ + #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) + /* + * The metadata field contains the VLAN tag and TPID value. - + * metadata[11:0] contains the vlan VID value. - metadata[12] + * contains the vlan DE value. - metadata[15:13] contains the + * vlan PRI value. - metadata[31:16] contains the vlan TPID + * value. + */ + #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4) + #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN + /* + * This field indicates the IP type for the inner-most IP header. A + * value of '0' indicates IPv4. A value of '1' indicates IPv6. This + * value is only valid if itype indicates a packet with an IP header. + */ + #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + uint32_t metadata; + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_PKT_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_PKT_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_PKT_CMPL_METADATA_TPID_SFT 16 + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_PKT_CMPL_V2 UINT32_C(0x1) + /* + * This error indicates that there was some sort of problem with the BDs + * for the packet that was found after part of the packet was already + * placed. The packet should be treated as invalid. + */ + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* No buffer error */ + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1) + /* + * Did Not Fit: Packet did not fit into packet buffer provided. + * For regular placement, this means the packet did not fit in + * the buffer provided. For HDS and jumbo placement, this means + * that the packet could not be placed into 7 physical buffers + * or less. + */ + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1) + /* + * Not On Chip: All BDs needed for the packet were not on-chip + * when the packet arrived. + */ + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1) + /* Bad Format: BDs were not formatted correctly. */ + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1) + #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT + /* This indicates that there was an error in the IP header checksum. */ + #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10) + /* + * This indicates that there was an error in the TCP, UDP or ICMP + * checksum. + */ + #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20) + /* + * This indicates that there was an error in the tunnel IP header + * checksum. + */ + #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40) + /* This indicates that there was an error in the tunnel UDP checksum. */ + #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80) + /* + * This indicates that there was a CRC error on either an FCoE or RoCE + * packet. The itype indicates the packet type. + */ + #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100) + /* + * This indicates that there was an error in the tunnel portion of the + * packet when this field is non-zero. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00) + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9 + /* + * No additional error occurred on the tunnel portion of the + * packet of the packet does not have a tunnel. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 in the tunnel header. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9) + /* + * Indicates that header length is out of range in the tunnel + * header. Valid for IPv4. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the PPPoE header length for a tunnel PPPoE packet. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9) + /* + * Indicates that physical packet is shorter than that claimed + * by the tunnel l3 header length. Valid for IPv4, or IPv6 + * tunnel packet packets. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9) + /* + * Indicates that the physical packet is shorter than that + * claimed by the tunnel UDP header length for a tunnel UDP + * packet that is not fragmented. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check have + * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4, + * and IPv6. + */ + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9) + #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL + /* + * This indicates that there was an error in the inner portion of the + * packet when this field is non-zero. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000) + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12 + /* + * No additional error occurred on the tunnel portion of the + * packet of the packet does not have a tunnel. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12) + /* + * Indicates that IP header version does not match expectation + * from L2 Ethertype for IPv4 and IPv6 or that option other than + * VFT was parsed on FCoE packet. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12) + /* + * indicates that header length is out of range. Valid for IPv4 + * and RoCE + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12) + /* + * indicates that the IPv4 TTL or IPv6 hop limit check have + * failed (e.g. TTL = 0). Valid for IPv4, and IPv6 + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12) + /* + * Indicates that physical packet is shorter than that claimed + * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE + * packets. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12) + /* + * Indicates that the physical packet is shorter than that + * claimed by the UDP header length for a UDP packet that is not + * fragmented. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12) + /* + * Indicates that TCP header length > IP payload. Valid for TCP + * packets only. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12) + /* Indicates that TCP header length < 5. Valid for TCP. */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12) + /* + * Indicates that TCP option headers result in a TCP header size + * that does not match data offset in TCP header. Valid for TCP. + */ + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12) + #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN + #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_PKT_CMPL_ERRORS_SFT 1 + uint16_t cfa_code; + /* + * This field identifies the CFA action rule that was used for this + * packet. + */ + uint32_t reorder; + /* + * This value holds the reordering sequence number for the packet. If + * the reordering sequence is not valid, then this value is zero. The + * reordering domain for the packet is in the bottom 8 to 10b of the + * rss_hash value. The bottom 20b of this value contain the ordering + * domain value for the packet. + */ + #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff) + #define RX_PKT_CMPL_REORDER_SFT 0 +} __attribute__((packed)); + +/* RX L2 TPA Start Completion Record (32 bytes split to 2 16-byte struct) */ + +struct rx_tpa_start_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_START_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA Start Completion: Completion at the beginning of a + * TPA operation. Length = 32B + */ + #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13) + /* This bit will always be '0' for TPA start completions. */ + #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: TPA Packet was placed using jumbo algorithm. This + * means that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer will + * be filled before moving to the next aggregation buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: Packet was placed using Header/Data + * separation algorithm. The separation location is indicated by + * the itype field. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7) + /* + * GRO/Jumbo: Packet will be placed using GRO/Jumbo where the + * first packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two aggregation + * buffers unless it starts at the beginning of an aggregation + * buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: Packet will be placed using + * GRO/HDS where the header is in the first packet. Payload of + * each packet will be placed such that any one packet does not + * span two aggregation buffers unless it starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7) + #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* This bit is '1' if the RSS field in this completion is valid. */ + #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400) + /* unused is 1 b */ + /* + * This value indicates what the inner packet determined for the packet + * was. + */ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12 + /* TCP Packet: Indicates that the packet was IP and TCP. */ + #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12) + #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST RX_TPA_START_CMPL_FLAGS_ITYPE_TCP + #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_START_CMPL_FLAGS_SFT 6 + uint16_t len; + /* + * This value indicates the amount of packet data written to the buffer + * the opaque field in this completion corresponds to. + */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint8_t v1; + /* unused1 is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_TPA_START_CMPL_V1 UINT32_C(0x1) + /* unused1 is 7 b */ + uint8_t rss_hash_type; + /* + * This is the RSS hash type for the packet. The value is packed + * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. + */ + uint16_t agg_id; + /* + * This is the aggregation ID that the completion is associated with. + * Use this number to correlate the TPA start completion with the TPA + * end completion. + */ + /* unused2 is 9 b */ + /* + * This is the aggregation ID that the completion is associated with. + * Use this number to correlate the TPA start completion with the TPA + * end completion. + */ + #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00) + #define RX_TPA_START_CMPL_AGG_ID_SFT 9 + uint32_t rss_hash; + /* + * This value is the RSS hash value calculated for the packet based on + * the mode bits and key value in the VNIC. + */ +} __attribute__((packed)); + +/* last 16 bytes of RX L2 TPA Start Completion Record */ + +struct rx_tpa_start_cmpl_hi { + uint32_t flags2; + /* + * This indicates that the ip checksum was calculated for the inner + * packet and that the sum passed for all segments included in the + * aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1) + /* + * This indicates that the TCP, UDP or ICMP checksum was calculated for + * the inner packet and that the sum passed for all segments included in + * the aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2) + /* + * This indicates that the ip checksum was calculated for the tunnel + * header and that the sum passed for all segments included in the + * aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4) + /* + * This indicates that the UDP checksum was calculated for the tunnel + * packet and that the sum passed for all segments included in the + * aggregation. + */ + #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8) + /* This value indicates what format the metadata field is. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4 + /* No metadata informtaion. Value is zero. */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4) + /* + * The metadata field contains the VLAN tag and TPID value. - + * metadata[11:0] contains the vlan VID value. - metadata[12] + * contains the vlan DE value. - metadata[15:13] contains the + * vlan PRI value. - metadata[31:16] contains the vlan TPID + * value. + */ + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4) + #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN + /* + * This field indicates the IP type for the inner-most IP header. A + * value of '0' indicates IPv4. A value of '1' indicates IPv6. + */ + #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100) + uint32_t metadata; + /* + * This is data from the CFA block as indicated by the meta_format + * field. + */ + /* When meta_format=1, this value is the VLAN VID. */ + #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff) + #define RX_TPA_START_CMPL_METADATA_VID_SFT 0 + /* When meta_format=1, this value is the VLAN DE. */ + #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000) + /* When meta_format=1, this value is the VLAN PRI. */ + #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000) + #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13 + /* When meta_format=1, this value is the VLAN TPID. */ + #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000) + #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16 + uint16_t v2; + /* unused4 is 15 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_TPA_START_CMPL_V2 UINT32_C(0x1) + /* unused4 is 15 b */ + uint16_t cfa_code; + /* + * This field identifies the CFA action rule that was used for this + * packet. + */ + uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset; + /* + * This is the size in bytes of the inner most L4 header. This can be + * subtracted from the payload_offset to determine the start of the + * inner most L4 header. + */ + /* + * This is the offset from the beginning of the packet in bytes for the + * outer L3 header. If there is no outer L3 header, then this value is + * zero. + */ + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff) + #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0 + /* + * This is the offset from the beginning of the packet in bytes for the + * inner most L2 header. + */ + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00) + #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9 + /* + * This is the offset from the beginning of the packet in bytes for the + * inner most L3 header. + */ + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000) + #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18 + /* + * This is the size in bytes of the inner most L4 header. This can be + * subtracted from the payload_offset to determine the start of the + * inner most L4 header. + */ + #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000) + #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27 +} __attribute__((packed)); + +/* RX TPA End Completion Record (32 bytes split to 2 16-byte struct) */ + +struct rx_tpa_end_cmpl { + uint16_t flags_type; + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_TPA_END_CMPL_TYPE_SFT 0 + /* + * RX L2 TPA End Completion: Completion at the end of a TPA + * operation. Length = 32B + */ + #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15) + /* + * When this bit is '1', it indicates a packet that has an error of some + * type. Type of error is indicated in error_flags. + */ + #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40) + /* This field indicates how the packet was placed in the buffer. */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7 + /* + * Jumbo: TPA Packet was placed using jumbo algorithm. This + * means that the first buffer will be filled with data before + * moving to aggregation buffers. Each aggregation buffer will + * be filled before moving to the next aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7) + /* + * Header/Data Separation: Packet was placed using Header/Data + * separation algorithm. The separation location is indicated by + * the itype field. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7) + /* + * GRO/Jumbo: Packet will be placed using GRO/Jumbo where the + * first packet is filled with data. Subsequent packets will be + * placed such that any one packet does not span two aggregation + * buffers unless it starts at the beginning of an aggregation + * buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7) + /* + * GRO/Header-Data Separation: Packet will be placed using + * GRO/HDS where the header is in the first packet. Payload of + * each packet will be placed such that any one packet does not + * span two aggregation buffers unless it starts at the + * beginning of an aggregation buffer. + */ + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7) + #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS + /* unused is 2 b */ + /* + * This value indicates what the inner packet determined for the packet + * was. - 2 TCP Packet Indicates that the packet was IP and TCP. This + * indicates that the ip_cs field is valid and that the tcp_udp_cs field + * is valid and contains the TCP checksum. This also indicates that the + * payload_offset field is valid. + */ + #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000) + #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12 + #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0) + #define RX_TPA_END_CMPL_FLAGS_SFT 6 + uint16_t len; + /* + * This value is zero for TPA End completions. There is no data in the + * buffer that corresponds to the opaque value in this completion. + */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the RX BD this completion + * corresponds to. + */ + uint8_t agg_bufs_v1; + /* unused1 is 1 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V1 UINT32_C(0x1) + /* + * This value is the number of aggregation buffers that follow this + * entry in the completion ring that are a part of this aggregation + * packet. If the value is zero, then the packet is completely contained + * in the buffer space provided in the aggregation start completion. + */ + #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e) + #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1 + /* unused1 is 1 b */ + uint8_t tpa_segs; + /* This value is the number of segments in the TPA operation. */ + uint8_t payload_offset; + /* + * This value indicates the offset in bytes from the beginning of the + * packet where the inner payload starts. This value is valid for TCP, + * UDP, FCoE, and RoCE packets. A value of zero indicates an offset of + * 256 bytes. + */ + uint8_t agg_id; + /* + * This is the aggregation ID that the completion is associated with. + * Use this number to correlate the TPA start completion with the TPA + * end completion. + */ + /* unused2 is 1 b */ + /* + * This is the aggregation ID that the completion is associated with. + * Use this number to correlate the TPA start completion with the TPA + * end completion. + */ + #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe) + #define RX_TPA_END_CMPL_AGG_ID_SFT 1 + uint32_t tsdelta; + /* + * For non-GRO packets, this value is the timestamp delta between + * earliest and latest timestamp values for TPA packet. If packets were + * not time stamped, then delta will be zero. For GRO packets, this + * field is zero except for the following sub-fields. - tsdelta[31] + * Timestamp present indication. When '0', no Timestamp option is in the + * packet. When '1', then a Timestamp option is present in the packet. + */ +} __attribute__((packed)); + +/* last 16 bytes of RX TPA End Completion Record */ + +struct rx_tpa_end_cmpl_hi { + uint32_t tpa_dup_acks; + /* unused3 is 28 b */ + /* + * This value is the number of duplicate ACKs that have been received as + * part of the TPA operation. + */ + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf) + #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0 + /* unused3 is 28 b */ + uint16_t tpa_seg_len; + /* + * This value is the valid when TPA completion is active. It indicates + * the length of the longest segment of the TPA operation for LRO mode + * and the length of the first segment in GRO mode. This value may be + * used by GRO software to re-construct the original packet stream from + * the TPA packet. This is the length of all but the last segment for + * GRO. In LRO mode this value may be used to indicate MSS size to the + * stack. + */ + uint16_t unused_3; + /* unused4 is 16 b */ + uint16_t errors_v2; + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_TPA_END_CMPL_V2 UINT32_C(0x1) + /* + * This error indicates that there was some sort of problem with the BDs + * for the packet that was found after part of the packet was already + * placed. The packet should be treated as invalid. + */ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1 + /* + * This error occurs when there is a fatal HW problem in the + * chip only. It indicates that there were not BDs on chip but + * that there was adequate reservation. provided by the TPA + * block. + */ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1) + /* + * This error occurs when TPA block was not configured to + * reserve adequate BDs for TPA operations on this RX ring. All + * data for the TPA operation was not placed. This error can + * also be generated when the number of segments is not + * programmed correctly in TPA and the 33 total aggregation + * buffers allowed for the TPA operation has been exceeded. + */ + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1) + #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR + #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe) + #define RX_TPA_END_CMPL_ERRORS_SFT 1 + uint16_t unused_4; + /* unused5 is 16 b */ + uint32_t start_opaque; + /* + * This is the opaque value that was completed for the TPA start + * completion that corresponds to this TPA end completion. + */ +} __attribute__((packed)); + +/* RX Aggregation Buffer Completion Record (16 bytes) */ + +struct rx_abuf_cmpl { + uint16_t type; + /* unused is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f) + #define RX_ABUF_CMPL_TYPE_SFT 0 + /* + * RX Aggregation Buffer completion : Completion of an L2 + * aggregation buffer in support of TPA, HDS, or Jumbo packet + * completion. Length = 16B + */ + #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12) + /* unused is 10 b */ + uint16_t len; + /* + * This is the length of the data for the packet stored in this + * aggregation buffer identified by the opaque value. This does not + * include the length of any data placed in other aggregation BDs or in + * the packet or buffer BDs. This length does not include any space + * added due to hdr_offset register during HDS placement mode. + */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the RX BD this aggregation + * buffer corresponds to. + */ + uint32_t v; + /* unused2 is 31 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define RX_ABUF_CMPL_V UINT32_C(0x1) + /* unused2 is 31 b */ + uint32_t unused_2; + /* unused3 is 32 b */ +} __attribute__((packed)); + +/* Statistics Ejection Buffer Completion Record (16 bytes) */ + +struct eject_cmpl { + uint16_t type; + /* unused is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define EJECT_CMPL_TYPE_SFT 0 + /* + * Statistics Ejection Completion: Completion of statistics data + * ejection buffer. Length = 16B + */ + #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a) + /* unused is 10 b */ + uint16_t len; + /* This is the length of the statistics data stored in this buffer. */ + uint32_t opaque; + /* + * This is a copy of the opaque field from the RX BD this ejection + * buffer corresponds to. + */ + uint32_t v; + /* unused2 is 31 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define EJECT_CMPL_V UINT32_C(0x1) + /* unused2 is 31 b */ + uint32_t unused_2; + /* unused3 is 32 b */ +} __attribute__((packed)); + +/* HWRM Completion Record (16 bytes) */ + +struct hwrm_cmpl { + uint16_t type; + /* unused is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_CMPL_TYPE_SFT 0 + /* HWRM Command Completion: Completion of an HWRM command. */ + #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20) + /* unused is 10 b */ + uint16_t sequence_id; + /* This is the sequence_id of the HWRM command that has completed. */ + uint32_t unused_1; + /* unused2 is 32 b */ + uint32_t v; + /* unused3 is 31 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_CMPL_V UINT32_C(0x1) + /* unused3 is 31 b */ + uint32_t unused_3; + /* unused4 is 32 b */ +} __attribute__((packed)); + +/* HWRM Forwarded Request (16 bytes) */ + +struct hwrm_fwd_req_cmpl { + uint16_t req_len_type; + /* Length of forwarded request in bytes. */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Request */ + #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22) + /* Length of forwarded request in bytes. */ + #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0) + #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 + uint16_t source_id; + /* + * Source ID of this request. Typically used in forwarding requests and + * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE - + * Reserved for internal processors 0xFFFF - HWRM + */ + uint32_t unused_0; + /* unused1 is 32 b */ + uint64_t req_buf_addr_v; + /* Address of forwarded request. */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1) + /* Address of forwarded request. */ + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 +} __attribute__((packed)); + +/* HWRM Forwarded Response (16 bytes) */ + +struct hwrm_fwd_resp_cmpl { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 + /* Forwarded HWRM Response */ + #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24) + /* unused1 is 10 b */ + uint16_t source_id; + /* + * Source ID of this response. Typically used in forwarding requests and + * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE - + * Reserved for internal processors 0xFFFF - HWRM + */ + uint16_t resp_len; + /* Length of forwarded response in bytes. */ + uint16_t unused_1; + /* unused2 is 16 b */ + uint64_t resp_buf_addr_v; + /* Address of forwarded response. */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1) + /* Address of forwarded response. */ + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe) + #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 +} __attribute__((packed)); + +#define GET_EVENT_ID(x) \ + ((x) == 0x30 ? "VF_FLR": \ + ((x) == 0x20 ? "PF_DRVR_UNLOAD": \ + ((x) == 0x10 ? "FUNC_DRVR_UNLOAD": \ + ((x) == 0xff ? "HWRM_ERROR": \ + ((x) == 0x32 ? "PF_VF_COMM_STATUS_CHANGE": \ + ((x) == 0x33 ? "VF_CFG_CHANGE": \ + ((x) == 0x11 ? "FUNC_DRVR_LOAD": \ + ((x) == 0x31 ? "VF_MAC_ADDR_CHANGE": \ + ((x) == 0x4 ? "PORT_CONN_NOT_ALLOWED": \ + ((x) == 0x5 ? "LINK_SPEED_CFG_NOT_ALLOWED": \ + ((x) == 0x6 ? "LINK_SPEED_CFG_CHANGE": \ + ((x) == 0x7 ? "PORT_PHY_CFG_CHANGE": \ + ((x) == 0x0 ? "LINK_STATUS_CHANGE": \ + ((x) == 0x1 ? "LINK_MTU_CHANGE": \ + ((x) == 0x2 ? "LINK_SPEED_CHANGE": \ + ((x) == 0x3 ? "DCB_CONFIG_CHANGE": \ + ((x) == 0x12 ? "FUNC_FLR_PROC_CMPLT": \ + ((x) == 0x21 ? "PF_DRVR_LOAD": \ + "Unknown event_id")))))))))))))))))) + +/* HWRM Asynchronous Event Completion Record (16 bytes) */ + +struct hwrm_async_event_cmpl { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0) + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1) + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2) + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3) + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4) + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5) + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6) + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7) + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10) + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11) + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12) + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20) + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21) + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR UINT32_C(0x30) + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31) + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32) + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33) + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ + +struct hwrm_async_event_cmpl_link_status_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link status changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* Indicates link status change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE UINT32_C(0x1) + /* + * If this bit set to 0, then it indicates that the link was up + * and it went down. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (UINT32_C(0x0) << 0) + /* + * If this bit is set to 1, then it indicates that the link was + * down and it went up. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (UINT32_C(0x1) << 0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP + /* Indicates the physical port this link status change occur */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0xe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0) + #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ + +struct hwrm_async_event_cmpl_link_mtu_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link MTU changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* The new MTU of the link in bytes. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ + +struct hwrm_async_event_cmpl_link_speed_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link speed changed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* + * When this bit is '1', the link was forced to the force_link_speed + * value. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE UINT32_C(0x1) + /* The new link speed in 100 Mbps units. */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK UINT32_C(0xfffe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 + /* 100Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (UINT32_C(0x1) << 1) + /* 1Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (UINT32_C(0xa) << 1) + /* 2Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (UINT32_C(0x14) << 1) + /* 2.5Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (UINT32_C(0x19) << 1) + /* 10Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (UINT32_C(0x64) << 1) + /* 20Mb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (UINT32_C(0xc8) << 1) + /* 25Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (UINT32_C(0xfa) << 1) + /* 40Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (UINT32_C(0x190) << 1) + /* 50Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (UINT32_C(0x1f4) << 1) + /* 100Gb link speed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (UINT32_C(0x3e8) << 1) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0000) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ + +struct hwrm_async_event_cmpl_dcb_config_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* DCB Configuration changed */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ + +struct hwrm_async_event_cmpl_port_conn_not_allowed { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Port connection not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 + /* + * This value indicates the current port level enforcement policy for + * the optics module when there is an optical module mismatch and port + * is not connected. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK UINT32_C(0xff0000) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 + /* No enforcement */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (UINT32_C(0x0) << 16) + /* Disable Transmit side Laser. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (UINT32_C(0x1) << 16) + /* Raise a warning message. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (UINT32_C(0x2) << 16) + /* Power down the module. */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (UINT32_C(0x3) << 16) + #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ + +struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link speed configuration was not allowed */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ + +struct hwrm_async_event_cmpl_link_speed_cfg_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Link speed configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 + /* + * If set to 1, it indicates that the supported link speeds + * configuration on the port has changed. If set to 0, then there is no + * change in supported link speeds configuration. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE UINT32_C(0x10000) + /* + * If set to 1, it indicates that the link speed configuration on the + * port has become illegal or invalid. If set to 0, then the link speed + * configuration on the port is legal or valid. + */ + #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG UINT32_C(0x20000) +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for port PHY configuration change (16 bytes) */ + +struct hwrm_async_event_cmpl_port_phy_cfg_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Port PHY configuration change */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PORT ID */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 + /* + * If set to 1, it indicates that the FEC configuration on the port has + * changed. If set to 0, then there is no change in FEC configuration. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE UINT32_C(0x10000) + /* + * If set to 1, it indicates that the EEE configuration on the port has + * changed. If set to 0, then there is no change in EEE configuration on + * the port. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE UINT32_C(0x20000) + /* + * If set to 1, it indicates that the pause configuration on the PHY has + * changed. If set to 0, then there is no change in the pause + * configuration on the PHY. + */ + #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE UINT32_C(0x40000) +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ + +struct hwrm_async_event_cmpl_func_drvr_unload { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Function driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ + +struct hwrm_async_event_cmpl_func_drvr_load { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Function driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ + +struct hwrm_async_event_cmpl_func_flr_proc_cmplt { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* Function FLR related processing has completed */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* Function ID */ + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ + +struct hwrm_async_event_cmpl_pf_drvr_unload { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* PF driver unloaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ + +struct hwrm_async_event_cmpl_pf_drvr_load { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* PF driver loaded */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* PF ID */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 + /* Indicates the physical port this pf belongs to */ + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000) + #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ + +struct hwrm_async_event_cmpl_vf_flr { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* VF Function Level Reset (FLR) */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ + +struct hwrm_async_event_cmpl_vf_mac_addr_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* VF MAC Address Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* VF ID */ + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff) + #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ + +struct hwrm_async_event_cmpl_pf_vf_comm_status_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* PF-VF communication channel status change. */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* + * If this bit is set to 1, then it indicates that the PF-VF + * communication was lost and it is established. If this bit set to 0, + * then it indicates that the PF-VF communication was established and it + * is lost. + */ + #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED UINT32_C(0x1) +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ + +struct hwrm_async_event_cmpl_vf_cfg_change { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* VF Configuration Change */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33) + uint32_t event_data2; + /* Event specific data */ + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* + * Each flag provided in this field indicates a specific VF + * configuration change. At least one of these flags shall be set to 1 + * when an asynchronous event completion of this type is provided by the + * HWRM. + */ + /* + * If this bit is set to 1, then the value of MTU was changed on this + * VF. If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE UINT32_C(0x1) + /* + * If this bit is set to 1, then the value of MRU was changed on this + * VF. If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE UINT32_C(0x2) + /* + * If this bit is set to 1, then the value of default MAC address was + * changed on this VF. If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE UINT32_C(0x4) + /* + * If this bit is set to 1, then the value of default VLAN was changed + * on this VF. If set to 0, then this bit should be ignored. + */ + #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE UINT32_C(0x8) +} __attribute__((packed)); + +/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ + +struct hwrm_async_event_cmpl_hwrm_error { + uint16_t type; + /* unused1 is 10 b */ + /* + * This field indicates the exact type of the completion. By convention, + * the LSB identifies the length of the record in 16B units. Even values + * indicate 16B records. Odd values indicate 32B records. + */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e) + /* unused1 is 10 b */ + uint16_t event_id; + /* Identifiers of events. */ + /* HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR UINT32_C(0xff) + uint32_t event_data2; + /* Event specific data */ + /* Severity of HWRM Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK UINT32_C(0xff) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 + /* Warning */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING UINT32_C(0x0) + /* Non-fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL UINT32_C(0x1) + /* Fatal Error */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL UINT32_C(0x2) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL + uint8_t opaque_v; + /* opaque is 7 b */ + /* + * This value is written by the NIC such that it will be different for + * each pass through the completion queue. The even passes will write 1. + * The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 + uint8_t timestamp_lo; + /* 8-lsb timestamp from POR (100-msec resolution) */ + uint16_t timestamp_hi; + /* 16-lsb timestamp from POR (100-msec resolution) */ + uint32_t event_data1; + /* Event specific data */ + /* Time stamp for error event */ + #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP UINT32_C(0x1) +} __attribute__((packed)); + +/* Door Bell Formats */ +/* + * Description: The backup version of the packet must be valid in the TX ring + * before the push doorbell is written to the chip. The first 32b and the BD + * portion of the push doorbell must be written in multiples of 32b units on the + * PCI interface. The data portion of the push doorbell may be written in + * multiples of 8b units on the PCI interface. A push update must contain + * exactly one push packet. The backup version of the packet must start with a + * long (32B) BD and the BDs must be less than or equal to 16x16B units long. + */ +/* + * Note: This door bell format is used by the driver when it wants to push a + * packet into the chip for super-fast transmission. This pushes a partial BD + * and the packet data into the chip. If the chip has room, it will transmit the + * packet. If the chip dosn't have room, it will read the BD and packet data + * from host memory as a normal packet. + */ +/* TX Door Bell Format (4 bytes) */ + +struct tx_doorbell { + uint32_t key_idx; + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '0' for TX door bell operations. + */ + /* + * BD Index of next BD that will be used to transmit data on the TX ring + * mapped to this door bell. NIC may read and process all BDs up to, but + * not including this index. + */ + #define TX_DOORBELL_IDX_MASK UINT32_C(0xffffff) + #define TX_DOORBELL_IDX_SFT 0 + /* reserved is 4 b */ + #define TX_DOORBELL_RESERVED_MASK UINT32_C(0xf000000) + #define TX_DOORBELL_RESERVED_SFT 24 + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '0' for TX door bell operations. + */ + #define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) + #define TX_DOORBELL_KEY_SFT 28 + /* TX Operation */ + #define TX_DOORBELL_KEY_TX (UINT32_C(0x0) << 28) +} __attribute__((packed)); + +/* RX Door Bell Format (4 bytes) */ + +struct rx_doorbell { + uint32_t key_idx; + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '1' for RX door bell operations. + */ + /* + * BD Index of next BD that will be used for an empty receive buffer on + * the RX ring mapped to this door bell. NIC may read and process all + * BDs up to, but not including this index. + */ + #define RX_DOORBELL_IDX_MASK UINT32_C(0xffffff) + #define RX_DOORBELL_IDX_SFT 0 + /* reserved is 4 b */ + #define RX_DOORBELL_RESERVED_MASK UINT32_C(0xf000000) + #define RX_DOORBELL_RESERVED_SFT 24 + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '1' for RX door bell operations. + */ + #define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000) + #define RX_DOORBELL_KEY_SFT 28 + /* RX Operation */ + #define RX_DOORBELL_KEY_RX (UINT32_C(0x1) << 28) +} __attribute__((packed)); + +/* CMP Door Bell Format (4 bytes) */ + +struct cmpl_doorbell { + uint32_t key_mask_valid_idx; + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '2' for CMP door bell operations. + */ + /* + * BD Index of the most recently handed completion record on the + * completion ring mapped to this door bell. NIC may write this location + * again with a new completion. + */ + #define CMPL_DOORBELL_IDX_MASK UINT32_C(0xffffff) + #define CMPL_DOORBELL_IDX_SFT 0 + /* reserved is 2 b */ + #define CMPL_DOORBELL_RESERVED_MASK UINT32_C(0x3000000) + #define CMPL_DOORBELL_RESERVED_SFT 24 + /* + * This indicates if the BDIDX value is valid for this update when it is + * '1'. When it is '0', the BDIDX value should be ignored. + */ + #define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000) + /* + * This bit indicates the new interrupt mask state for the interrupt + * associated with the BDIDX. A '1', means the interrupt is to be + * masked. A '0' indicates the interrupt is to be unmasked. + */ + #define CMPL_DOORBELL_MASK UINT32_C(0x8000000) + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '2' for CMP door bell operations. + */ + #define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000) + #define CMPL_DOORBELL_KEY_SFT 28 + /* Completion Operation */ + #define CMPL_DOORBELL_KEY_CMPL (UINT32_C(0x2) << 28) +} __attribute__((packed)); + +/* Status Door Bell Format (4 bytes) */ + +struct status_doorbell { + uint32_t key_idx; + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '3' for Status door bell operations. + */ + /* + * BD Index of the status record for which space is now available to the + * NIC. + */ + /* + * While there is no actual BD associated with the index, the similar + * scheme is being used to communicate to the NIC that space is + * available for status completions. + */ + #define STATUS_DOORBELL_IDX_MASK UINT32_C(0xffffff) + #define STATUS_DOORBELL_IDX_SFT 0 + /* reserved is 4 b */ + #define STATUS_DOORBELL_RESERVED_MASK UINT32_C(0xf000000) + #define STATUS_DOORBELL_RESERVED_SFT 24 + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is '3' for Status door bell operations. + */ + #define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000) + #define STATUS_DOORBELL_KEY_SFT 28 + /* Status Operation */ + #define STATUS_DOORBELL_KEY_STAT (UINT32_C(0x3) << 28) +} __attribute__((packed)); + +/* Push w/32B BD Door Bell Format (32 bytes) */ + +struct push32_doorbell { + uint32_t key_sz_idx; + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is 4 for push door bell operations. + */ + /* + * This is the BD Index of last BD of the push packet that will be used + * to transmit data on the TX ring mapped to this door bell. + */ + #define PUSH32_DOORBELL_IDX_MASK UINT32_C(0xffffff) + #define PUSH32_DOORBELL_IDX_SFT 0 + /* + * This is the number of 16B BDs spaces consumed in the TX Ring by the + * "backup" version of the packet being pushed. A value of 1 is invalid + * since backup must start with a long 32B BE. A value of 2 indicates + * just the first 32B BE. A value of 3 indicates 32B+16B BD. etc. A + * value of 0 indicates 16x16B BD spaces are consumed. + */ + #define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000) + #define PUSH32_DOORBELL_SZ_SFT 24 + /* + * This value indicates the type of door bell operation that is begin + * requested. This value is 4 for push door bell operations. + */ + #define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000) + #define PUSH32_DOORBELL_KEY_SFT 28 + /* Push Operation */ + #define PUSH32_DOORBELL_KEY_PUSH (UINT32_C(0x4) << 28) + uint16_t flags_type; + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + /* This value identifies the type of buffer descriptor. */ + #define PUSH32_DOORBELL_TYPE_MASK UINT32_C(0x3f) + #define PUSH32_DOORBELL_TYPE_SFT 0 + /* + * Indicates that this BD is 32B long and is used for normal L2 + * packet transmission. + */ + #define PUSH32_DOORBELL_TYPE_TX_BD_LONG UINT32_C(0x10) + /* + * If set to 1, the packet ends with the data in the buffer pointed to + * by this descriptor. This flag must be valid on every BD. This bit + * must be set on all push doorbells. + */ + #define PUSH32_DOORBELL_FLAGS_PACKET_END UINT32_C(0x40) + /* + * If set to 1, the device will not generate a completion for this + * transmit packet unless there is an error in it's processing. If this + * bit is set to 0, then the packet will be completed normally. This bit + * must be valid only on the first BD of a packet. + */ + #define PUSH32_DOORBELL_FLAGS_NO_CMPL UINT32_C(0x80) + /* + * This value must match the sz field in the first 32b of the push + * operation except that if 16x16B BD locations are consumed in the ring + * by this packet, then this value must be 16 (not zero). + */ + #define PUSH32_DOORBELL_FLAGS_BD_CNT_MASK UINT32_C(0x1f00) + #define PUSH32_DOORBELL_FLAGS_BD_CNT_SFT 8 + /* + * This value is a hint for the length of the entire packet. It is used + * by the chip to optimize internal processing. The packet will be + * dropped if the hint is too short. This field is valid only on the + * first BD of a packet. + */ + #define PUSH32_DOORBELL_FLAGS_LHINT_MASK UINT32_C(0x6000) + #define PUSH32_DOORBELL_FLAGS_LHINT_SFT 13 + /* indicates packet length < 512B */ + #define PUSH32_DOORBELL_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13) + /* indicates 512 <= packet length < 1KB */ + #define PUSH32_DOORBELL_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13) + /* indicates 1KB <= packet length < 2KB */ + #define PUSH32_DOORBELL_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13) + /* indicates packet length >= 2KB */ + #define PUSH32_DOORBELL_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13) + #define PUSH32_DOORBELL_FLAGS_LHINT_LAST PUSH32_DOORBELL_FLAGS_LHINT_GTE2K + /* + * If set to 1, the device immediately updates the Send Consumer Index + * after the buffer associated with this descriptor has been transferred + * via DMA to NIC memory from host memory. An interrupt may or may not + * be generated according to the state of the interrupt avoidance + * mechanisms. If this bit is set to 0, then the Consumer Index is only + * updated as soon as one of the host interrupt coalescing conditions + * has been met. This bit must be valid on the first BD of a packet. + */ + #define PUSH32_DOORBELL_FLAGS_COAL_NOW UINT32_C(0x8000) + /* + * All bits in this field must be valid on the first BD of a packet. + * Only the packet_end bit must be valid for the remaining BDs of a + * packet. + */ + #define PUSH32_DOORBELL_FLAGS_MASK UINT32_C(0xffc0) + #define PUSH32_DOORBELL_FLAGS_SFT 6 + uint16_t len; + /* + * This is the length of the host physical buffer this BD describes in + * bytes. This field must be valid on all BDs of a packet. + */ + uint32_t opaque; + /* + * The opaque data field is pass through to the completion and can be + * used for any data that the driver wants to associate with the + * transmit BD. This field must be valid on the first BD of a packet. + */ + uint16_t lflags; + /* + * All bits in this field must be valid on the first BD of a packet. + * Their value on other BDs of the packet will be ignored. + */ + /* + * If set to 1, the controller replaces the TCP/UPD checksum fields of + * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the + * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP + * checksum for the packet associated with this descriptor. The flag is + * ignored if the LSO flag is set. This bit must be valid on the first + * BD of a packet. + */ + #define PUSH32_DOORBELL_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1) + /* + * If set to 1, the controller replaces the IP checksum of the normal + * packets, or the inner IP checksum of the encapsulated packets with + * the hardware calculated IP checksum for the packet associated with + * this descriptor. This bit must be valid on the first BD of a packet. + */ + #define PUSH32_DOORBELL_LFLAGS_IP_CHKSUM UINT32_C(0x2) + /* + * If set to 1, the controller will not append an Ethernet CRC to the + * end of the frame. This bit must be valid on the first BD of a packet. + * Packet must be 64B or longer when this flag is set. It is not useful + * to use this bit with any form of TX offload such as CSO or LSO. The + * intent is that the packet from the host already has a valid Ethernet + * CRC on the packet. + */ + #define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4) + /* + * If set to 1, the device will record the time at which the packet was + * actually transmitted at the TX MAC. This bit must be valid on the + * first BD of a packet. + */ + #define PUSH32_DOORBELL_LFLAGS_STAMP UINT32_C(0x8) + /* + * If set to 1, The controller replaces the tunnel IP checksum field + * with hardware calculated IP checksum for the IP header of the packet + * associated with this descriptor. For outer UDP checksum, global outer + * UDP checksum TE_NIC register needs to be enabled. If the global outer + * UDP checksum TE_NIC register bit is set, outer UDP checksum will be + * calculated for the following cases: 1. Packets with tcp_udp_chksum + * flag set to offload checksum for inner packet AND the inner packet is + * TCP/UDP. If the inner packet is ICMP for example (non-TCP/UDP), even + * if the tcp_udp_chksum is set, the outer UDP checksum will not be + * calculated. 2. Packets with lso flag set which implies inner TCP + * checksum calculation as part of LSO operation. + */ + #define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10) + /* + * If set to 1, the device will treat this packet with LSO(Large Send + * Offload) processing for both normal or encapsulated packets, which is + * a form of TCP segmentation. When this bit is 1, the hdr_size and mss + * fields must be valid. The driver doesn't need to set t_ip_chksum, + * ip_chksum, and tcp_udp_chksum flags since the controller will replace + * the appropriate checksum fields for segmented packets. When this bit + * is 1, the hdr_size and mss fields must be valid. + */ + #define PUSH32_DOORBELL_LFLAGS_LSO UINT32_C(0x20) + /* + * If set to zero when LSO is '1', then the IPID will be treated as a + * 16b number and will be wrapped if it exceeds a value of 0xffff. If + * set to one when LSO is '1', then the IPID will be treated as a 15b + * number and will be wrapped if it exceeds a value 0f 0x7fff. + */ + #define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40) + /* + * If set to zero when LSO is '1', then the IPID of the tunnel IP header + * will not be modified during LSO operations. If set to one when LSO is + * '1', then the IPID of the tunnel IP header will be incremented for + * each subsequent segment of an LSO operation. The flag is ignored if + * the LSO packet is a normal (non-tunneled) TCP packet. + */ + #define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80) + /* + * If set to '1', then the RoCE ICRC will be appended to the packet. + * Packet must be a valid RoCE format packet. + */ + #define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100) + /* + * If set to '1', then the FCoE CRC will be appended to the packet. + * Packet must be a valid FCoE format packet. + */ + #define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200) + uint16_t hdr_size; + /* + * When LSO is '1', this field must contain the offset of the TCP + * payload from the beginning of the packet in as 16b words. In case of + * encapsulated/tunneling packet, this field contains the offset of the + * inner TCP payload from beginning of the packet as 16-bit words. This + * value must be valid on the first BD of a packet. + */ + #define PUSH32_DOORBELL_HDR_SIZE_MASK UINT32_C(0x1ff) + #define PUSH32_DOORBELL_HDR_SIZE_SFT 0 + uint32_t mss; + /* + * This is the MSS value that will be used to do the LSO processing. The + * value is the length in bytes of the TCP payload for each segment + * generated by the LSO operation. This value must be valid on the first + * BD of a packet. + */ + #define PUSH32_DOORBELL_MSS_MASK UINT32_C(0x7fff) + #define PUSH32_DOORBELL_MSS_SFT 0 + uint16_t unused_2; + uint16_t cfa_action; + /* + * This value selects a CFA action to perform on the packet. Set this + * value to zero if no CFA action is desired. This value must be valid + * on the first BD of a packet. + */ + uint32_t cfa_meta; + /* + * This value is action meta-data that defines CFA edit operations that + * are done in addition to any action editing. + */ + /* When key=1, This is the VLAN tag VID value. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_VID_MASK UINT32_C(0xfff) + #define PUSH32_DOORBELL_CFA_META_VLAN_VID_SFT 0 + /* When key=1, This is the VLAN tag DE value. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_DE UINT32_C(0x1000) + /* When key=1, This is the VLAN tag PRI value. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000) + #define PUSH32_DOORBELL_CFA_META_VLAN_PRI_SFT 13 + /* When key=1, This is the VLAN tag TPID select value. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000) + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_SFT 16 + /* 0x88a8 */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16) + /* 0x8100 */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16) + /* 0x9100 */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16) + /* 0x9200 */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16) + /* 0x9300 */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16) + /* Value programmed in CFA VLANTPID register. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16) + #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_LAST PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG + /* When key=1, This is the VLAN tag TPID select value. */ + #define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000) + #define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_SFT 19 + /* + * This field identifies the type of edit to be performed on the packet. + * This value must be valid on the first BD of a packet. + */ + #define PUSH32_DOORBELL_CFA_META_KEY_MASK UINT32_C(0xf0000000) + #define PUSH32_DOORBELL_CFA_META_KEY_SFT 28 + /* No editing */ + #define PUSH32_DOORBELL_CFA_META_KEY_NONE (UINT32_C(0x0) << 28) + /* + * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12] + * - PRI/DE value. - meta[11:0] - VID value. + */ + #define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28) + #define PUSH32_DOORBELL_CFA_META_KEY_LAST PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG + uint32_t data[25]; + /* + * This is the data for the push packet. If the packet data does not fit + * in the first pass, data writing can continue at offset 4 of the + * doorbell for up to 4 additional passes for a total data size of 512B + * maximum. + */ +} __attribute__((packed)); + +/* HW Resource Manager Specification 1.4.0 */ +#define HWRM_VERSION_MAJOR 1 +#define HWRM_VERSION_MINOR 4 +#define HWRM_VERSION_UPDATE 0 + +#define HWRM_VERSION_STR "1.4.0" +/* + * Following is the signature for HWRM message field that indicates not + * applicable (All F's). Need to cast it the size of the field if needed. + */ +#define HWRM_NA_SIGNATURE ((uint32_t)(-1)) +#define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ +#define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ +#define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ +#define HW_HASH_KEY_SIZE 40 +#define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ +/* + * Description: Port Rx Statistics Formats. The HWRM shall return any + * unsupported counter with a value of 0xFFFFFFFF for 32-bit counters and + * 0xFFFFFFFFFFFFFFFF for 64-bit counters. + */ +/* + * Note: The Hardware Resource Manager (HWRM) manages various hardware resources + * inside the chip. The HWRM is implemented in firmware, and runs on embedded + * processors inside the chip. This firmware service is vital part of the chip. + * The chip can not be used by a driver or HWRM client without the HWRM. + */ +/* Input (16 bytes) */ + +struct input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (8 bytes) */ + +struct output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ +} __attribute__((packed)); + +#define GET_HWRM_REQ_TYPE(x) \ + ((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \ + ((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \ + ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \ + ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \ + ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \ + ((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \ + ((x) == 0x94 ? "RESERVED3": \ + ((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \ + ((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \ + ((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \ + ((x) == 0x10 ? "RESERVED1": \ + ((x) == 0x11 ? "HWRM_FUNC_RESET": \ + ((x) == 0x12 ? "HWRM_FUNC_GETFID": \ + ((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \ + ((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \ + ((x) == 0x15 ? "HWRM_FUNC_QCAPS": \ + ((x) == 0x16 ? "HWRM_FUNC_QCFG": \ + ((x) == 0x17 ? "HWRM_FUNC_CFG": \ + ((x) == 0x18 ? "HWRM_FUNC_QSTATS": \ + ((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \ + ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \ + ((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \ + ((x) == 0xd2 ? "HWRM_FWD_RESP": \ + ((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \ + ((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \ + ((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \ + ((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \ + ((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \ + ((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \ + ((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \ + ((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \ + ((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \ + ((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \ + ((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \ + ((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \ + ((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \ + ((x) == 0xc8 ? "HWRM_FW_SET_TIME": \ + ((x) == 0xc9 ? "HWRM_FW_GET_TIME": \ + ((x) == 0xc0 ? "HWRM_FW_RESET": \ + ((x) == 0xc1 ? "HWRM_FW_QSTATUS": \ + ((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \ + ((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \ + ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \ + ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \ + ((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \ + ((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \ + ((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \ + ((x) == 0x61 ? "HWRM_RING_GRP_FREE": \ + ((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \ + ((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \ + ((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \ + ((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \ + ((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \ + ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \ + ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \ + ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \ + ((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \ + ((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \ + ((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \ + ((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \ + ((x) == 0xf ? "HWRM_FUNC_VF_CFG": \ + ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \ + ((x) == 0xfffe ? "HWRM_NVM_WRITE": \ + ((x) == 0xfffd ? "HWRM_NVM_READ": \ + ((x) == 0x50 ? "HWRM_RING_ALLOC": \ + ((x) == 0x51 ? "HWRM_RING_FREE": \ + ((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \ + ((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \ + ((x) == 0x4a ? "HWRM_VNIC_QCAPS": \ + ((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \ + ((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \ + ((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \ + ((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \ + ((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \ + ((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \ + ((x) == 0x43 ? "HWRM_VNIC_QCFG": \ + ((x) == 0x42 ? "HWRM_VNIC_CFG": \ + ((x) == 0x41 ? "HWRM_VNIC_FREE": \ + ((x) == 0x40 ? "HWRM_VNIC_ALLOC": \ + ((x) == 0x0 ? "HWRM_VER_GET": \ + ((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \ + ((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \ + ((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \ + ((x) == 0x5e ? "HWRM_RING_RESET": \ + ((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \ + ((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \ + ((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \ + ((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \ + ((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \ + ((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \ + ((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \ + ((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \ + ((x) == 0x32 ? "HWRM_QUEUE_CFG": \ + ((x) == 0x33 ? "HWRM_QUEUE_BUFFERS_QCFG": \ + ((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \ + ((x) == 0x31 ? "HWRM_QUEUE_QCFG": \ + ((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \ + ((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \ + ((x) == 0x34 ? "HWRM_QUEUE_BUFFERS_CFG": \ + ((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \ + ((x) == 0xff14 ? "HWRM_DBG_DUMP": \ + ((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \ + ((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \ + ((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \ + ((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \ + ((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \ + ((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \ + ((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \ + ((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \ + ((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \ + ((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \ + ((x) == 0x23 ? "HWRM_PORT_QSTATS": \ + ((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \ + ((x) == 0x29 ? "HWRM_PORT_BLINK_LED": \ + ((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \ + ((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \ + "Unknown req_type")))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) + +/* Command numbering (8 bytes) */ + +struct cmd_nums { + uint16_t req_type; + /* + * This version of the specification defines the commands listed in the + * table below. The following are general implementation requirements + * for these commands: # All commands listed below that are marked + * neither reserved nor experimental shall be implemented by the HWRM. # + * A HWRM client compliant to this specification should not use commands + * outside of the list below. # A HWRM client compliant to this + * specification should not use command numbers marked reserved below. # + * A command marked experimental below may not be implemented by the + * HWRM. # A command marked experimental may change in the future + * version of the HWRM specification. # A command not listed below may + * be implemented by the HWRM. The behavior of commands that are not + * listed below is outside the scope of this specification. + */ + #define HWRM_VER_GET (UINT32_C(0x0)) + #define HWRM_FUNC_BUF_UNRGTR (UINT32_C(0xe)) + /* Experimental */ + #define HWRM_FUNC_VF_CFG (UINT32_C(0xf)) + /* Reserved for future use */ + #define RESERVED1 (UINT32_C(0x10)) + #define HWRM_FUNC_RESET (UINT32_C(0x11)) + #define HWRM_FUNC_GETFID (UINT32_C(0x12)) + #define HWRM_FUNC_VF_ALLOC (UINT32_C(0x13)) + #define HWRM_FUNC_VF_FREE (UINT32_C(0x14)) + #define HWRM_FUNC_QCAPS (UINT32_C(0x15)) + #define HWRM_FUNC_QCFG (UINT32_C(0x16)) + #define HWRM_FUNC_CFG (UINT32_C(0x17)) + #define HWRM_FUNC_QSTATS (UINT32_C(0x18)) + #define HWRM_FUNC_CLR_STATS (UINT32_C(0x19)) + #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a)) + #define HWRM_FUNC_VF_RESC_FREE (UINT32_C(0x1b)) + #define HWRM_FUNC_VF_VNIC_IDS_QUERY (UINT32_C(0x1c)) + #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d)) + #define HWRM_FUNC_DRV_QVER (UINT32_C(0x1e)) + #define HWRM_FUNC_BUF_RGTR (UINT32_C(0x1f)) + #define HWRM_PORT_PHY_CFG (UINT32_C(0x20)) + #define HWRM_PORT_MAC_CFG (UINT32_C(0x21)) + /* Experimental */ + #define HWRM_PORT_TS_QUERY (UINT32_C(0x22)) + #define HWRM_PORT_QSTATS (UINT32_C(0x23)) + #define HWRM_PORT_LPBK_QSTATS (UINT32_C(0x24)) + /* Experimental */ + #define HWRM_PORT_CLR_STATS (UINT32_C(0x25)) + /* Experimental */ + #define HWRM_PORT_LPBK_CLR_STATS (UINT32_C(0x26)) + #define HWRM_PORT_PHY_QCFG (UINT32_C(0x27)) + /* Experimental */ + #define HWRM_PORT_MAC_QCFG (UINT32_C(0x28)) + /* Experimental */ + #define HWRM_PORT_BLINK_LED (UINT32_C(0x29)) + /* Experimental */ + #define HWRM_PORT_PHY_QCAPS (UINT32_C(0x2a)) + /* Experimental */ + #define HWRM_PORT_PHY_I2C_WRITE (UINT32_C(0x2b)) + /* Experimental */ + #define HWRM_PORT_PHY_I2C_READ (UINT32_C(0x2c)) + #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30)) + #define HWRM_QUEUE_QCFG (UINT32_C(0x31)) + #define HWRM_QUEUE_CFG (UINT32_C(0x32)) + #define HWRM_QUEUE_BUFFERS_QCFG (UINT32_C(0x33)) + #define HWRM_QUEUE_BUFFERS_CFG (UINT32_C(0x34)) + /* Experimental */ + #define HWRM_QUEUE_PFCENABLE_QCFG (UINT32_C(0x35)) + /* Experimental */ + #define HWRM_QUEUE_PFCENABLE_CFG (UINT32_C(0x36)) + /* Experimental */ + #define HWRM_QUEUE_PRI2COS_QCFG (UINT32_C(0x37)) + /* Experimental */ + #define HWRM_QUEUE_PRI2COS_CFG (UINT32_C(0x38)) + /* Experimental */ + #define HWRM_QUEUE_COS2BW_QCFG (UINT32_C(0x39)) + /* Experimental */ + #define HWRM_QUEUE_COS2BW_CFG (UINT32_C(0x3a)) + #define HWRM_VNIC_ALLOC (UINT32_C(0x40)) + #define HWRM_VNIC_FREE (UINT32_C(0x41)) + #define HWRM_VNIC_CFG (UINT32_C(0x42)) + /* Experimental */ + #define HWRM_VNIC_QCFG (UINT32_C(0x43)) + #define HWRM_VNIC_TPA_CFG (UINT32_C(0x44)) + /* Experimental */ + #define HWRM_VNIC_TPA_QCFG (UINT32_C(0x45)) + #define HWRM_VNIC_RSS_CFG (UINT32_C(0x46)) + #define HWRM_VNIC_RSS_QCFG (UINT32_C(0x47)) + #define HWRM_VNIC_PLCMODES_CFG (UINT32_C(0x48)) + #define HWRM_VNIC_PLCMODES_QCFG (UINT32_C(0x49)) + /* Experimental */ + #define HWRM_VNIC_QCAPS (UINT32_C(0x4a)) + #define HWRM_RING_ALLOC (UINT32_C(0x50)) + #define HWRM_RING_FREE (UINT32_C(0x51)) + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (UINT32_C(0x52)) + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (UINT32_C(0x53)) + #define HWRM_RING_RESET (UINT32_C(0x5e)) + #define HWRM_RING_GRP_ALLOC (UINT32_C(0x60)) + #define HWRM_RING_GRP_FREE (UINT32_C(0x61)) + #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70)) + #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71)) + #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90)) + #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91)) + #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92)) + #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93)) + /* Reserved for future use */ + #define RESERVED3 (UINT32_C(0x94)) + #define HWRM_CFA_TUNNEL_FILTER_ALLOC (UINT32_C(0x95)) + #define HWRM_CFA_TUNNEL_FILTER_FREE (UINT32_C(0x96)) + /* Experimental */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC (UINT32_C(0x97)) + /* Experimental */ + #define HWRM_CFA_ENCAP_RECORD_FREE (UINT32_C(0x98)) + #define HWRM_CFA_NTUPLE_FILTER_ALLOC (UINT32_C(0x99)) + #define HWRM_CFA_NTUPLE_FILTER_FREE (UINT32_C(0x9a)) + #define HWRM_CFA_NTUPLE_FILTER_CFG (UINT32_C(0x9b)) + /* Experimental */ + #define HWRM_CFA_EM_FLOW_ALLOC (UINT32_C(0x9c)) + /* Experimental */ + #define HWRM_CFA_EM_FLOW_FREE (UINT32_C(0x9d)) + /* Experimental */ + #define HWRM_CFA_EM_FLOW_CFG (UINT32_C(0x9e)) + #define HWRM_TUNNEL_DST_PORT_QUERY (UINT32_C(0xa0)) + #define HWRM_TUNNEL_DST_PORT_ALLOC (UINT32_C(0xa1)) + #define HWRM_TUNNEL_DST_PORT_FREE (UINT32_C(0xa2)) + #define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0)) + #define HWRM_STAT_CTX_FREE (UINT32_C(0xb1)) + #define HWRM_STAT_CTX_QUERY (UINT32_C(0xb2)) + #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3)) + #define HWRM_FW_RESET (UINT32_C(0xc0)) + #define HWRM_FW_QSTATUS (UINT32_C(0xc1)) + /* Experimental */ + #define HWRM_FW_SET_TIME (UINT32_C(0xc8)) + /* Experimental */ + #define HWRM_FW_GET_TIME (UINT32_C(0xc9)) + #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0)) + #define HWRM_REJECT_FWD_RESP (UINT32_C(0xd1)) + #define HWRM_FWD_RESP (UINT32_C(0xd2)) + #define HWRM_FWD_ASYNC_EVENT_CMPL (UINT32_C(0xd3)) + #define HWRM_TEMP_MONITOR_QUERY (UINT32_C(0xe0)) + /* Experimental */ + #define HWRM_WOL_FILTER_ALLOC (UINT32_C(0xf0)) + /* Experimental */ + #define HWRM_WOL_FILTER_FREE (UINT32_C(0xf1)) + /* Experimental */ + #define HWRM_WOL_FILTER_QCFG (UINT32_C(0xf2)) + /* Experimental */ + #define HWRM_WOL_REASON_QCFG (UINT32_C(0xf3)) + /* Experimental */ + #define HWRM_DBG_READ_DIRECT (UINT32_C(0xff10)) + /* Experimental */ + #define HWRM_DBG_READ_INDIRECT (UINT32_C(0xff11)) + /* Experimental */ + #define HWRM_DBG_WRITE_DIRECT (UINT32_C(0xff12)) + /* Experimental */ + #define HWRM_DBG_WRITE_INDIRECT (UINT32_C(0xff13)) + #define HWRM_DBG_DUMP (UINT32_C(0xff14)) + #define HWRM_NVM_INSTALL_UPDATE (UINT32_C(0xfff3)) + #define HWRM_NVM_MODIFY (UINT32_C(0xfff4)) + #define HWRM_NVM_VERIFY_UPDATE (UINT32_C(0xfff5)) + #define HWRM_NVM_GET_DEV_INFO (UINT32_C(0xfff6)) + #define HWRM_NVM_ERASE_DIR_ENTRY (UINT32_C(0xfff7)) + #define HWRM_NVM_MOD_DIR_ENTRY (UINT32_C(0xfff8)) + #define HWRM_NVM_FIND_DIR_ENTRY (UINT32_C(0xfff9)) + #define HWRM_NVM_GET_DIR_ENTRIES (UINT32_C(0xfffa)) + #define HWRM_NVM_GET_DIR_INFO (UINT32_C(0xfffb)) + #define HWRM_NVM_RAW_DUMP (UINT32_C(0xfffc)) + #define HWRM_NVM_READ (UINT32_C(0xfffd)) + #define HWRM_NVM_WRITE (UINT32_C(0xfffe)) + #define HWRM_NVM_RAW_WRITE_BLK (UINT32_C(0xffff)) + uint16_t unused_0[3]; +} __attribute__((packed)); + +#define GET_HWRM_ERROR_CODE(x) \ + ((x) == 0xf ? "HWRM_ERROR": \ + ((x) == 0xffff ? "CMD_NOT_SUPPORTED": \ + ((x) == 0xfffe ? "UNKNOWN_ERR": \ + ((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \ + ((x) == 0x5 ? "INVALID_FLAGS": \ + ((x) == 0x6 ? "INVALID_ENABLES": \ + ((x) == 0x0 ? "SUCCESS": \ + ((x) == 0x1 ? "FAIL": \ + ((x) == 0x2 ? "INVALID_PARAMS": \ + ((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \ + "Unknown error_code")))))))))) + +/* Return Codes (8 bytes) */ + +struct ret_codes { + uint16_t error_code; + /* These are numbers assigned to return/error codes. */ + /* Request was successfully executed by the HWRM. */ + #define HWRM_ERR_CODE_SUCCESS (UINT32_C(0x0)) + /* THe HWRM failed to execute the request. */ + #define HWRM_ERR_CODE_FAIL (UINT32_C(0x1)) + /* The request contains invalid argument(s) or input parameters. */ + #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2)) + /* + * The requester is not allowed to access the requested + * resource. This error code shall be provided in a response to + * a request to query or modify an existing resource that is not + * accessible by the requester. + */ + #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3)) + /* + * The HWRM is unable to allocate the requested resource. This + * code only applies to requests for HWRM resource allocations. + */ + #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (UINT32_C(0x4)) + /* Invalid combination of flags is specified in the request. */ + #define HWRM_ERR_CODE_INVALID_FLAGS (UINT32_C(0x5)) + /* + * Invalid combination of enables fields is specified in the + * request. + */ + #define HWRM_ERR_CODE_INVALID_ENABLES (UINT32_C(0x6)) + /* Generic HWRM execution error that represents an internal error. */ + #define HWRM_ERR_CODE_HWRM_ERROR (UINT32_C(0xf)) + /* Unknown error */ + #define HWRM_ERR_CODE_UNKNOWN_ERR (UINT32_C(0xfffe)) + /* Unsupported or invalid command */ + #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (UINT32_C(0xffff)) + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_err_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t opaque_0; + /* debug info for this error response. */ + uint16_t opaque_1; + /* debug info for this error response. */ + uint8_t cmd_err; + /* + * In the case of an error response, command specific error code is + * returned in this field. + */ + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* Port Tx Statistics Formats (408 bytes) */ + +struct tx_port_stats { + uint64_t tx_64b_frames; + /* Total Number of 64 Bytes frames transmitted */ + uint64_t tx_65b_127b_frames; + /* Total Number of 65-127 Bytes frames transmitted */ + uint64_t tx_128b_255b_frames; + /* Total Number of 128-255 Bytes frames transmitted */ + uint64_t tx_256b_511b_frames; + /* Total Number of 256-511 Bytes frames transmitted */ + uint64_t tx_512b_1023b_frames; + /* Total Number of 512-1023 Bytes frames transmitted */ + uint64_t tx_1024b_1518_frames; + /* Total Number of 1024-1518 Bytes frames transmitted */ + uint64_t tx_good_vlan_frames; + /* + * Total Number of each good VLAN (exludes FCS errors) frame transmitted + * which is 1519 to 1522 bytes in length inclusive (excluding framing + * bits but including FCS bytes). + */ + uint64_t tx_1519b_2047_frames; + /* Total Number of 1519-2047 Bytes frames transmitted */ + uint64_t tx_2048b_4095b_frames; + /* Total Number of 2048-4095 Bytes frames transmitted */ + uint64_t tx_4096b_9216b_frames; + /* Total Number of 4096-9216 Bytes frames transmitted */ + uint64_t tx_9217b_16383b_frames; + /* Total Number of 9217-16383 Bytes frames transmitted */ + uint64_t tx_good_frames; + /* Total Number of good frames transmitted */ + uint64_t tx_total_frames; + /* Total Number of frames transmitted */ + uint64_t tx_ucast_frames; + /* Total number of unicast frames transmitted */ + uint64_t tx_mcast_frames; + /* Total number of multicast frames transmitted */ + uint64_t tx_bcast_frames; + /* Total number of broadcast frames transmitted */ + uint64_t tx_pause_frames; + /* Total number of PAUSE control frames transmitted */ + uint64_t tx_pfc_frames; + /* Total number of PFC/per-priority PAUSE control frames transmitted */ + uint64_t tx_jabber_frames; + /* Total number of jabber frames transmitted */ + uint64_t tx_fcs_err_frames; + /* Total number of frames transmitted with FCS error */ + uint64_t tx_control_frames; + /* Total number of control frames transmitted */ + uint64_t tx_oversz_frames; + /* Total number of over-sized frames transmitted */ + uint64_t tx_single_dfrl_frames; + /* Total number of frames with single deferral */ + uint64_t tx_multi_dfrl_frames; + /* Total number of frames with multiple deferrals */ + uint64_t tx_single_coll_frames; + /* Total number of frames with single collision */ + uint64_t tx_multi_coll_frames; + /* Total number of frames with multiple collisions */ + uint64_t tx_late_coll_frames; + /* Total number of frames with late collisions */ + uint64_t tx_excessive_coll_frames; + /* Total number of frames with excessive collisions */ + uint64_t tx_frag_frames; + /* Total number of fragmented frames transmitted */ + uint64_t tx_err; + /* Total number of transmit errors */ + uint64_t tx_tagged_frames; + /* Total number of single VLAN tagged frames transmitted */ + uint64_t tx_dbl_tagged_frames; + /* Total number of double VLAN tagged frames transmitted */ + uint64_t tx_runt_frames; + /* Total number of runt frames transmitted */ + uint64_t tx_fifo_underruns; + /* Total number of TX FIFO under runs */ + uint64_t tx_pfc_ena_frames_pri0; + /* Total number of PFC frames with PFC enabled bit for Pri 0 transmitted */ + uint64_t tx_pfc_ena_frames_pri1; + /* Total number of PFC frames with PFC enabled bit for Pri 1 transmitted */ + uint64_t tx_pfc_ena_frames_pri2; + /* Total number of PFC frames with PFC enabled bit for Pri 2 transmitted */ + uint64_t tx_pfc_ena_frames_pri3; + /* Total number of PFC frames with PFC enabled bit for Pri 3 transmitted */ + uint64_t tx_pfc_ena_frames_pri4; + /* Total number of PFC frames with PFC enabled bit for Pri 4 transmitted */ + uint64_t tx_pfc_ena_frames_pri5; + /* Total number of PFC frames with PFC enabled bit for Pri 5 transmitted */ + uint64_t tx_pfc_ena_frames_pri6; + /* Total number of PFC frames with PFC enabled bit for Pri 6 transmitted */ + uint64_t tx_pfc_ena_frames_pri7; + /* Total number of PFC frames with PFC enabled bit for Pri 7 transmitted */ + uint64_t tx_eee_lpi_events; + /* Total number of EEE LPI Events on TX */ + uint64_t tx_eee_lpi_duration; + /* EEE LPI Duration Counter on TX */ + uint64_t tx_llfc_logical_msgs; + /* Total number of Link Level Flow Control (LLFC) messages transmitted */ + uint64_t tx_hcfc_msgs; + /* Total number of HCFC messages transmitted */ + uint64_t tx_total_collisions; + /* Total number of TX collisions */ + uint64_t tx_bytes; + /* Total number of transmitted bytes */ + uint64_t tx_xthol_frames; + /* Total number of end-to-end HOL frames */ + uint64_t tx_stat_discard; + /* Total Tx Drops per Port reported by STATS block */ + uint64_t tx_stat_error; + /* Total Tx Error Drops per Port reported by STATS block */ +} __attribute__((packed)); + +/* Port Rx Statistics Formats (528 bytes) */ + +struct rx_port_stats { + uint64_t rx_64b_frames; + /* Total Number of 64 Bytes frames received */ + uint64_t rx_65b_127b_frames; + /* Total Number of 65-127 Bytes frames received */ + uint64_t rx_128b_255b_frames; + /* Total Number of 128-255 Bytes frames received */ + uint64_t rx_256b_511b_frames; + /* Total Number of 256-511 Bytes frames received */ + uint64_t rx_512b_1023b_frames; + /* Total Number of 512-1023 Bytes frames received */ + uint64_t rx_1024b_1518_frames; + /* Total Number of 1024-1518 Bytes frames received */ + uint64_t rx_good_vlan_frames; + /* + * Total Number of each good VLAN (exludes FCS errors) frame received + * which is 1519 to 1522 bytes in length inclusive (excluding framing + * bits but including FCS bytes). + */ + uint64_t rx_1519b_2047b_frames; + /* Total Number of 1519-2047 Bytes frames received */ + uint64_t rx_2048b_4095b_frames; + /* Total Number of 2048-4095 Bytes frames received */ + uint64_t rx_4096b_9216b_frames; + /* Total Number of 4096-9216 Bytes frames received */ + uint64_t rx_9217b_16383b_frames; + /* Total Number of 9217-16383 Bytes frames received */ + uint64_t rx_total_frames; + /* Total number of frames received */ + uint64_t rx_ucast_frames; + /* Total number of unicast frames received */ + uint64_t rx_mcast_frames; + /* Total number of multicast frames received */ + uint64_t rx_bcast_frames; + /* Total number of broadcast frames received */ + uint64_t rx_fcs_err_frames; + /* Total number of received frames with FCS error */ + uint64_t rx_ctrl_frames; + /* Total number of control frames received */ + uint64_t rx_pause_frames; + /* Total number of PAUSE frames received */ + uint64_t rx_pfc_frames; + /* Total number of PFC frames received */ + uint64_t rx_unsupported_opcode_frames; + /* Total number of frames received with an unsupported opcode */ + uint64_t rx_unsupported_da_pausepfc_frames; + /* + * Total number of frames received with an unsupported DA for pause and + * PFC + */ + uint64_t rx_wrong_sa_frames; + /* Total number of frames received with an unsupported SA */ + uint64_t rx_align_err_frames; + /* Total number of received packets with alignment error */ + uint64_t rx_oor_len_frames; + /* Total number of received frames with out-of-range length */ + uint64_t rx_code_err_frames; + /* Total number of received frames with error termination */ + uint64_t rx_false_carrier_frames; + /* + * Total number of received frames with a false carrier is detected + * during idle, as defined by RX_ER samples active and RXD is 0xE. The + * event is reported along with the statistics generated on the next + * received frame. Only one false carrier condition can be detected and + * logged between frames. Carrier event, valid for 10M/100M speed modes + * only. + */ + uint64_t rx_ovrsz_frames; + /* Total number of over-sized frames received */ + uint64_t rx_jbr_frames; + /* Total number of jabber packets received */ + uint64_t rx_mtu_err_frames; + /* Total number of received frames with MTU error */ + uint64_t rx_match_crc_frames; + /* Total number of received frames with CRC match */ + uint64_t rx_promiscuous_frames; + /* Total number of frames received promiscuously */ + uint64_t rx_tagged_frames; + /* Total number of received frames with one or two VLAN tags */ + uint64_t rx_double_tagged_frames; + /* Total number of received frames with two VLAN tags */ + uint64_t rx_trunc_frames; + /* Total number of truncated frames received */ + uint64_t rx_good_frames; + /* Total number of good frames (without errors) received */ + uint64_t rx_pfc_xon2xoff_frames_pri0; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 0 + */ + uint64_t rx_pfc_xon2xoff_frames_pri1; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 1 + */ + uint64_t rx_pfc_xon2xoff_frames_pri2; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 2 + */ + uint64_t rx_pfc_xon2xoff_frames_pri3; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 3 + */ + uint64_t rx_pfc_xon2xoff_frames_pri4; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 4 + */ + uint64_t rx_pfc_xon2xoff_frames_pri5; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 5 + */ + uint64_t rx_pfc_xon2xoff_frames_pri6; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 6 + */ + uint64_t rx_pfc_xon2xoff_frames_pri7; + /* + * Total number of received PFC frames with transition from XON to XOFF + * on Pri 7 + */ + uint64_t rx_pfc_ena_frames_pri0; + /* Total number of received PFC frames with PFC enabled bit for Pri 0 */ + uint64_t rx_pfc_ena_frames_pri1; + /* Total number of received PFC frames with PFC enabled bit for Pri 1 */ + uint64_t rx_pfc_ena_frames_pri2; + /* Total number of received PFC frames with PFC enabled bit for Pri 2 */ + uint64_t rx_pfc_ena_frames_pri3; + /* Total number of received PFC frames with PFC enabled bit for Pri 3 */ + uint64_t rx_pfc_ena_frames_pri4; + /* Total number of received PFC frames with PFC enabled bit for Pri 4 */ + uint64_t rx_pfc_ena_frames_pri5; + /* Total number of received PFC frames with PFC enabled bit for Pri 5 */ + uint64_t rx_pfc_ena_frames_pri6; + /* Total number of received PFC frames with PFC enabled bit for Pri 6 */ + uint64_t rx_pfc_ena_frames_pri7; + /* Total number of received PFC frames with PFC enabled bit for Pri 7 */ + uint64_t rx_sch_crc_err_frames; + /* Total Number of frames received with SCH CRC error */ + uint64_t rx_undrsz_frames; + /* Total Number of under-sized frames received */ + uint64_t rx_frag_frames; + /* Total Number of fragmented frames received */ + uint64_t rx_eee_lpi_events; + /* Total number of RX EEE LPI Events */ + uint64_t rx_eee_lpi_duration; + /* EEE LPI Duration Counter on RX */ + uint64_t rx_llfc_physical_msgs; + /* + * Total number of physical type Link Level Flow Control (LLFC) messages + * received + */ + uint64_t rx_llfc_logical_msgs; + /* + * Total number of logical type Link Level Flow Control (LLFC) messages + * received + */ + uint64_t rx_llfc_msgs_with_crc_err; + /* + * Total number of logical type Link Level Flow Control (LLFC) messages + * received with CRC error + */ + uint64_t rx_hcfc_msgs; + /* Total number of HCFC messages received */ + uint64_t rx_hcfc_msgs_with_crc_err; + /* Total number of HCFC messages received with CRC error */ + uint64_t rx_bytes; + /* Total number of received bytes */ + uint64_t rx_runt_bytes; + /* Total number of bytes received in runt frames */ + uint64_t rx_runt_frames; + /* Total number of runt frames received */ + uint64_t rx_stat_discard; + /* Total Rx Discards per Port reported by STATS block */ + uint64_t rx_stat_err; + /* Total Rx Error Drops per Port reported by STATS block */ +} __attribute__((packed)); + +/* hwrm_ver_get */ +/* + * Description: This function is called by a driver to determine the HWRM + * interface version supported by the HWRM firmware, the version of HWRM + * firmware implementation, the name of HWRM firmware, the versions of other + * embedded firmwares, and the names of other embedded firmwares, etc. Any + * interface or firmware version with major = 0, minor = 0, and update = 0 shall + * be considered an invalid version. + */ +/* Input (24 bytes) */ + +struct hwrm_ver_get_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t hwrm_intf_maj; + /* + * This field represents the major version of HWRM interface + * specification supported by the driver HWRM implementation. The + * interface major version is intended to change only when non backward + * compatible changes are made to the HWRM interface specification. + */ + uint8_t hwrm_intf_min; + /* + * This field represents the minor version of HWRM interface + * specification supported by the driver HWRM implementation. A change + * in interface minor version is used to reflect significant backward + * compatible modification to HWRM interface specification. This can be + * due to addition or removal of functionality. HWRM interface + * specifications with the same major version but different minor + * versions are compatible. + */ + uint8_t hwrm_intf_upd; + /* + * This field represents the update version of HWRM interface + * specification supported by the driver HWRM implementation. The + * interface update version is used to reflect minor changes or bug + * fixes to a released HWRM interface specification. + */ + uint8_t unused_0[5]; +} __attribute__((packed)); + +/* Output (128 bytes) */ + +struct hwrm_ver_get_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t hwrm_intf_maj; + /* + * This field represents the major version of HWRM interface + * specification supported by the HWRM implementation. The interface + * major version is intended to change only when non backward compatible + * changes are made to the HWRM interface specification. A HWRM + * implementation that is compliant with this specification shall + * provide value of 1 in this field. + */ + uint8_t hwrm_intf_min; + /* + * This field represents the minor version of HWRM interface + * specification supported by the HWRM implementation. A change in + * interface minor version is used to reflect significant backward + * compatible modification to HWRM interface specification. This can be + * due to addition or removal of functionality. HWRM interface + * specifications with the same major version but different minor + * versions are compatible. A HWRM implementation that is compliant with + * this specification shall provide value of 2 in this field. + */ + uint8_t hwrm_intf_upd; + /* + * This field represents the update version of HWRM interface + * specification supported by the HWRM implementation. The interface + * update version is used to reflect minor changes or bug fixes to a + * released HWRM interface specification. A HWRM implementation that is + * compliant with this specification shall provide value of 2 in this + * field. + */ + uint8_t hwrm_intf_rsvd; + uint8_t hwrm_fw_maj; + /* + * This field represents the major version of HWRM firmware. A change in + * firmware major version represents a major firmware release. + */ + uint8_t hwrm_fw_min; + /* + * This field represents the minor version of HWRM firmware. A change in + * firmware minor version represents significant firmware functionality + * changes. + */ + uint8_t hwrm_fw_bld; + /* + * This field represents the build version of HWRM firmware. A change in + * firmware build version represents bug fixes to a released firmware. + */ + uint8_t hwrm_fw_rsvd; + /* + * This field is a reserved field. This field can be used to represent + * firmware branches or customer specific releases tied to a specific + * (major,minor,update) version of the HWRM firmware. + */ + uint8_t mgmt_fw_maj; + /* + * This field represents the major version of mgmt firmware. A change in + * major version represents a major release. + */ + uint8_t mgmt_fw_min; + /* + * This field represents the minor version of mgmt firmware. A change in + * minor version represents significant functionality changes. + */ + uint8_t mgmt_fw_bld; + /* + * This field represents the build version of mgmt firmware. A change in + * update version represents bug fixes. + */ + uint8_t mgmt_fw_rsvd; + /* + * This field is a reserved field. This field can be used to represent + * firmware branches or customer specific releases tied to a specific + * (major,minor,update) version + */ + uint8_t netctrl_fw_maj; + /* + * This field represents the major version of network control firmware. + * A change in major version represents a major release. + */ + uint8_t netctrl_fw_min; + /* + * This field represents the minor version of network control firmware. + * A change in minor version represents significant functionality + * changes. + */ + uint8_t netctrl_fw_bld; + /* + * This field represents the build version of network control firmware. + * A change in update version represents bug fixes. + */ + uint8_t netctrl_fw_rsvd; + /* + * This field is a reserved field. This field can be used to represent + * firmware branches or customer specific releases tied to a specific + * (major,minor,update) version + */ + uint32_t reserved1; + /* + * This field is reserved for future use. The responder should set it to + * 0. The requester should ignore this field. + */ + uint8_t roce_fw_maj; + /* + * This field represents the major version of RoCE firmware. A change in + * major version represents a major release. + */ + uint8_t roce_fw_min; + /* + * This field represents the minor version of RoCE firmware. A change in + * minor version represents significant functionality changes. + */ + uint8_t roce_fw_bld; + /* + * This field represents the build version of RoCE firmware. A change in + * update version represents bug fixes. + */ + uint8_t roce_fw_rsvd; + /* + * This field is a reserved field. This field can be used to represent + * firmware branches or customer specific releases tied to a specific + * (major,minor,update) version + */ + char hwrm_fw_name[16]; + /* + * This field represents the name of HWRM FW (ASCII chars with NULL at + * the end). + */ + char mgmt_fw_name[16]; + /* + * This field represents the name of mgmt FW (ASCII chars with NULL at + * the end). + */ + char netctrl_fw_name[16]; + /* + * This field represents the name of network control firmware (ASCII + * chars with NULL at the end). + */ + uint32_t reserved2[4]; + /* + * This field is reserved for future use. The responder should set it to + * 0. The requester should ignore this field. + */ + char roce_fw_name[16]; + /* + * This field represents the name of RoCE FW (ASCII chars with NULL at + * the end). + */ + uint16_t chip_num; + /* This field returns the chip number. */ + uint8_t chip_rev; + /* This field returns the revision of chip. */ + uint8_t chip_metal; + /* This field returns the chip metal number. */ + uint8_t chip_bond_id; + /* This field returns the bond id of the chip. */ + uint8_t chip_platform_type; + /* + * This value indicates the type of platform used for chip + * implementation. + */ + /* ASIC */ + #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0) + /* FPGA platform of the chip. */ + #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1) + /* Palladium platform of the chip. */ + #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2) + uint16_t max_req_win_len; + /* + * This field returns the maximum value of request window that is + * supported by the HWRM. The request window is mapped into device + * address space using MMIO. + */ + uint16_t max_resp_len; + /* This field returns the maximum value of response buffer in bytes. */ + uint16_t def_req_timeout; + /* This field returns the default request timeout value in milliseconds. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_reset */ +/* + * Description: This command resets a hardware function (PCIe function) and + * frees any resources used by the function. This command shall be initiated by + * the driver after an FLR has occurred to prepare the function for re-use. This + * command may also be initiated by a driver prior to doing it's own + * configuration. This command puts the function into the reset state. In the + * reset state, global and port related features of the chip are not available. + */ +/* + * Note: This command will reset a function that has already been disabled or + * idled. The command returns all the resources owned by the function so a new + * driver may allocate and configure resources normally. + */ +/* Input (24 bytes) */ + +struct hwrm_func_reset_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the vf_id_valid field to be configured. */ + #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + uint16_t vf_id; + /* + * The ID of the VF that this PF is trying to reset. Only the parent PF + * shall be allowed to reset a child VF. A parent PF driver shall use + * this field only when a specific child VF is requested to be reset. + */ + uint8_t func_reset_level; + /* This value indicates the level of a function reset. */ + /* + * Reset the caller function and its children VFs (if any). If + * no children functions exist, then reset the caller function + * only. + */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL UINT32_C(0x0) + /* Reset the caller function only */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME UINT32_C(0x1) + /* + * Reset all children VFs of the caller function driver if the + * caller is a PF driver. It is an error to specify this level + * by a VF driver. It is an error to specify this level by a PF + * driver with no children VFs. + */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2) + /* + * Reset a specific VF of the caller function driver if the + * caller is the parent PF driver. It is an error to specify + * this level by a VF driver. It is an error to specify this + * level by a PF driver that is not the parent of the VF that is + * being requested to reset. + */ + #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF UINT32_C(0x3) + uint8_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_reset_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_getfid */ +/* + * Description: This command returns the FID value for the function. If a valid + * pci_id is provided, then this function returns fid for that PCI function. + * Otherwise, it returns FID of the requesting function. This value is needed to + * configure Rings and MSI-X vectors so their DMA operations appear correctly on + * the PCI bus. For PF-HWRM commands, there is no need for FID. Similarly there + * is no need for FID for VF-HWRM commands. In the PF-VF communication, only PF + * needs to know FIDs. + */ +/* Input (24 bytes) */ + +struct hwrm_func_getfid_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the pci_id field to be configured. */ + #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1) + uint16_t pci_id; + /* + * This value is the PCI ID of the queried function. If ARI is enabled, + * then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus + * Number (8b):Device Number (4b):Function Number(4b). + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_getfid_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t fid; + /* + * FID value. This value is used to identify operations on the PCI bus + * as belonging to a particular PCI function. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_vf_alloc */ +/* + * Description: This command is used to allocate requested number of virtual + * functions on a physical function. It will return the FID value of the first + * virtual function. The FIDs of the remaining virtual functions can be derived + * by sequentially incrementing the FID value of the first VF. This command + * supports the following models for VF allocation: # Allocation of one or more + * VFs from a PF without specifying the first VF ID # Allocation of multiple VFs + * from a PF starting with a specific VF # Allocation of a specific VF from a PF + * If this command is called on a virtual function or a physical function that + * is not enabled for SR-IOV, the HWRM shall return an error. The VF IDs + * returned by this function remain valid after the VF is disabled or reset. + */ +/* Input (24 bytes) */ + +struct hwrm_func_vf_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the first_vf_id field to be configured. */ + #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + uint16_t first_vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint16_t num_vfs; + /* The number of virtual functions requested. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_vf_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t first_vf_id; + /* The ID of the first VF allocated. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_vf_free */ +/* + * Description: This command will free allocated virtual functions on a physical + * function. If this command is called on a virtual function or a physical + * function that is not enabled for SR-IOV, the HWRM shall return an error. + * After the successful completion of this command, the VF IDs of the VFs that + * are freed on the PF are invalid. + */ +/* Input (24 bytes) */ + +struct hwrm_func_vf_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the first_vf_id field to be configured. */ + #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1) + uint16_t first_vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint16_t num_vfs; + /* + * The number of virtual functions requested. 0xFFFF - Cleanup all + * children of this PF. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_vf_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_vf_cfg */ +/* + * Description: This command allows configuration of a VF by its driver. If this + * function is called by a PF driver, then the HWRM shall fail this command. If + * guest VLAN and/or MAC address are provided in this command, then the HWRM + * shall set up appropriate MAC/VLAN filters for the VF that is being + * configured. A VF driver should set VF MTU/MRU using this command prior to + * allocating RX VNICs or TX rings for the corresponding VF. + */ +/* Input (32 bytes) */ + +struct hwrm_func_vf_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the mtu field to be configured. */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) + /* This bit must be '1' for the guest_vlan field to be configured. */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2) + /* This bit must be '1' for the async_event_cr field to be configured. */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4) + /* This bit must be '1' for the dflt_mac_addr field to be configured. */ + #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8) + uint16_t mtu; + /* + * The maximum transmission unit requested on the function. The HWRM + * should make sure that the mtu of the function does not exceed the mtu + * of the physical port that this function is associated with. In + * addition to requesting mtu per function, it is possible to configure + * mtu per transmit ring. By default, the mtu of each transmit ring + * associated with a function is equal to the mtu of the function. The + * HWRM should make sure that the mtu of each transmit ring that is + * assigned to a function has a valid mtu. + */ + uint16_t guest_vlan; + /* + * The guest VLAN for the function being configured. This field's format + * is same as 802.1Q Tag's Tag Control Information (TCI) format that + * includes both Priority Code Point (PCP) and VLAN Identifier (VID). + */ + uint16_t async_event_cr; + /* + * ID of the target completion ring for receiving asynchronous event + * completions. If this field is not valid, then the HWRM shall use the + * default completion ring of the function that is being configured as + * the target completion ring for providing any asynchronous event + * completions for that function. If this field is valid, then the HWRM + * shall use the completion ring identified by this ID as the target + * completion ring for providing any asynchronous event completions for + * the function that is being configured. + */ + uint8_t dflt_mac_addr[6]; + /* + * This value is the current MAC address requested by the VF driver to + * be configured on this VF. A value of 00-00-00-00-00-00 indicates no + * MAC address configuration is requested by the VF driver. The parent + * PF driver may reject or overwrite this MAC address. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_vf_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_qcaps */ +/* + * Description: This command returns capabilities of a function. The input FID + * value is used to indicate what function is being queried. This allows a + * physical function driver to query virtual functions that are children of the + * physical function. The output FID value is needed to configure Rings and + * MSI-X vectors so their DMA operations appear correctly on the PCI bus. + */ +/* Input (24 bytes) */ + +struct hwrm_func_qcaps_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t fid; + /* + * Function ID of the function that is being queried. 0xFF... (All Fs) + * if the query is for the requesting function. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (80 bytes) */ + +struct hwrm_func_qcaps_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t fid; + /* + * FID value. This value is used to identify operations on the PCI bus + * as belonging to a particular PCI function. + */ + uint16_t port_id; + /* + * Port ID of port that this function is associated with. Valid only for + * the PF. 0xFF... (All Fs) if this function is not associated with any + * port. 0xFF... (All Fs) if this function is called from a VF. + */ + uint32_t flags; + /* If 1, then Push mode is supported on this function. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1) + /* If 1, then the global MSI-X auto-masking is enabled for the device. */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING UINT32_C(0x2) + /* + * If 1, then the Precision Time Protocol (PTP) processing is supported + * on this function. The HWRM should enable PTP on only a single + * Physical Function (PF) per port. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4) + /* + * If 1, then RDMA over Converged Ethernet (RoCE) v1 is supported on + * this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED UINT32_C(0x8) + /* + * If 1, then RDMA over Converged Ethernet (RoCE) v2 is supported on + * this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10) + /* + * If 1, then control and configuration of WoL magic packet is supported + * on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20) + /* + * If 1, then control and configuration of bitmap pattern packet is + * supported on this function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40) + uint8_t mac_address[6]; + /* + * This value is current MAC address configured for this function. A + * value of 00-00-00-00-00-00 indicates no MAC address is currently + * configured. + */ + uint16_t max_rsscos_ctx; + /* + * The maximum number of RSS/COS contexts that can be allocated to the + * function. + */ + uint16_t max_cmpl_rings; + /* + * The maximum number of completion rings that can be allocated to the + * function. + */ + uint16_t max_tx_rings; + /* + * The maximum number of transmit rings that can be allocated to the + * function. + */ + uint16_t max_rx_rings; + /* + * The maximum number of receive rings that can be allocated to the + * function. + */ + uint16_t max_l2_ctxs; + /* + * The maximum number of L2 contexts that can be allocated to the + * function. + */ + uint16_t max_vnics; + /* The maximum number of VNICs that can be allocated to the function. */ + uint16_t first_vf_id; + /* + * The identifier for the first VF enabled on a PF. This is valid only + * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is + * called on a PF with SR-IOV disabled or on a VF. + */ + uint16_t max_vfs; + /* + * The maximum number of VFs that can be allocated to the function. This + * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this + * command is called on a PF with SR-IOV disabled or on a VF. + */ + uint16_t max_stat_ctx; + /* + * The maximum number of statistic contexts that can be allocated to the + * function. + */ + uint32_t max_encap_records; + /* + * The maximum number of Encapsulation records that can be offloaded by + * this function. + */ + uint32_t max_decap_records; + /* + * The maximum number of decapsulation records that can be offloaded by + * this function. + */ + uint32_t max_tx_em_flows; + /* + * The maximum number of Exact Match (EM) flows that can be offloaded by + * this function on the TX side. + */ + uint32_t max_tx_wm_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can be offloaded + * by this function on the TX side. + */ + uint32_t max_rx_em_flows; + /* + * The maximum number of Exact Match (EM) flows that can be offloaded by + * this function on the RX side. + */ + uint32_t max_rx_wm_flows; + /* + * The maximum number of Wildcard Match (WM) flows that can be offloaded + * by this function on the RX side. + */ + uint32_t max_mcast_filters; + /* + * The maximum number of multicast filters that can be supported by this + * function on the RX side. + */ + uint32_t max_flow_id; + /* + * The maximum value of flow_id that can be supported in completion + * records. + */ + uint32_t max_hw_ring_grps; + /* + * The maximum number of HW ring groups that can be supported on this + * function. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_qcfg */ +/* + * Description: This command returns the current configuration of a function. + * The input FID value is used to indicate what function is being queried. This + * allows a physical function driver to query virtual functions that are + * children of the physical function. The output FID value is needed to + * configure Rings and MSI-X vectors so their DMA operations appear correctly on + * the PCI bus. + */ +/* Input (24 bytes) */ + +struct hwrm_func_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t fid; + /* + * Function ID of the function that is being queried. 0xFF... (All Fs) + * if the query is for the requesting function. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (72 bytes) */ + +struct hwrm_func_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t fid; + /* + * FID value. This value is used to identify operations on the PCI bus + * as belonging to a particular PCI function. + */ + uint16_t port_id; + /* + * Port ID of port that this function is associated with. 0xFF... (All + * Fs) if this function is not associated with any port. + */ + uint16_t vlan; + /* + * This value is the current VLAN setting for this function. The value + * of 0 for this field indicates no priority tagging or VLAN is used. + * This field's format is same as 802.1Q Tag's Tag Control Information + * (TCI) format that includes both Priority Code Point (PCP) and VLAN + * Identifier (VID). + */ + uint16_t flags; + /* + * If 1, then magic packet based Out-Of-Box WoL is enabled on the port + * associated with this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED UINT32_C(0x1) + /* + * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled on + * the port associated with this function. + */ + #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2) + uint8_t mac_address[6]; + /* + * This value is current MAC address configured for this function. A + * value of 00-00-00-00-00-00 indicates no MAC address is currently + * configured. + */ + uint16_t pci_id; + /* + * This value is current PCI ID of this function. If ARI is enabled, + * then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus + * Number (8b):Device Number (4b):Function Number(4b). + */ + uint16_t alloc_rsscos_ctx; + /* The number of RSS/COS contexts currently allocated to the function. */ + uint16_t alloc_cmpl_rings; + /* + * The number of completion rings currently allocated to the function. + * This does not include the rings allocated to any children functions + * if any. + */ + uint16_t alloc_tx_rings; + /* + * The number of transmit rings currently allocated to the function. + * This does not include the rings allocated to any children functions + * if any. + */ + uint16_t alloc_rx_rings; + /* + * The number of receive rings currently allocated to the function. This + * does not include the rings allocated to any children functions if + * any. + */ + uint16_t alloc_l2_ctx; + /* The allocated number of L2 contexts to the function. */ + uint16_t alloc_vnics; + /* The allocated number of vnics to the function. */ + uint16_t mtu; + /* + * The maximum transmission unit of the function. For rings allocated on + * this function, this default value is used if ring MTU is not + * specified. + */ + uint16_t mru; + /* + * The maximum receive unit of the function. For vnics allocated on this + * function, this default value is used if vnic MRU is not specified. + */ + uint16_t stat_ctx_id; + /* The statistics context assigned to a function. */ + uint8_t port_partition_type; + /* + * The HWRM shall return Unknown value for this field when this command + * is used to query VF's configuration. + */ + /* Single physical function */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0) + /* Multiple physical functions */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1) + /* Network Partitioning 1.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2) + /* Network Partitioning 1.5 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3) + /* Network Partitioning 2.0 */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4) + /* Unknown */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff) + uint8_t unused_0; + uint16_t dflt_vnic_id; + /* The default VNIC ID assigned to a function that is being queried. */ + uint8_t unused_1; + uint8_t unused_2; + uint32_t min_bw; + /* + * Minimum BW allocated for this function in Mbps. The HWRM will + * translate this value into byte counter and time interval used for the + * scheduler inside the device. A value of 0 indicates the minimum + * bandwidth is not configured. + */ + uint32_t max_bw; + /* + * Maximum BW allocated for this function in Mbps. The HWRM will + * translate this value into byte counter and time interval used for the + * scheduler inside the device. A value of 0 indicates that the maximum + * bandwidth is not configured. + */ + uint8_t evb_mode; + /* + * This value indicates the Edge virtual bridge mode for the domain that + * this function belongs to. + */ + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2) + uint8_t unused_3; + uint16_t unused_4; + uint32_t alloc_mcast_filters; + /* + * The number of allocated multicast filters for this function on the RX + * side. + */ + uint32_t alloc_hw_ring_grps; + /* The number of allocated HW ring groups for this function. */ + uint8_t unused_5; + uint8_t unused_6; + uint8_t unused_7; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_cfg */ +/* + * Description: This command allows configuration of a PF by the corresponding + * PF driver. This command also allows configuration of a child VF by its parent + * PF driver. The input FID value is used to indicate what function is being + * configured. This allows a PF driver to configure the PF owned by itself or a + * virtual function that is a child of the PF. This command allows to reserve + * resources for a VF by its parent PF. To reverse the process, the command + * should be called with all enables flags cleared for resources. This will free + * allocated resources for the VF and return them to the resource pool. If this + * command is requested by a VF driver to configure or reserve resources, then + * the HWRM shall fail this command. If default MAC address and/or VLAN are + * provided in this command, then the HWRM shall set up appropriate MAC/VLAN + * filters for the function that is being configured. If source properties + * checks are enabled and default MAC address and/or IP address are provided in + * this command, then the HWRM shall set appropriate source property checks + * based on provided MAC and/or IP addresses. The parent PF driver should not + * set MTU/MRU for a VF using this command. This is to allow MTU/MRU setting by + * the VF driver. If the MTU or MRU for a VF is set by the PF driver, then the + * HWRM should ignore it. A function's MTU/MRU should be set prior to allocating + * RX VNICs or TX rings. + */ +/* Input (88 bytes) */ + +struct hwrm_func_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t fid; + /* + * Function ID of the function that is being configured. If set to + * 0xFF... (All Fs), then the the configuration is for the requesting + * function. + */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t flags; + /* + * When this bit is '1', the function is requested to be put in the + * promiscuous mode. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_PROM_MODE UINT32_C(0x1) + /* + * When this bit is '1', the function is enabled with source MAC address + * check. This is an anti-spoofing check. If this flag is set, then the + * function shall be configured to allow transmission of frames with the + * source MAC address that is configured for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK UINT32_C(0x2) + /* + * When this bit is '1', the function is enabled with source IP address + * check. This is an anti-spoofing check. If this flag is set, then the + * function shall be configured to allow transmission of frames with the + * source IP address that is configured for this function. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_IP_ADDR_CHECK UINT32_C(0x4) + /* + * When this bit is set to '1', the function shall be configured with + * VLAN priority match. If the VLAN PRI of a packet originated from this + * function does not match, then the packet shall be discarded. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_VLAN_PRI_MATCH UINT32_C(0x8) + /* + * When this bit is set to '1', the function shall be configured to + * check for VLAN priority match. If the VLAN PRI of a packet originated + * from this function does not match, then the default VLAN PRI shall be + * used. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DFLT_PRI_NOMATCH UINT32_C(0x10) + /* + * When this bit is set to '1', the function shall be configured to not + * allow the transmission of pause frames. PAUSE frames use 48-bit + * destination multicast MAC address 01-80-C2-00-00-01. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_PAUSE UINT32_C(0x20) + /* + * When this bit is set to '1', the function shall be configured to not + * allow the transmission of Spanning Tree Protocol (STP) frames. STP + * frames use Ethertype 0x0802 and 48-bit destination multicast MAC + * address 01-80-C2-00-00-00 and 01-80-C2-00-00-08 for 802.1D and + * 802.1ad respectively. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_STP UINT32_C(0x40) + /* + * When this bit is set to '1', the function shall be configured to not + * allow the transmission of Link Layer Discovery Protocol (LLDP) + * frames. LLDP frames use Ethertype 0x88CC and 48-bit destination + * multicast MAC address 01-80-C2-00-00-00 or 01-80-C2-00-00-03 or + * 01-80-C2-00-00-0E. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_LLDP UINT32_C(0x80) + /* + * When this bit is set to '1', the function shall be configured to not + * allow the transmission of Precision Time Protocol (PTP) v2 frames. + * PTP frames use Ethertype 0x88F7 and 48-bit destination multicast MAC + * address 01-80-C2-00-00-0E or 01-1B-19-00-00-00. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_DISABLE_PTPV2 UINT32_C(0x100) + uint32_t enables; + /* This bit must be '1' for the mtu field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU UINT32_C(0x1) + /* This bit must be '1' for the mru field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU UINT32_C(0x2) + /* This bit must be '1' for the num_rsscos_ctxs field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x4) + /* This bit must be '1' for the num_cmpl_rings field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x8) + /* This bit must be '1' for the num_tx_rings field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x10) + /* This bit must be '1' for the num_rx_rings field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x20) + /* This bit must be '1' for the num_l2_ctxs field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x40) + /* This bit must be '1' for the num_vnics field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x80) + /* This bit must be '1' for the num_stat_ctxs field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x100) + /* This bit must be '1' for the dflt_mac_addr field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x200) + /* This bit must be '1' for the dflt_vlan field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN UINT32_C(0x400) + /* This bit must be '1' for the dflt_ip_addr field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR UINT32_C(0x800) + /* This bit must be '1' for the min_bw field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW UINT32_C(0x1000) + /* This bit must be '1' for the max_bw field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW UINT32_C(0x2000) + /* This bit must be '1' for the async_event_cr field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4000) + /* + * This bit must be '1' for the vlan_antispoof_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE UINT32_C(0x8000) + /* + * This bit must be '1' for the allowed_vlan_pris field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS UINT32_C(0x10000) + /* This bit must be '1' for the evb_mode field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE UINT32_C(0x20000) + /* + * This bit must be '1' for the num_mcast_filters field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS UINT32_C(0x40000) + /* This bit must be '1' for the num_hw_ring_grps field to be configured. */ + #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x80000) + uint16_t mtu; + /* + * The maximum transmission unit of the function. The HWRM should make + * sure that the mtu of the function does not exceed the mtu of the + * physical port that this function is associated with. In addition to + * configuring mtu per function, it is possible to configure mtu per + * transmit ring. By default, the mtu of each transmit ring associated + * with a function is equal to the mtu of the function. The HWRM should + * make sure that the mtu of each transmit ring that is assigned to a + * function has a valid mtu. + */ + uint16_t mru; + /* + * The maximum receive unit of the function. The HWRM should make sure + * that the mru of the function does not exceed the mru of the physical + * port that this function is associated with. In addition to + * configuring mru per function, it is possible to configure mru per + * vnic. By default, the mru of each vnic associated with a function is + * equal to the mru of the function. The HWRM should make sure that the + * mru of each vnic that is assigned to a function has a valid mru. + */ + uint16_t num_rsscos_ctxs; + /* The number of RSS/COS contexts requested for the function. */ + uint16_t num_cmpl_rings; + /* + * The number of completion rings requested for the function. This does + * not include the rings allocated to any children functions if any. + */ + uint16_t num_tx_rings; + /* + * The number of transmit rings requested for the function. This does + * not include the rings allocated to any children functions if any. + */ + uint16_t num_rx_rings; + /* + * The number of receive rings requested for the function. This does not + * include the rings allocated to any children functions if any. + */ + uint16_t num_l2_ctxs; + /* The requested number of L2 contexts for the function. */ + uint16_t num_vnics; + /* The requested number of vnics for the function. */ + uint16_t num_stat_ctxs; + /* The requested number of statistic contexts for the function. */ + uint16_t num_hw_ring_grps; + /* + * The number of HW ring groups that should be reserved for this + * function. + */ + uint8_t dflt_mac_addr[6]; + /* The default MAC address for the function being configured. */ + uint16_t dflt_vlan; + /* + * The default VLAN for the function being configured. This field's + * format is same as 802.1Q Tag's Tag Control Information (TCI) format + * that includes both Priority Code Point (PCP) and VLAN Identifier + * (VID). + */ + uint32_t dflt_ip_addr[4]; /* big endian */ + /* + * The default IP address for the function being configured. This + * address is only used in enabling source property check. + */ + uint32_t min_bw; + /* + * Minimum BW allocated for this function in Mbps. The HWRM will + * translate this value into byte counter and time interval used for the + * scheduler inside the device. + */ + uint32_t max_bw; + /* + * Maximum BW allocated for this function in Mbps. The HWRM will + * translate this value into byte counter and time interval used for the + * scheduler inside the device. + */ + uint16_t async_event_cr; + /* + * ID of the target completion ring for receiving asynchronous event + * completions. If this field is not valid, then the HWRM shall use the + * default completion ring of the function that is being configured as + * the target completion ring for providing any asynchronous event + * completions for that function. If this field is valid, then the HWRM + * shall use the completion ring identified by this ID as the target + * completion ring for providing any asynchronous event completions for + * the function that is being configured. + */ + uint8_t vlan_antispoof_mode; + /* VLAN Anti-spoofing mode. */ + /* No VLAN anti-spoofing checks are enabled */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK UINT32_C(0x0) + /* Validate VLAN against the configured VLAN(s) */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN UINT32_C(0x1) + /* Insert VLAN if it does not exist, otherwise discard */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE UINT32_C(0x2) + /* Insert VLAN if it does not exist, override VLAN if it exists */ + #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN UINT32_C(0x3) + uint8_t allowed_vlan_pris; + /* + * This bit field defines VLAN PRIs that are allowed on this function. + * If nth bit is set, then VLAN PRI n is allowed on this function. + */ + uint8_t evb_mode; + /* + * The HWRM shall allow a PF driver to change EVB mode for the partition + * it belongs to. The HWRM shall not allow a VF driver to change the EVB + * mode. The HWRM shall take into account the switching of EVB mode from + * one to another and reconfigure hardware resources as appropriately. + * The switching from VEB to VEPA mode requires the disabling of the + * loopback traffic. Additionally, source knock outs are handled + * differently in VEB and VEPA modes. + */ + /* No Edge Virtual Bridging (EVB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0) + /* Virtual Ethernet Bridge (VEB) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1) + /* Virtual Ethernet Port Aggregator (VEPA) */ + #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2) + uint8_t unused_2; + uint16_t num_mcast_filters; + /* + * The number of multicast filters that should be reserved for this + * function on the RX side. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_qstats */ +/* + * Description: This command returns statistics of a function. The input FID + * value is used to indicate what function is being queried. This allows a + * physical function driver to query virtual functions that are children of the + * physical function. The HWRM shall return any unsupported counter with a value + * of 0xFFFFFFFF for 32-bit counters and 0xFFFFFFFFFFFFFFFF for 64-bit counters. + */ +/* Input (24 bytes) */ + +struct hwrm_func_qstats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t fid; + /* + * Function ID of the function that is being queried. 0xFF... (All Fs) + * if the query is for the requesting function. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (176 bytes) */ + +struct hwrm_func_qstats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t tx_ucast_pkts; + /* Number of transmitted unicast packets on the function. */ + uint64_t tx_mcast_pkts; + /* Number of transmitted multicast packets on the function. */ + uint64_t tx_bcast_pkts; + /* Number of transmitted broadcast packets on the function. */ + uint64_t tx_err_pkts; + /* + * Number of transmitted packets that were dropped due to internal NIC + * resource problems. For transmit, this can only happen if TMP is + * configured to allow dropping in HOL blocking conditions, which is not + * a normal configuration. + */ + uint64_t tx_drop_pkts; + /* + * Number of dropped packets on transmit path on the function. These are + * packets that have been marked for drop by the TE CFA block or are + * packets that exceeded the transmit MTU limit for the function. + */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for unicast traffic on the function. */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for multicast traffic on the function. */ + uint64_t tx_bcast_bytes; + /* Number of transmitted bytes for broadcast traffic on the function. */ + uint64_t rx_ucast_pkts; + /* Number of received unicast packets on the function. */ + uint64_t rx_mcast_pkts; + /* Number of received multicast packets on the function. */ + uint64_t rx_bcast_pkts; + /* Number of received broadcast packets on the function. */ + uint64_t rx_err_pkts; + /* + * Number of received packets that were dropped on the function due to + * resource limitations. This can happen for 3 reasons. # The BD used + * for the packet has a bad format. # There were no BDs available in the + * ring for the packet. # There were no BDs available on-chip for the + * packet. + */ + uint64_t rx_drop_pkts; + /* + * Number of dropped packets on received path on the function. These are + * packets that have been marked for drop by the RE CFA. + */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for unicast traffic on the function. */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for multicast traffic on the function. */ + uint64_t rx_bcast_bytes; + /* Number of received bytes for broadcast traffic on the function. */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast packets on the function. */ + uint64_t rx_agg_bytes; + /* Number of aggregated unicast bytes on the function. */ + uint64_t rx_agg_events; + /* Number of aggregation events on the function. */ + uint64_t rx_agg_aborts; + /* Number of aborted aggregations on the function. */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_clr_stats */ +/* + * Description: This command clears statistics of a function. The input FID + * value is used to indicate what function's statistics is being cleared. This + * allows a physical function driver to clear statistics of virtual functions + * that are children of the physical function. + */ +/* Input (24 bytes) */ + +struct hwrm_func_clr_stats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t fid; + /* + * Function ID of the function. 0xFF... (All Fs) if the query is for the + * requesting function. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_clr_stats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_vf_resc_free */ +/* Description: This command frees resources of a vf. */ +/* Input (24 bytes) */ + +struct hwrm_func_vf_resc_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_vf_resc_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_vf_vnic_ids_query */ +/* Description: This command is used to query vf vnic ids. */ +/* Input (32 bytes) */ + +struct hwrm_func_vf_vnic_ids_query_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t max_vnic_id_cnt; + /* Max number of vnic ids in vnic id table */ + uint64_t vnic_id_tbl_addr; + /* This is the address for VF VNIC ID table */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_vf_vnic_ids_query_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t vnic_id_cnt; + /* Actual number of vnic ids Each VNIC ID is written as a 32-bit number. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_drv_rgtr */ +/* + * Description: This command is used by the function driver to register its + * information with the HWRM. A function driver shall implement this command. A + * function driver shall use this command during the driver initialization right + * after the HWRM version discovery and default ring resources allocation. + */ +/* Input (80 bytes) */ + +struct hwrm_func_drv_rgtr_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', the function driver is requesting all requests + * from its children VF drivers to be forwarded to itself. This flag can + * only be set by the PF driver. If a VF driver sets this flag, it + * should be ignored by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1) + /* + * When this bit is '1', the function is requesting none of the requests + * from its children VF drivers to be forwarded to itself. This flag can + * only be set by the PF driver. If a VF driver sets this flag, it + * should be ignored by the HWRM. + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2) + uint32_t enables; + /* This bit must be '1' for the os_type field to be configured. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1) + /* This bit must be '1' for the ver field to be configured. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2) + /* This bit must be '1' for the timestamp field to be configured. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4) + /* This bit must be '1' for the vf_req_fwd field to be configured. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8) + /* This bit must be '1' for the async_event_fwd field to be configured. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10) + uint16_t os_type; + /* This value indicates the type of OS. */ + /* Unknown */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + uint8_t ver_maj; + /* This is the major version of the driver. */ + uint8_t ver_min; + /* This is the minor version of the driver. */ + uint8_t ver_upd; + /* This is the update version of the driver. */ + uint8_t unused_0; + uint16_t unused_1; + uint32_t timestamp; + /* + * This is a 32-bit timestamp provided by the driver for keep alive. The + * timestamp is in multiples of 1ms. + */ + uint32_t unused_2; + uint32_t vf_req_fwd[8]; + /* + * This is a 256-bit bit mask provided by the PF driver for letting the + * HWRM know what commands issued by the VF driver to the HWRM should be + * forwarded to the PF driver. Nth bit refers to the Nth req_type. + * Setting Nth bit to 1 indicates that requests from the VF driver with + * req_type equal to N shall be forwarded to the parent PF driver. This + * field is not valid for the VF driver. + */ + uint32_t async_event_fwd[8]; + /* + * This is a 256-bit bit mask provided by the function driver (PF or VF + * driver) to indicate the list of asynchronous event completions to be + * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1 + * by the function driver shall result in the HWRM forwarding + * asynchronous event completion with event_id equal to N. If all bits + * are set to 0 (value of 0), then the HWRM shall not forward any + * asynchronous event completion to this function driver. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_drv_rgtr_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_drv_unrgtr */ +/* + * Description: This command is used by the function driver to un register with + * the HWRM. A function driver shall implement this command. A function driver + * shall use this command during the driver unloading. + */ +/* Input (24 bytes) */ + +struct hwrm_func_drv_unrgtr_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', the function driver is notifying the HWRM to + * prepare for the shutdown. + */ + #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN UINT32_C(0x1) + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_drv_unrgtr_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_buf_rgtr */ +/* + * Description: This command is used by the PF driver to register buffers used + * in the PF-VF communication with the HWRM. The PF driver uses this command to + * register buffers for each PF-VF channel. A parent PF may issue this command + * per child VF. If VF ID is not valid, then this command is used to register + * buffers for all children VFs of the PF. + */ +/* Input (128 bytes) */ + +struct hwrm_func_buf_rgtr_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the vf_id field to be configured. */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + /* This bit must be '1' for the err_buf_addr field to be configured. */ + #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2) + uint16_t vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint16_t req_buf_num_pages; + /* This field represents the number of pages used for request buffer(s). */ + uint16_t req_buf_page_size; + /* This field represents the page size used for request buffer(s). */ + /* 16 bytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4) + /* 4 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc) + /* 8 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd) + /* 64 Kbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10) + /* 2 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15) + /* 4 Mbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16) + /* 1 Gbytes */ + #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e) + uint16_t req_buf_len; + /* The length of the request buffer per VF in bytes. */ + uint16_t resp_buf_len; + /* The length of the response buffer in bytes. */ + uint8_t unused_0; + uint8_t unused_1; + uint64_t req_buf_page_addr0; + /* This field represents the page address of page #0. */ + uint64_t req_buf_page_addr1; + /* This field represents the page address of page #1. */ + uint64_t req_buf_page_addr2; + /* This field represents the page address of page #2. */ + uint64_t req_buf_page_addr3; + /* This field represents the page address of page #3. */ + uint64_t req_buf_page_addr4; + /* This field represents the page address of page #4. */ + uint64_t req_buf_page_addr5; + /* This field represents the page address of page #5. */ + uint64_t req_buf_page_addr6; + /* This field represents the page address of page #6. */ + uint64_t req_buf_page_addr7; + /* This field represents the page address of page #7. */ + uint64_t req_buf_page_addr8; + /* This field represents the page address of page #8. */ + uint64_t req_buf_page_addr9; + /* This field represents the page address of page #9. */ + uint64_t error_buf_addr; + /* + * This field is used to receive the error reporting from the chipset. + * Only applicable for PFs. + */ + uint64_t resp_buf_addr; + /* This field is used to receive the response forwarded by the HWRM. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_buf_rgtr_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_buf_unrgtr */ +/* + * Description: This command is used by the PF driver to unregister buffers used + * in the PF-VF communication with the HWRM. The PF driver uses this command to + * unregister buffers for PF-VF communication. A parent PF may issue this + * command to unregister buffers for communication between the PF and a specific + * VF. If the VF ID is not valid, then this command is used to unregister + * buffers used for communications with all children VFs of the PF. + */ +/* Input (24 bytes) */ + +struct hwrm_func_buf_unrgtr_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the vf_id field to be configured. */ + #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1) + uint16_t vf_id; + /* + * This value is used to identify a Virtual Function (VF). The scope of + * VF ID is local within a PF. + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_buf_unrgtr_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_func_drv_qver */ +/* + * Description: This command is used to query the version of the driver. Any + * driver version with major = 0, minor = 0, and update = 0 shall be considered + * an invalid or unknown version. + */ +/* Input (24 bytes) */ + +struct hwrm_func_drv_qver_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t reserved; + /* Reserved for future use */ + uint16_t fid; + /* + * Function ID of the function that is being queried. 0xFF... (All Fs) + * if the query is for the requesting function. + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_func_drv_qver_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t os_type; + /* This value indicates the type of OS. */ + /* Unknown */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0) + /* Other OS not listed below. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1) + /* MSDOS OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe) + /* Windows OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12) + /* Solaris OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d) + /* Linux OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24) + /* FreeBSD OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a) + /* VMware ESXi OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68) + /* Microsoft Windows 8 64-bit OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73) + /* Microsoft Windows Server 2012 R2 OS. */ + #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74) + uint8_t ver_maj; + /* This is the major version of the driver. */ + uint8_t ver_min; + /* This is the minor version of the driver. */ + uint8_t ver_upd; + /* This is the update version of the driver. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_phy_cfg */ +/* + * Description: This command configures the PHY device for the port. It allows + * setting of the most generic settings for the PHY. The HWRM shall complete + * this command as soon as PHY settings are configured. They may not be applied + * when the command response is provided. A VF driver shall not be allowed to + * configure PHY using this command. In a network partition mode, a PF driver + * shall not be allowed to configure PHY using this command. + */ +/* Input (56 bytes) */ + +struct hwrm_port_phy_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is set to '1', the PHY for the port shall be reset. # + * If this bit is set to 1, then the HWRM shall reset the PHY after + * applying PHY configuration changes specified in this command. # In + * order to guarantee that PHY configuration changes specified in this + * command take effect, the HWRM client should set this flag to 1. # If + * this bit is not set to 1, then the HWRM may reset the PHY depending + * on the current PHY configuration and settings specified in this + * command. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1) + /* + * When this bit is set to '1', the link shall be forced to be taken + * down. # When this bit is set to '1", all other command input settings + * related to the link speed shall be ignored. Once the link state is + * forced down, it can be explicitly cleared from that state by setting + * this flag to '0'. # If this flag is set to '0', then the link shall + * be cleared from forced down state if the link is in forced down + * state. There may be conditions (e.g. out-of-band or sideband + * configuration changes for the link) outside the scope of the HWRM + * implementation that may clear forced down link state. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2) + /* + * When this bit is set to '1', the link shall be forced to the + * force_link_speed value. When this bit is set to '1', the HWRM client + * should not enable any of the auto negotiation related fields + * represented by auto_XXX fields in this command. When this bit is set + * to '1' and the HWRM client has enabled a auto_XXX field in this + * command, then the HWRM shall ignore the enabled auto_XXX field. When + * this bit is set to zero, the link shall be allowed to autoneg. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4) + /* + * When this bit is set to '1', the auto-negotiation process shall be + * restarted on the link. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8) + /* + * When this bit is set to '1', Energy Efficient Ethernet (EEE) is + * requested to be enabled on this link. If EEE is not supported on this + * port, then this flag shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10) + /* + * When this bit is set to '1', Energy Efficient Ethernet (EEE) is + * requested to be disabled on this link. If EEE is not supported on + * this port, then this flag shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20) + /* + * When this bit is set to '1' and EEE is enabled on this link, then TX + * LPI is requested to be enabled on the link. If EEE is not supported + * on this port, then this flag shall be ignored by the HWRM. If EEE is + * disabled on this port, then this flag shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE UINT32_C(0x40) + /* + * When this bit is set to '1' and EEE is enabled on this link, then TX + * LPI is requested to be disabled on the link. If EEE is not supported + * on this port, then this flag shall be ignored by the HWRM. If EEE is + * disabled on this port, then this flag shall be ignored by the HWRM. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80) + /* + * When set to 1, then the HWRM shall enable FEC autonegotitation on + * this port if supported. When set to 0, then this flag shall be + * ignored. If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100) + /* + * When set to 1, then the HWRM shall disable FEC autonegotiation on + * this port if supported. When set to 0, then this flag shall be + * ignored. If FEC autonegotiation is not supported, then the HWRM shall + * ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200) + /* + * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code) + * on this port if supported. When set to 0, then this flag shall be + * ignored. If FEC CLAUSE 74 is not supported, then the HWRM shall + * ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400) + /* + * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code) + * on this port if supported. When set to 0, then this flag shall be + * ignored. If FEC CLAUSE 74 is not supported, then the HWRM shall + * ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE UINT32_C(0x800) + /* + * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed + * Solomon) on this port if supported. When set to 0, then this flag + * shall be ignored. If FEC CLAUSE 91 is not supported, then the HWRM + * shall ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE UINT32_C(0x1000) + /* + * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed + * Solomon) on this port if supported. When set to 0, then this flag + * shall be ignored. If FEC CLAUSE 91 is not supported, then the HWRM + * shall ignore this flag. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000) + uint32_t enables; + /* This bit must be '1' for the auto_mode field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1) + /* This bit must be '1' for the auto_duplex field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2) + /* This bit must be '1' for the auto_pause field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4) + /* This bit must be '1' for the auto_link_speed field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8) + /* + * This bit must be '1' for the auto_link_speed_mask field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK UINT32_C(0x10) + /* This bit must be '1' for the wirespeed field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20) + /* This bit must be '1' for the lpbk field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40) + /* This bit must be '1' for the preemphasis field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80) + /* This bit must be '1' for the force_pause field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100) + /* + * This bit must be '1' for the eee_link_speed_mask field to be + * configured. + */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK UINT32_C(0x200) + /* This bit must be '1' for the tx_lpi_timer field to be configured. */ + #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400) + uint16_t port_id; + /* Port ID of port that is to be configured. */ + uint16_t force_link_speed; + /* + * This is the speed that will be used if the force bit is '1'. If + * unsupported speed is selected, an error will be generated. + */ + /* 100Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) + uint8_t auto_mode; + /* + * This value is used to identify what autoneg mode is used when the + * link speed is not being forced. + */ + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0) + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + /* + * Select only the auto_link_speed speed for autoneg mode. This + * mode has been DEPRECATED. An HWRM client should not use this + * mode. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + /* + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should + * not use this mode. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask + * value that is provided. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) + uint8_t auto_duplex; + /* + * This is the duplex setting that will be used if the autoneg_mode is + * "one_speed" or "one_or_below". + */ + /* Half Duplex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0) + /* Full duplex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1) + /* Both Half and Full dupex will be requested. */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2) + uint8_t auto_pause; + /* + * This value is used to configure the pause that will be used for + * autonegotiation. Add text on the usage of auto_pause and force_pause. + */ + /* + * When this bit is '1', Generation of tx pause messages has been + * requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages has been + * requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2) + /* + * When set to 1, the advertisement of pause is enabled. # When the + * auto_mode is not set to none and this flag is set to 1, then the + * auto_pause bits on this port are being advertised and autoneg pause + * results are being interpreted. # When the auto_mode is not set to + * none and this flag is set to 0, the pause is forced as indicated in + * force_pause, and also advertised as auto_pause bits, but the autoneg + * results are not interpreted since the pause configuration is being + * forced. # When the auto_mode is set to none and this flag is set to + * 1, auto_pause bits should be ignored and should be set to 0. + */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4) + uint8_t unused_0; + uint16_t auto_link_speed; + /* + * This is the speed that will be used if the autoneg_mode is + * "one_speed" or "one_or_below". If an unsupported speed is selected, + * an error will be generated. + */ + /* 100Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) + uint16_t auto_link_speed_mask; + /* + * This is a mask of link speeds that will be used if autoneg_mode is + * "mask". If unsupported speed is enabled an error will be generated. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000) + uint8_t wirespeed; + /* This value controls the wirespeed feature. */ + /* Wirespeed feature is disabled. */ + #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0) + /* Wirespeed feature is enabled. */ + #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1) + uint8_t lpbk; + /* This value controls the loopback setting for the PHY. */ + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that host + * data is sent back to the host without modification. + */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that port + * logic will send packets back out the transmitter that are + * received. + */ + #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t force_pause; + /* + * This value is used to configure the pause that will be used for force + * mode. + */ + /* + * When this bit is '1', Generation of tx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2) + uint8_t unused_1; + uint32_t preemphasis; + /* + * This value controls the pre-emphasis to be used for the link. Driver + * should not set this value (use enable.preemphasis = 0) unless driver + * is sure of setting. Normally HWRM FW will determine proper pre- + * emphasis. + */ + uint16_t eee_link_speed_mask; + /* + * Setting for link speed mask that is used to advertise speeds during + * autonegotiation when EEE is enabled. This field is valid only when + * EEE is enabled. The speeds specified in this field shall be a subset + * of speeds specified in auto_link_speed_mask. If EEE is enabled,then + * at least one speed shall be provided in this mask. + */ + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40) + uint8_t unused_2; + uint8_t unused_3; + uint32_t tx_lpi_timer; + uint32_t unused_4; + /* + * Reuested setting of TX LPI timer in microseconds. This field is valid + * only when EEE is enabled and TX LPI is enabled. + */ + #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) + #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0 +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_phy_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_phy_qcfg */ +/* Description: This command queries the PHY configuration for the port. */ +/* Input (24 bytes) */ + +struct hwrm_port_phy_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port that is to be queried. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (96 bytes) */ + +struct hwrm_port_phy_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t link; + /* This value indicates the current link status. */ + /* There is no link or cable detected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0) + /* There is no link, but a cable has been detected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1) + /* There is a link. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2) + uint8_t unused_0; + uint16_t link_speed; + /* This value indicates the current link speed of the connection. */ + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff) + uint8_t duplex; + /* This value is indicates the duplex of the current connection. */ + /* Half Duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_HALF UINT32_C(0x0) + /* Full duplex connection. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL UINT32_C(0x1) + uint8_t pause; + /* + * This value is used to indicate the current pause configuration. When + * autoneg is enabled, this value represents the autoneg results of + * pause configuration. + */ + /* + * When this bit is '1', Generation of tx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2) + uint16_t support_speeds; + /* + * The supported speeds for the port. This is a bit mask. For each speed + * that is supported, the corrresponding bit will be set to '1'. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB UINT32_C(0x2000) + uint16_t force_link_speed; + /* + * Current setting of forced link speed. When the link speed is not + * being forced, this value shall be set to 0. + */ + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff) + uint8_t auto_mode; + /* Current setting of auto negotiation mode. */ + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0) + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + /* + * Select only the auto_link_speed speed for autoneg mode. This + * mode has been DEPRECATED. An HWRM client should not use this + * mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + /* + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should + * not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask + * value that is provided. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4) + uint8_t auto_pause; + /* + * Current setting of pause autonegotiation. Move autoneg_pause flag + * here. + */ + /* + * When this bit is '1', Generation of tx pause messages has been + * requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages has been + * requested. Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2) + /* + * When set to 1, the advertisement of pause is enabled. # When the + * auto_mode is not set to none and this flag is set to 1, then the + * auto_pause bits on this port are being advertised and autoneg pause + * results are being interpreted. # When the auto_mode is not set to + * none and this flag is set to 0, the pause is forced as indicated in + * force_pause, and also advertised as auto_pause bits, but the autoneg + * results are not interpreted since the pause configuration is being + * forced. # When the auto_mode is set to none and this flag is set to + * 1, auto_pause bits should be ignored and should be set to 0. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4) + uint16_t auto_link_speed; + /* + * Current setting for auto_link_speed. This field is only valid when + * auto_mode is set to "one_speed" or "one_or_below". + */ + /* 100Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1) + /* 1Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64) + /* 20Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8) + /* 10Mb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff) + uint16_t auto_link_speed_mask; + /* + * Current setting for auto_link_speed_mask that is used to advertise + * speeds during autonegotiation. This field is only valid when + * auto_mode is set to "mask". The speeds specified in this field shall + * be a subset of supported speeds on this port. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000) + uint8_t wirespeed; + /* Current setting for wirespeed. */ + /* Wirespeed feature is disabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0) + /* Wirespeed feature is enabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1) + uint8_t lpbk; + /* Current setting for loopback. */ + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that host + * data is sent back to the host without modification. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that port + * logic will send packets back out the transmitter that are + * received. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t force_pause; + /* + * Current setting of forced pause. When the pause configuration is not + * being forced, then this value shall be set to 0. + */ + /* + * When this bit is '1', Generation of tx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2) + uint8_t module_status; + /* + * This value indicates the current status of the optics module on this + * port. + */ + /* Module is inserted and accepted */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE UINT32_C(0x0) + /* Module is rejected and transmit side Laser is disabled. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX UINT32_C(0x1) + /* Module mismatch warning. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG UINT32_C(0x2) + /* Module is rejected and powered down. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN UINT32_C(0x3) + /* Module is not inserted. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED UINT32_C(0x4) + /* Module status is not applicable. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff) + uint32_t preemphasis; + /* Current setting for preemphasis. */ + uint8_t phy_maj; + /* This field represents the major version of the PHY. */ + uint8_t phy_min; + /* This field represents the minor version of the PHY. */ + uint8_t phy_bld; + /* This field represents the build version of the PHY. */ + uint8_t phy_type; + /* This value represents a PHY type. */ + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN UINT32_C(0x0) + /* BASE-CR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR UINT32_C(0x1) + /* BASE-KR4 (Deprecated) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 UINT32_C(0x2) + /* BASE-LR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR UINT32_C(0x3) + /* BASE-SR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR UINT32_C(0x4) + /* BASE-KR2 (Deprecated) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 UINT32_C(0x5) + /* BASE-KX */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX UINT32_C(0x6) + /* BASE-KR */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR UINT32_C(0x7) + /* BASE-T */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET UINT32_C(0x8) + /* EEE capable BASE-T */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9) + /* SGMII connected external PHY */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa) + uint8_t media_type; + /* This value represents a media type. */ + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0) + /* Twisted Pair */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1) + /* Direct Attached Copper */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2) + /* Fiber */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3) + uint8_t xcvr_pkg_type; + /* This value represents a transceiver type. */ + /* PHY and MAC are in the same package */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL UINT32_C(0x1) + /* PHY and MAC are in different packages */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL UINT32_C(0x2) + uint8_t eee_config_phy_addr; + /* + * This field represents flags related to EEE configuration. These EEE + * configuration flags are valid only when the auto_mode is not set to + * none (in other words autonegotiation is enabled). + */ + /* This field represents PHY address. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f) + #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0 + /* + * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled. + * Speeds for autoneg with EEE mode enabled are based on + * eee_link_speed_mask. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20) + /* + * This flag is valid only when eee_enabled is set to 1. # If + * eee_enabled is set to 0, then EEE mode is disabled and this flag + * shall be ignored. # If eee_enabled is set to 1 and this flag is set + * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and in + * use. # If eee_enabled is set to 1 and this flag is set to 0, then + * Energy Efficient Ethernet (EEE) mode is enabled but is currently not + * in use. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE UINT32_C(0x40) + /* + * This flag is valid only when eee_enabled is set to 1. # If + * eee_enabled is set to 0, then EEE mode is disabled and this flag + * shall be ignored. # If eee_enabled is set to 1 and this flag is set + * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and TX LPI + * is enabled. # If eee_enabled is set to 1 and this flag is set to 0, + * then Energy Efficient Ethernet (EEE) mode is enabled but TX LPI is + * disabled. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI UINT32_C(0x80) + /* + * This field represents flags related to EEE configuration. These EEE + * configuration flags are valid only when the auto_mode is not set to + * none (in other words autonegotiation is enabled). + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0) + #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5 + uint8_t parallel_detect; + /* Reserved field, set to 0 */ + /* + * When set to 1, the parallel detection is used to determine the speed + * of the link partner. Parallel detection is used when a + * autonegotiation capable device is connected to a link parter that is + * not capable of autonegotiation. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1) + /* Reserved field, set to 0 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_MASK UINT32_C(0xfe) + #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_SFT 1 + uint16_t link_partner_adv_speeds; + /* + * The advertised speeds for the port by the link partner. Each + * advertised speed will be set to '1'. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB UINT32_C(0x2000) + uint8_t link_partner_adv_auto_mode; + /* + * The advertised autoneg for the port by the link partner. This field + * is deprecated and should be set to 0. + */ + /* Disable autoneg or autoneg disabled. No speeds are selected. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE UINT32_C(0x0) + /* Select all possible speeds for autoneg mode. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1) + /* + * Select only the auto_link_speed speed for autoneg mode. This + * mode has been DEPRECATED. An HWRM client should not use this + * mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2) + /* + * Select the auto_link_speed or any speed below that speed for + * autoneg. This mode has been DEPRECATED. An HWRM client should + * not use this mode. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3) + /* + * Select the speeds based on the corresponding link speed mask + * value that is provided. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK UINT32_C(0x4) + uint8_t link_partner_adv_pause; + /* The advertised pause settings on the port by the link partner. */ + /* + * When this bit is '1', Generation of tx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX UINT32_C(0x1) + /* + * When this bit is '1', Reception of rx pause messages is supported. + * Disabled otherwise. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX UINT32_C(0x2) + uint16_t adv_eee_link_speed_mask; + /* + * Current setting for link speed mask that is used to advertise speeds + * during autonegotiation when EEE is enabled. This field is valid only + * when eee_enabled flags is set to 1. The speeds specified in this + * field shall be a subset of speeds specified in auto_link_speed_mask. + */ + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40) + uint16_t link_partner_adv_eee_link_speed_mask; + /* + * Current setting for link speed mask that is advertised by the link + * partner when EEE is enabled. This field is valid only when + * eee_enabled flags is set to 1. + */ + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40) + uint32_t xcvr_identifier_type_tx_lpi_timer; + /* This value represents transceiver identifier type. */ + /* + * Current setting of TX LPI timer in microseconds. This field is valid + * only when_eee_enabled flag is set to 1 and tx_lpi_enabled is set to + * 1. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0 + /* This value represents transceiver identifier type. */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24 + /* Unknown */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN (UINT32_C(0x0) << 24) + /* SFP/SFP+/SFP28 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP (UINT32_C(0x3) << 24) + /* QSFP */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24) + /* QSFP+ */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24) + /* QSFP28 */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24) + uint16_t fec_cfg; + /* + * This value represents the current configuration of Forward Error + * Correction (FEC) on the port. + */ + /* + * When set to 1, then FEC is not supported on this port. If this flag + * is set to 1, then all other FEC configuration flags shall be ignored. + * When set to 0, then FEC is supported as indicated by other + * configuration flags. If no cable is attached and the HWRM does not + * yet know the FEC capability, then the HWRM shall set this flag to 1 + * when reporting FEC capability. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1) + /* + * When set to 1, then FEC autonegotiation is supported on this port. + * When set to 0, then FEC autonegotiation is not supported on this + * port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2) + /* + * When set to 1, then FEC autonegotiation is enabled on this port. When + * set to 0, then FEC autonegotiation is disabled if supported. This + * flag should be ignored if FEC autonegotiation is not supported on + * this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4) + /* + * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this + * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported + * on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8) + /* + * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this + * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if + * supported. This flag should be ignored if FEC CLAUSE 74 is not + * supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10) + /* + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this + * port. When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not + * supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED UINT32_C(0x20) + /* + * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this + * port. When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if + * supported. This flag should be ignored if FEC CLAUSE 91 is not + * supported on this port. + */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40) + uint8_t unused_1; + uint8_t unused_2; + char phy_vendor_name[16]; + /* + * Up to 16 bytes of null padded ASCII string representing PHY vendor. + * If the string is set to null, then the vendor name is not available. + */ + char phy_vendor_partnumber[16]; + /* + * Up to 16 bytes of null padded ASCII string that identifies vendor + * specific part number of the PHY. If the string is set to null, then + * the vendor specific part number is not available. + */ + uint32_t unused_3; + uint8_t unused_4; + uint8_t unused_5; + uint8_t unused_6; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_mac_cfg */ +/* Description: This command configures the MAC block for the port. */ +/* Input (40 bytes) */ + +struct hwrm_port_mac_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', this command will configure the MAC to match + * the current link state of the PHY. If the link is not established on + * the PHY, then this bit has no effect. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1) + /* + * When this bit is '1', the CoS assignment logic is enabled. When this + * logic is enabled, then inner VLAN PRI to CoS mapping is enabled. If + * this bit is '0', then the default CoS is used. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_COS_ASSIGNMENT_ENABLE UINT32_C(0x2) + /* + * When this bit is '1', tunnel or outer VLAN PRI field to CoS mapping + * is enabled. If this bit is '0', then outer VLAN PRI bits are not used + * in determining CoS. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4) + /* + * When this bit is '1', the IP DSCP to CoS mapping is enabled. If this + * bit is '0', then IP DSCP bits are not used in determining CoS. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8) + /* + * When this bit is '1', the HWRM is requested to enable timestamp + * capture capability on the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10) + /* + * When this bit is '1', the HWRM is requested to disable timestamp + * capture capability on the receive side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE UINT32_C(0x20) + /* + * When this bit is '1', the HWRM is requested to enable timestamp + * capture capability on the transmit side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x40) + /* + * When this bit is '1', the HWRM is requested to disable timestamp + * capture capability on the transmit side of this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE UINT32_C(0x80) + /* + * When this bit is '1', the Out-Of-Box WoL is requested to be enabled + * on this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x100) + /* + * When this bit is '1', the the Out-Of-Box WoL is requested to be + * disabled on this port. + */ + #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200) + uint32_t enables; + /* This bit must be '1' for the ipg field to be configured. */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1) + /* This bit must be '1' for the lpbk field to be configured. */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2) + /* + * This bit must be '1' for the ivlan_pri2cos_map_pri field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IVLAN_PRI2COS_MAP_PRI UINT32_C(0x4) + /* This bit must be '1' for the lcos_map_pri field to be configured. */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LCOS_MAP_PRI UINT32_C(0x8) + /* + * This bit must be '1' for the tunnel_pri2cos_map_pri field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI UINT32_C(0x10) + /* This bit must be '1' for the dscp2cos_map_pri field to be configured. */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20) + /* + * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40) + /* + * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be + * configured. + */ + #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80) + uint16_t port_id; + /* Port ID of port that is to be configured. */ + uint8_t ipg; + /* + * This value is used to configure the minimum IPG that will be sent + * between packets by this port. + */ + uint8_t lpbk; + /* This value controls the loopback setting for the MAC. */ + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that host + * data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that port + * logic will send packets back out the transmitter that are + * received. + */ + #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t ivlan_pri2cos_map_pri; + /* + * This value controls the priority of mapping. Valid values: 1-4 Higher + * the number, higher the priority + */ + uint8_t lcos_map_pri; + /* + * This value controls the priority of mapping. Valid values: 1-4 Higher + * the number, higher the priority + */ + uint8_t tunnel_pri2cos_map_pri; + /* + * This value controls the priority of mapping. Valid values: 1-4 Higher + * the number, higher the priority + */ + uint8_t dscp2pri_map_pri; + /* + * This value controls the priority of mapping. Valid values: 1-4 Higher + * the number, higher the priority + */ + uint16_t rx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that is used to request a specific + * configuration of time stamp capture of PTP messages on the receive + * side of this port. This field shall be ignored if the + * ptp_rx_ts_capture_enable flag is not set in this command. Otherwise, + * if bit 'i' is set, then the HWRM is being requested to configure the + * receive side of the port to capture the time stamp of every received + * PTP message with messageType field value set to i. + */ + uint16_t tx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that is used to request a specific + * configuration of time stamp capture of PTP messages on the transmit + * side of this port. This field shall be ignored if the + * ptp_tx_ts_capture_enable flag is not set in this command. Otherwise, + * if bit 'i' is set, then the HWRM is being requested to configure the + * transmit sied of the port to capture the time stamp of every + * transmitted PTP message with messageType field value set to i. + */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_mac_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t mru; + /* + * This is the configured maximum length of Ethernet packet payload that + * is allowed to be received on the port. This value does not include + * the number of bytes used by Ethernet header and trailer (CRC). + */ + uint16_t mtu; + /* + * This is the configured maximum length of Ethernet packet payload that + * is allowed to be transmitted on the port. This value does not include + * the number of bytes used by Ethernet header and trailer (CRC). + */ + uint8_t ipg; + /* Current configuration of the IPG value. */ + uint8_t lpbk; + /* Current value of the loopback value. */ + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that host + * data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that port + * logic will send packets back out the transmitter that are + * received. + */ + #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t unused_0; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_mac_qcfg */ +/* Description: This command queries the MAC block for the port. */ +/* Input (24 bytes) */ + +struct hwrm_port_mac_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port that is to be configured. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_port_mac_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t mru; + /* + * This is the configured maximum length of Ethernet packet payload that + * is allowed to be received on the port. This value does not include + * the number of bytes used by the Ethernet header and trailer (CRC). + */ + uint16_t mtu; + /* + * This is the configured maximum length of Ethernet packet payload that + * is allowed to be transmitted on the port. This value does not include + * the number of bytes used by the Ethernet header and trailer (CRC). + */ + uint8_t ipg; + /* The minimum IPG that will be sent between packets by this port. */ + uint8_t lpbk; + /* The loopback setting for the MAC. */ + /* No loopback is selected. Normal operation. */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0) + /* + * The HW will be configured with local loopback such that host + * data is sent back to the host without modification. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1) + /* + * The HW will be configured with remote loopback such that port + * logic will send packets back out the transmitter that are + * received. + */ + #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2) + uint8_t ivlan_pri2cos_map_pri; + /* + * Priority of pri to CoS mapping. Valid values: 1-4 Higher the number, + * higher the priority Value 0 indicates that this mapping is not used. + */ + uint8_t lcos_map_pri; + /* + * Priority of local CoS to PRI mapping. Valid values: 1-4 Higher the + * number, higher the priority Value 0 indicates that this mapping is + * not used. + */ + uint8_t tunnel_pri2cos_map_pri; + /* + * Priority of tunnel PRI to CoS mapping. Valid values: 1-4 Higher the + * number, higher the priority Value 0 indicates that this mapping is + * not used. + */ + uint8_t dscp2pri_map_pri; + /* + * Priority of DSCP to PRI mapping. Valid values: 1-4 Higher the number, + * higher the priority Value 0 indicates that this mapping is not used. + */ + uint16_t rx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that represents the current configuration + * of time stamp capture of PTP messages on the receive side of this + * port. If bit 'i' is set, then the receive side of the port is + * configured to capture the time stamp of every received PTP message + * with messageType field value set to i. If all bits are set to 0 (i.e. + * field value set 0), then the receive side of the port is not + * configured to capture timestamp for PTP messages. If all bits are set + * to 1, then the receive side of the port is configured to capture + * timestamp for all PTP messages. + */ + uint16_t tx_ts_capture_ptp_msg_type; + /* + * This is a 16-bit bit mask that represents the current configuration + * of time stamp capture of PTP messages on the transmit side of this + * port. If bit 'i' is set, then the transmit side of the port is + * configured to capture the time stamp of every received PTP message + * with messageType field value set to i. If all bits are set to 0 (i.e. + * field value set 0), then the transmit side of the port is not + * configured to capture timestamp for PTP messages. If all bits are set + * to 1, then the transmit side of the port is configured to capture + * timestamp for all PTP messages. + */ + uint8_t unused_0; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_qstats */ +/* Description: This function returns per port Ethernet statistics. */ +/* Input (40 bytes) */ + +struct hwrm_port_qstats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port that is being queried. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2[3]; + uint8_t unused_3; + uint64_t tx_stat_host_addr; + /* This is the host address where Tx port statistics will be stored */ + uint64_t rx_stat_host_addr; + /* This is the host address where Rx port statistics will be stored */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_qstats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t tx_stat_size; + /* The size of TX port statistics block in bytes. */ + uint16_t rx_stat_size; + /* The size of RX port statistics block in bytes. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_lpbk_qstats */ +/* Description: This function returns loopback statistics. */ +/* Input (16 bytes) */ + +struct hwrm_port_lpbk_qstats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (96 bytes) */ + +struct hwrm_port_lpbk_qstats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t lpbk_ucast_frames; + /* Number of transmitted unicast frames */ + uint64_t lpbk_mcast_frames; + /* Number of transmitted multicast frames */ + uint64_t lpbk_bcast_frames; + /* Number of transmitted broadcast frames */ + uint64_t lpbk_ucast_bytes; + /* Number of transmitted bytes for unicast traffic */ + uint64_t lpbk_mcast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t lpbk_bcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t tx_stat_discard; + /* Total Tx Drops for loopback traffic reported by STATS block */ + uint64_t tx_stat_error; + /* Total Tx Error Drops for loopback traffic reported by STATS block */ + uint64_t rx_stat_discard; + /* Total Rx Drops for loopback traffic reported by STATS block */ + uint64_t rx_stat_error; + /* Total Rx Error Drops for loopback traffic reported by STATS block */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_clr_stats */ +/* + * Description: This function clears per port statistics. The HWRM shall not + * allow a VF driver to clear port statistics. The HWRM shall not allow a PF + * driver to clear port statistics in a partitioning mode. The HWRM may allow a + * PF driver to clear port statistics in the non-partitioning mode. + */ +/* Input (24 bytes) */ + +struct hwrm_port_clr_stats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port that is being queried. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_clr_stats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_lpbk_clr_stats */ +/* + * Description: This function clears loopback statistics. The HWRM shall not + * allow a VF driver to clear loopback statistics. The HWRM shall not allow a PF + * driver to clear loopback statistics in a partitioning mode. The HWRM may + * allow a PF driver to clear loopback statistics in the non-partitioning mode. + */ +/* Input (16 bytes) */ + +struct hwrm_port_lpbk_clr_stats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_lpbk_clr_stats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_blink_led */ +/* + * Description: This function blinks the port LED for the specified number of + * times. + */ +/* Input (24 bytes) */ + +struct hwrm_port_blink_led_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t num_blinks; + /* Number of blinks. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_port_blink_led_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_ts_query */ +/* + * Description: This function is used to read timestamp information captured for + * PTP messages on this port. + */ +/* Input (24 bytes) */ + +struct hwrm_port_ts_query_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX + uint16_t port_id; + /* Port ID of port that is being queried. */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_port_ts_query_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t ptp_msg_ts; + /* Timestamp value of PTP message captured. */ + uint16_t ptp_msg_seqid; + /* Sequence ID of the PTP message captured. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_port_phy_qcaps */ +/* + * Description: This function is used to query the current capabilities of PHY + * on this link. + */ +/* Input (24 bytes) */ + +struct hwrm_port_phy_qcaps_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port that is being queried. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_port_phy_qcaps_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t eee_supported; + /* + * Reserved field. The HWRM shall set this field to 0. An HWRM client + * shall ignore this field. + */ + /* + * If set to 1, then this field indicates that the link is capable of + * supporting EEE. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_EEE_SUPPORTED UINT32_C(0x1) + /* + * Reserved field. The HWRM shall set this field to 0. An HWRM client + * shall ignore this field. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD1_MASK UINT32_C(0xfe) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD1_SFT 1 + uint8_t unused_0; + uint16_t supported_speeds_force_mode; + /* + * This is a bit mask to indicate what speeds are supported as forced + * speeds on this link. For each speed that can be forced on this link, + * the corresponding mask bit shall be set to '1'. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB UINT32_C(0x2000) + uint16_t supported_speeds_auto_mode; + /* + * This is a bit mask to indicate what speeds are supported for + * autonegotiation on this link. For each speed that can be + * autonegotiated on this link, the corresponding mask bit shall be set + * to '1'. + */ + /* 100Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB UINT32_C(0x2) + /* 1Gb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB UINT32_C(0x8) + /* 2Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB UINT32_C(0x10) + /* 2.5Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB UINT32_C(0x40) + /* 20Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB UINT32_C(0x80) + /* 25Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB UINT32_C(0x100) + /* 40Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB UINT32_C(0x200) + /* 50Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB UINT32_C(0x400) + /* 100Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB UINT32_C(0x800) + /* 10Mb link speed (Half-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD UINT32_C(0x1000) + /* 10Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB UINT32_C(0x2000) + uint16_t supported_speeds_eee_mode; + /* + * This is a bit mask to indicate what speeds are supported for EEE on + * this link. For each speed that can be autonegotiated when EEE is + * enabled on this link, the corresponding mask bit shall be set to '1'. + * This field is only valid when the eee_suppotred is set to '1'. + */ + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 UINT32_C(0x1) + /* 100Mb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB UINT32_C(0x2) + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 UINT32_C(0x4) + /* 1Gb link speed (Full-duplex) */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB UINT32_C(0x8) + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 UINT32_C(0x10) + /* Reserved */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 UINT32_C(0x20) + /* 10Gb link speed */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB UINT32_C(0x40) + uint32_t tx_lpi_timer_low; + /* + * Reserved field. The HWRM shall set this field to 0. An HWRM client + * shall ignore this field. + */ + /* + * The lowest value of TX LPI timer that can be set on this link when + * EEE is enabled. This value is in microseconds. This field is valid + * only when_eee_supported is set to '1'. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0 + /* + * Reserved field. The HWRM shall set this field to 0. An HWRM client + * shall ignore this field. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24 + uint32_t valid_tx_lpi_timer_high; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ + /* + * The highest value of TX LPI timer that can be set on this link when + * EEE is enabled. This value is in microseconds. This field is valid + * only when_eee_supported is set to '1'. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK UINT32_C(0xffffff) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0 + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK UINT32_C(0xff000000) + #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24 +} __attribute__((packed)); + +/* hwrm_queue_qportcfg */ +/* + * Description: This function is called by a driver to query queue configuration + * of a port. # The HWRM shall at least advertise one queue with lossy service + * profile. # The driver shall use this command to query queue ids before + * configuring or using any queues. # If a service profile is not set for a + * queue, then the driver shall not use that queue without configuring a service + * profile for it. # If the driver is not allowed to configure service profiles, + * then the driver shall only use queues for which service profiles are pre- + * configured. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_qportcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX + uint16_t port_id; + /* + * Port ID of port for which the queue configuration is being queried. + * This field is only required when sent by IPC. + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_queue_qportcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t max_configurable_queues; + /* The maximum number of queues that can be configured. */ + uint8_t max_configurable_lossless_queues; + /* The maximum number of lossless queues that can be configured. */ + uint8_t queue_cfg_allowed; + /* + * 0 - Not allowed. Non-zero - Allowed. If this value is non-zero, then + * the HWRM shall allow the host SW driver to configure queues using + * hwrm_queue_cfg. + */ + uint8_t queue_buffers_cfg_allowed; + /* + * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then + * the HWRM shall allow the host SW driver to configure queue buffers + * using hwrm_queue_buffers_cfg. + */ + uint8_t queue_pfcenable_cfg_allowed; + /* + * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then + * the HWRM shall allow the host SW driver to configure PFC using + * hwrm_queue_pfcenable_cfg. + */ + uint8_t queue_pri2cos_cfg_allowed; + /* + * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then + * the HWRM shall allow the host SW driver to configure Priority to CoS + * mapping using hwrm_queue_pri2cos_cfg. + */ + uint8_t queue_cos2bw_cfg_allowed; + /* + * 0 - Not allowed. Non-zero - Allowed If this value is non-zero, then + * the HWRM shall allow the host SW driver to configure CoS Bandwidth + * configuration using hwrm_queue_cos2bw_cfg. + */ + uint8_t queue_id0; + /* ID of CoS Queue 0. FF - Invalid id */ + uint8_t queue_id0_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id1; + /* ID of CoS Queue 1. FF - Invalid id */ + uint8_t queue_id1_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id2; + /* ID of CoS Queue 2. FF - Invalid id */ + uint8_t queue_id2_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id3; + /* ID of CoS Queue 3. FF - Invalid id */ + uint8_t queue_id3_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id4; + /* ID of CoS Queue 4. FF - Invalid id */ + uint8_t queue_id4_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id5; + /* ID of CoS Queue 5. FF - Invalid id */ + uint8_t queue_id5_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id6; + /* ID of CoS Queue 6. FF - Invalid id */ + uint8_t queue_id6_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t queue_id7; + /* ID of CoS Queue 7. FF - Invalid id */ + uint8_t queue_id7_service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_qcfg */ +/* + * Description: This function is called by a driver to query a queue + * configuration. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX + uint32_t queue_id; + /* Queue ID of the queue. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t queue_len; + /* This value is a the estimate packet length used in the TX arbiter. */ + uint8_t service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t unused_0; + uint8_t unused_1; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_cfg */ +/* Description: This function is called by a driver to configure a queue. */ +/* Input (40 bytes) */ + +struct hwrm_queue_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX + uint32_t enables; + /* This bit must be '1' for the dflt_len field to be configured. */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1) + /* This bit must be '1' for the service_profile field to be configured. */ + #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2) + uint32_t queue_id; + /* Queue ID of queue that is to be configured by this function. */ + uint32_t dflt_len; + /* + * This value is a the estimate packet length used in the TX arbiter. + * Set to 0xFF... (All Fs) to not adjust this value. + */ + uint8_t service_profile; + /* This value is applicable to CoS queues only. */ + /* Lossy (best-effort) */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0) + /* Lossless */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1) + /* Set to 0xFF... (All Fs) if there is no service profile specified */ + #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff) + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_buffers_qcfg */ +/* + * Description: This function is called by a driver to query configuration of + * the buffers assigned to a queue. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_buffers_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_BUFFERS_QCFG_INPUT_FLAGS_PATH_RX + uint32_t queue_id; + /* Queue ID of queue that is to be configured by this function. */ +} __attribute__((packed)); + +/* Output (40 bytes) */ + +struct hwrm_queue_buffers_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t reserved; + /* Number of bytes allocated as reserved space for this queue. */ + uint32_t shared; + /* + * Number of bytes of shared buffer space for this queue. The changing + * of shared buffer size for one CoS may create an adverse effect on + * other CoSs sharing the same buffer. It is recommended that the driver + * does not modify the shared mbuf size without understanding the + * consequence of it. + */ + uint32_t xoff; + /* + * XOFF threshold of the queue. This is a high threshold value used to + * trigger XOFF. + */ + uint32_t xon; + /* + * XON threshold of the queue. This is the low threshold value used to + * trigger XON. + */ + uint32_t full; + /* + * FULL threshold of the queue. At this threshold, buffers allocated for + * this queue are full. Once this condition is asserted, packets on that + * queue are dropped. + */ + uint32_t notfull; + /* + * NOTFULL threshold of the queue. This threshold is used for the de- + * assertion of buffers full condition. + */ + uint32_t max; + /* + * The maximum number of bytes that will be allowed to be consumed by + * the queue. This value is the sum of both the number of bytes reserved + * for this queue and the maximum number of bytes of shared buffers + * allowed to be consumed by this queue. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_buffers_cfg */ +/* + * Description: This function is called by a driver to configure the buffering + * for a queue. + */ +/* Input (56 bytes) */ + +struct hwrm_queue_buffers_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0) + /* rx path */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1) + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_BUFFERS_CFG_INPUT_FLAGS_PATH_RX + uint32_t enables; + /* This bit must be '1' for the reserved field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_RESERVED UINT32_C(0x1) + /* This bit must be '1' for the shared field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_SHARED UINT32_C(0x2) + /* This bit must be '1' for the xoff field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_XOFF UINT32_C(0x4) + /* This bit must be '1' for the xon field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_XON UINT32_C(0x8) + /* This bit must be '1' for the full field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_FULL UINT32_C(0x10) + /* This bit must be '1' for the notfull field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_NOTFULL UINT32_C(0x20) + /* This bit must be '1' for the max field to be configured. */ + #define HWRM_QUEUE_BUFFERS_CFG_INPUT_ENABLES_MAX UINT32_C(0x40) + uint32_t queue_id; + /* Queue ID of queue that is to be configured by this function. */ + uint32_t reserved; + /* Number of bytes to be allocated as reserved space for this queue. */ + uint32_t shared; + /* + * Number of bytes of shared buffer space for this queue. The changing + * of shared buffer size for one CoS may create an adverse effect on + * other CoSs sharing the same buffer. It is recommended that the driver + * does not modify the shared mbuf size without understanding the + * consequence of it. + */ + uint32_t xoff; + /* + * XOFF threshold of the queue. This is a high threshold value used to + * trigger XOFF. + */ + uint32_t xon; + /* + * XON threshold of the queue. This is the low threshold value used to + * trigger XON. + */ + uint32_t full; + /* + * FULL threshold of the queue. At this threshold, buffers allocated for + * this queue are full. Once this condition is asserted, packets on that + * queue are dropped. + */ + uint32_t notfull; + /* + * NOTFULL threshold of the queue. This threshold is used for the de- + * assertion of buffers full condition. + */ + uint32_t max; + /* + * The maximum number of bytes that will be allowed to be consumed by + * the queue. This value is the sum of both the number of bytes reserved + * for this queue and the maximum number of bytes of shared buffers + * allowed to be consumed by this queue. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_buffers_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_pfcenable_qcfg */ +/* + * Description: This function is called by a driver to query PFC configuration + * for different priorities on that port. This mapping can be different on + * different ports. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_pfcenable_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure pri2cos + * mapping on this port. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_pfcenable_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t flags; + /* If set to 1, then PFC is enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1) + /* If set to 1, then PFC is enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2) + /* If set to 1, then PFC is enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4) + /* If set to 1, then PFC is enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8) + /* If set to 1, then PFC is enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10) + /* If set to 1, then PFC is enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20) + /* If set to 1, then PFC is enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40) + /* If set to 1, then PFC is enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80) + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_pfcenable_cfg */ +/* + * Description: This function is called by a driver to configure the PFC enabled + * for different priorities on that port. This mapping can be different on + * different ports. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_pfcenable_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* If set to 1, then PFC is requested to be enabled on PRI 0. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1) + /* If set to 1, then PFC is requested to be enabled on PRI 1. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2) + /* If set to 1, then PFC is requested to be enabled on PRI 2. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4) + /* If set to 1, then PFC is requested to be enabled on PRI 3. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8) + /* If set to 1, then PFC is requested to be enabled on PRI 4. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10) + /* If set to 1, then PFC is requested to be enabled on PRI 5. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20) + /* If set to 1, then PFC is requested to be enabled on PRI 6. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40) + /* If set to 1, then PFC is requested to be enabled on PRI 7. */ + #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80) + uint16_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure pri2cos + * mapping on this port. + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_pfcenable_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_pri2cos_qcfg */ +/* + * Description: This function is called by a driver to query configuration of + * the priority to CoS queue mapping on the transmit side and receive side. This + * mapping can be different in each direction (TX or RX). This mapping can be + * different on different ports. Each CoS queue represents a Traffic Class (TC) + * on that port. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_pri2cos_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0) + /* rx path */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0) + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX + /* + * When this bit is set to '1', the mapping is requested for inner VLAN + * PRI. + */ + #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) + uint8_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure pri2cos + * mapping on this port. + */ + uint8_t unused_0[3]; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_queue_pri2cos_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t pri0_cos_queue_id; + /* + * CoS Queue assigned to priority 0. This value can only be changed + * before traffic has started. + */ + uint8_t pri1_cos_queue_id; + /* + * CoS Queue assigned to priority 1. This value can only be changed + * before traffic has started. + */ + uint8_t pri2_cos_queue_id; + /* + * CoS Queue assigned to priority 2 This value can only be changed + * before traffic has started. + */ + uint8_t pri3_cos_queue_id; + /* + * CoS Queue assigned to priority 3. This value can only be changed + * before traffic has started. + */ + uint8_t pri4_cos_queue_id; + /* + * CoS Queue assigned to priority 4. This value can only be changed + * before traffic has started. + */ + uint8_t pri5_cos_queue_id; + /* + * CoS Queue assigned to priority 5. This value can only be changed + * before traffic has started. + */ + uint8_t pri6_cos_queue_id; + /* + * CoS Queue assigned to priority 6. This value can only be changed + * before traffic has started. + */ + uint8_t pri7_cos_queue_id; + /* + * CoS Queue assigned to priority 7. This value can only be changed + * before traffic has started. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_pri2cos_cfg */ +/* + * Description: This function is called by a driver to configure the priority to + * CoS queue mapping on the transmit side and receive side. This mapping can be + * different in each direction (TX or RX). This mapping can be different on + * different ports. Each CoS queue represents a Traffic Class (TC) on that port. + * This command configures the VLAN PRI-to-TC mapping for a specific port in + * specific direction. + */ +/* Input (40 bytes) */ + +struct hwrm_queue_pri2cos_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0) + /* rx path */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0) + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX + /* When this bit is '1', the mapping is for inner VLAN PRI. */ + #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x2) + uint32_t enables; + uint8_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure pri2cos + * mapping on this port. + */ + uint8_t pri0_cos_queue_id; + /* + * CoS Queue assigned to priority 0. This value can only be changed + * before traffic has started. + */ + uint8_t pri1_cos_queue_id; + /* + * CoS Queue assigned to priority 1. This value can only be changed + * before traffic has started. + */ + uint8_t pri2_cos_queue_id; + /* + * CoS Queue assigned to priority 2 This value can only be changed + * before traffic has started. + */ + uint8_t pri3_cos_queue_id; + /* + * CoS Queue assigned to priority 3. This value can only be changed + * before traffic has started. + */ + uint8_t pri4_cos_queue_id; + /* + * CoS Queue assigned to priority 4. This value can only be changed + * before traffic has started. + */ + uint8_t pri5_cos_queue_id; + /* + * CoS Queue assigned to priority 5. This value can only be changed + * before traffic has started. + */ + uint8_t pri6_cos_queue_id; + /* + * CoS Queue assigned to priority 6. This value can only be changed + * before traffic has started. + */ + uint8_t pri7_cos_queue_id; + /* + * CoS Queue assigned to priority 7. This value can only be changed + * before traffic has started. + */ + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_pri2cos_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_cos2bw_qcfg */ +/* + * Description: This function is called by a driver to query the BW to CoS queue + * mapping on the transmit side of a specific port. This mapping can be + * different on different ports. Each CoS queue represents a Traffic Class (TC) + * on that port. Each traffic class can be assigned a valid combination of the + * following: - Minimum bandwidth - Maximum bandwidth - Transmission selection + * algorithm (TSA) - Priority Level (only applies to strict priority COS) - + * Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict + * priority. Is an COS min BW is set to 0x0 then it is considered to be non-SP; + * this is a valid configuration. Note: SP provides lower latency in addition to + * reserved bandwidth # For both SP CoS and non-SP CoS, min BW can be specified + * to reserve specific amount of the port BW. # The min BW specified for a CoS + * shall not exceed max port bandwidth. # The total of min BWs specified for all + * CoS shall not exceed max port bandwidth. # For any non-SP CoS, the minimum + * bandwidth guarantees are subject to round-robin scheduling. This allows BW + * reservation with anti-starvation; one CoS will not block another CoS using + * RR. Note: The bandwidth guarantees for any non-SP CoS are met after servicing + * all SP CoS. # An SP CoS can potentially starve other lower priority SP CoS + * and non-SP CoS queues. This can occur to the extent the SP min exceeds the + * available port BW. # For any CoS, max BW can be specified to limit the BW + * consumed by the CoS. # The max BW specified for a CoS shall not exceed the + * max port bandwidth. # The WFQ provides a mechanism for sharing available + * bandwidth beyond the reserved minimums configured for each CoS. The WFQ + * scheduler is used to provide the percentages of remaining bandwidth after: * + * first servicing the reserved bandwidth for all SP CoS, * followed by the + * reserved bandwidth for all non-SP CoS * All CoS may participate in the WFQ # + * If a CoS does not have a configured max BW it may use all available bandwidth + * up to the max port bandwidth Minimum Bandwidth (min BW): # This is the + * guaranteed bandwidth for the COS. # A value of 0x0 is valid and it means that + * this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means + * min BW is not specified. When the min BW is not specified, the HWRM can set + * it to any value it considers appropriate. Note: For a non-SP COS, the HWRM + * should set min BW to 0 when the min BW is not specified. For an SP COS, the + * HWRM should set min BW to some small value when the min BW is not specified. + * Maximum Bandwidth: # This is the bandwidth limit of the COS. # Values 0x0 and + * 0xFF.. (all Fs) are considered unspecified and the HWRM will set the maximum + * bandwidth to maximum port bandwidth. Priority Level: # It applies only to SP. + * # This parameter is ignored for non-SP. # 0-7 are valid values (higher value + * means higher priority) # A priority level can be assigned to at most one SP. + * # Invalid priority levels assignment for SPs shall result in failure. + * Additional notes: # The HWRM may have to use min and (max - min) to set + * appropriate counters of hardware rate limiters. # The bandwidth percentage as + * specified in the DCB TC BW assignment should be used by the driver to specify + * maximum bandwidth and bandwidth weight for a COS. For example, the driver + * should set max BW to 20 Gbps and weight to 50 for two COSs when these two + * COSs are assigned 50% share of 40 Gbps max port bandwidth. + */ +/* Input (24 bytes) */ + +struct hwrm_queue_cos2bw_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure TC BW + * assignment on this port. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (112 bytes) */ + +struct hwrm_queue_cos2bw_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t queue_id0; + /* ID of CoS Queue 0. */ + uint8_t unused_0; + uint16_t unused_1; + uint32_t queue_id0_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id0_max_bw; + /* + * Maximum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id0_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id0_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id0_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id1; + /* ID of CoS Queue 1. */ + uint32_t queue_id1_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id1_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id1_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id1_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id1_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id2; + /* ID of CoS Queue 2. */ + uint32_t queue_id2_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id2_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id2_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id2_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id2_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id3; + /* ID of CoS Queue 3. */ + uint32_t queue_id3_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id3_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id3_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id3_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id3_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id4; + /* ID of CoS Queue 4. */ + uint32_t queue_id4_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id4_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id4_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id4_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id4_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id5; + /* ID of CoS Queue 5. */ + uint32_t queue_id5_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id5_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id5_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id5_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id5_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id6; + /* ID of CoS Queue 6. */ + uint32_t queue_id6_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id6_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id6_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id6_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id6_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id7; + /* ID of CoS Queue 7. */ + uint32_t queue_id7_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id7_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id7_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id7_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id7_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t unused_5; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_queue_cos2bw_cfg */ +/* + * Description: This function is called by a driver to configure the BW to CoS + * queue mapping on the transmit side of a specific port. This mapping can be + * different on different ports. Each CoS queue represents a Traffic Class (TC) + * on that port. Each traffic class can be assigned a valid combination of the + * following: - Minimum bandwidth - Maximum bandwidth - Transmission selection + * algorithm (TSA) - Priority Level (only applies to strict priority COS) - + * Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict + * priority. Is an COS min BW is set to 0x0 then it is considered to be non-SP; + * this is a valid configuration. Note: SP provides lower latency in addition to + * reserved bandwidth # For both SP CoS and non-SP CoS, min BW can be specified + * to reserve specific amount of the port BW. # The min BW specified for a CoS + * shall not exceed max port bandwidth. # The total of min BWs specified for all + * CoS shall not exceed max port bandwidth. # For any non-SP CoS, the minimum + * bandwidth guarantees are subject to round-robin scheduling. This allows BW + * reservation with anti-starvation; one CoS will not block another CoS using + * RR. Note: The bandwidth guarantees for any non-SP CoS are met after servicing + * all SP CoS. # An SP CoS can potentially starve other lower priority SP CoS + * and non-SP CoS queues. This can occur to the extent the SP min exceeds the + * available port BW. # For any CoS, max BW can be specified to limit the BW + * consumed by the CoS. # The max BW specified for a CoS shall not exceed the + * max port bandwidth. # The WFQ provides a mechanism for sharing available + * bandwidth beyond the reserved minimums configured for each CoS. The WFQ + * scheduler is used to provide the percentages of remaining bandwidth after: - + * first servicing the reserved bandwidth for all SP CoS, - followed by the + * reserved bandwidth for all non-SP CoS - All CoS may participate in the WFQ # + * If a CoS does not have a configured max BW it may use all available bandwidth + * up to the max port bandwidth Minimum Bandwidth (min BW): # This is the + * guaranteed bandwidth for the COS. # A value of 0x0 is valid and it means that + * this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means + * min BW is not specified. When the min BW is not specified, the HWRM can set + * it to any value it considers appropriate. Note: For a non-SP COS, the HWRM + * should set min BW to 0 when the min BW is not specified. For an SP COS, the + * HWRM should set min BW to some small value when the min BW is not specified. + * Maximum Bandwidth: # This is the bandwidth limit of the COS. # Values 0x0 and + * 0xFF.. (all Fs) are considered unspecified and the HWRM will set the maximum + * bandwidth to maximum port bandwidth. Priority Level: # It applies only to SP. + * # This parameter is ignored for non-SP. # 0-7 are valid values (higher value + * means higher priority) # A priority level can be assigned to at most one SP. + * # Invalid priority levels assignment for SPs shall result in failure. + * Additional notes: # The HWRM may have to use min and (max - min) to set + * appropriate counters of hardware rate limiters. # The bandwidth percentage as + * specified in the DCB TC BW assignment should be used by the driver to specify + * maximum bandwidth and bandwidth weight for a COS. For example, the driver + * should set max BW to 20 Gbps and weight to 50 for two COSs when these two + * COSs are assigned 50% share of 40 Gbps max port bandwidth. + */ +/* Input (128 bytes) */ + +struct hwrm_queue_cos2bw_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the cos_queue_id0_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1) + /* + * This bit must be '1' for the cos_queue_id1_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2) + /* + * This bit must be '1' for the cos_queue_id2_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4) + /* + * This bit must be '1' for the cos_queue_id3_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8) + /* + * This bit must be '1' for the cos_queue_id4_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10) + /* + * This bit must be '1' for the cos_queue_id5_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20) + /* + * This bit must be '1' for the cos_queue_id6_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40) + /* + * This bit must be '1' for the cos_queue_id7_valid field to be + * configured. + */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80) + uint16_t port_id; + /* + * Port ID of port for which the table is being configured. The HWRM + * needs to check whether this function is allowed to configure TC BW + * assignment on this port. + */ + uint8_t queue_id0; + /* ID of CoS Queue 0. */ + uint8_t unused_0; + uint32_t queue_id0_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id0_max_bw; + /* + * Maximum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id0_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id0_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id0_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id1; + /* ID of CoS Queue 1. */ + uint32_t queue_id1_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id1_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id1_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id1_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id1_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id2; + /* ID of CoS Queue 2. */ + uint32_t queue_id2_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id2_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id2_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id2_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id2_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id3; + /* ID of CoS Queue 3. */ + uint32_t queue_id3_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id3_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id3_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id3_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id3_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id4; + /* ID of CoS Queue 4. */ + uint32_t queue_id4_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id4_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id4_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id4_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id4_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id5; + /* ID of CoS Queue 5. */ + uint32_t queue_id5_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id5_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id5_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id5_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id5_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id6; + /* ID of CoS Queue 6. */ + uint32_t queue_id6_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id6_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id6_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id6_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id6_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t queue_id7; + /* ID of CoS Queue 7. */ + uint32_t queue_id7_min_bw; + /* + * Minimum BW allocated to CoS Queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint32_t queue_id7_max_bw; + /* + * Maximum BW allocated to CoS queue in Mbps. The HWRM will translate + * this value into byte counter and time interval used for this COS + * inside the device. + */ + uint8_t queue_id7_tsa_assign; + /* Transmission Selection Algorithm (TSA) for CoS Queue. */ + /* Strict Priority */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0) + /* Enhanced Transmission Selection */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2) + /* reserved */ + #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff) + uint8_t queue_id7_pri_lvl; + /* + * Priority level for strict priority. Valid only when the tsa_assign is + * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved. + */ + uint8_t queue_id7_bw_weight; + /* + * Weight used to allocate remaining BW for this COS after servicing + * guaranteed bandwidths for all COS. + */ + uint8_t unused_1[5]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_queue_cos2bw_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_alloc */ +/* + * Description: This VNIC is a resource in the RX side of the chip that is used + * to represent a virtual host "interface". # At the time of VNIC allocation or + * configuration, the function can specify whether it wants the requested VNIC + * to be the default VNIC for the function or not. # If a function requests + * allocation of a VNIC for the first time and a VNIC is successfully allocated + * by the HWRM, then the HWRM shall make the allocated VNIC as the default VNIC + * for that function. # The default VNIC shall be used for the default action + * for a partition or function. # For each VNIC allocated on a function, a + * mapping on the RX side to map the allocated VNIC to source virtual interface + * shall be performed by the HWRM. This should be hidden to the function driver + * requesting the VNIC allocation. This enables broadcast/multicast replication + * with source knockout. # If multicast replication with source knockout is + * enabled, then the internal VNIC to SVIF mapping data structures shall be + * programmed at the time of VNIC allocation. + */ +/* Input (24 bytes) */ + +struct hwrm_vnic_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', this VNIC is requested to be the default VNIC + * for this function. + */ + #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t vnic_id; + /* Logical vnic ID */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_free */ +/* + * Description: Free a VNIC resource. Idle any resources associated with the + * VNIC as well as the VNIC. Reset and release all resources associated with the + * VNIC. + */ +/* Input (24 bytes) */ + +struct hwrm_vnic_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t vnic_id; + /* Logical vnic ID */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_cfg */ +/* Description: Configure the RX VNIC structure. */ +/* Input (40 bytes) */ + +struct hwrm_vnic_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', the VNIC is requested to be the default VNIC + * for the function. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is being configured to strip VLAN in + * the RX path. If set to '0', then VLAN stripping is disabled on this + * VNIC. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is being configured to buffer receive + * packets in the hardware until the host posts new receive buffers. If + * set to '0', then bd_stall is being configured to be disabled on this + * VNIC. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is being configured to receive both + * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not + * configured to be operating in dual VNIC mode. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) + /* + * When this flag is set to '1', the VNIC is requested to be configured + * to receive only RoCE traffic. If this flag is set to '0', then this + * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set + * to '1', then the HWRM client shall not set this flag to '1'. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) + /* + * When a VNIC uses one destination ring group for certain application + * (e.g. Receive Flow Steering) where exact match is used to direct + * packets to a VNIC with one destination ring group only, there is no + * need to configure RSS indirection table for that VNIC as only one + * destination ring group is used. This flag is used to enable a mode + * where RSS is enabled in the VNIC using a RSS context for computing + * RSS hash but the RSS indirection table is not configured using + * hwrm_vnic_rss_cfg. If this mode is enabled, then the driver should + * not program RSS indirection table for the RSS context that is used + * for computing RSS hash only. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) + uint32_t enables; + /* This bit must be '1' for the dflt_ring_grp field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1) + /* This bit must be '1' for the rss_rule field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2) + /* This bit must be '1' for the cos_rule field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4) + /* This bit must be '1' for the lb_rule field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8) + /* This bit must be '1' for the mru field to be configured. */ + #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10) + uint16_t vnic_id; + /* Logical vnic ID */ + uint16_t dflt_ring_grp; + /* + * Default Completion ring for the VNIC. This ring will be chosen if + * packet does not match any RSS rules and if there is no COS rule. + */ + uint16_t rss_rule; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no + * RSS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no + * COS rule. + */ + uint16_t lb_rule; + /* + * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if + * there is no LB rule. + */ + uint16_t mru; + /* + * The maximum receive unit of the vnic. Each vnic is associated with a + * function. The vnic mru value overwrites the mru setting of the + * associated function. The HWRM shall make sure that vnic mru does not + * exceed the mru of the port the function is associated with. + */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_qcfg */ +/* + * Description: Query the RX VNIC structure. This function can be used by a PF + * driver to query its own VNIC resource or VNIC resource of its child VF. This + * function can also be used by a VF driver to query its own VNIC resource. + */ +/* Input (32 bytes) */ + +struct hwrm_vnic_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the vf_id_valid field to be configured. */ + #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1) + uint32_t vnic_id; + /* Logical vnic ID */ + uint16_t vf_id; + /* ID of Virtual Function whose VNIC resource is being queried. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_vnic_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t dflt_ring_grp; + /* Default Completion ring for the VNIC. */ + uint16_t rss_rule; + /* + * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no + * RSS rule. + */ + uint16_t cos_rule; + /* + * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no + * COS rule. + */ + uint16_t lb_rule; + /* + * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if + * there is no LB rule. + */ + uint16_t mru; + /* The maximum receive unit of the vnic. */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t flags; + /* When this bit is '1', the VNIC is the default VNIC for the function. */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to strip VLAN in the RX + * path. If set to '0', then VLAN stripping is disabled on this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to buffer receive + * packets in the hardware until the host posts new receive buffers. If + * set to '0', then bd_stall is disabled on this VNIC. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to receive both RoCE and + * non-RoCE traffic. If set to '0', then this VNIC is not configured to + * operate in dual VNIC mode. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8) + /* + * When this flag is set to '1', the VNIC is configured to receive only + * RoCE traffic. When this flag is set to '0', the VNIC is not + * configured to receive only RoCE traffic. If roce_dual_vnic_mode flag + * and this flag both are set to '1', then it is an invalid + * configuration of the VNIC. The HWRM should not allow that type of + * mis-configuration by HWRM clients. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10) + /* + * When a VNIC uses one destination ring group for certain application + * (e.g. Receive Flow Steering) where exact match is used to direct + * packets to a VNIC with one destination ring group only, there is no + * need to configure RSS indirection table for that VNIC as only one + * destination ring group is used. When this bit is set to '1', then the + * VNIC is enabled in a mode where RSS is enabled in the VNIC using a + * RSS context for computing RSS hash but the RSS indirection table is + * not configured. + */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20) + uint32_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t unused_5; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_qcaps */ +/* + * Description: This function is used to query the capabilities of VNIC + * resources. + */ +/* Input (24 bytes) */ + +struct hwrm_vnic_qcaps_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_vnic_qcaps_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t mru; + /* The maximum receive unit that is settable on a vnic. */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t flags; + /* Unused. */ + /* + * When this bit is '1', the capability of stripping VLAN in the RX path + * is supported on VNIC(s). If set to '0', then VLAN stripping + * capability is not supported on VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2) + /* + * When this bit is '1', the capability to buffer receive packets in the + * hardware until the host posts new receive buffers is supported on + * VNIC(s). If set to '0', then bd_stall capability is not supported on + * VNIC(s). + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4) + /* + * When this bit is '1', the capability to receive both RoCE and non- + * RoCE traffic on VNIC(s) is supported. If set to '0', then the + * capability to receive both RoCE and non-RoCE traffic on VNIC(s) is + * not supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8) + /* + * When this bit is set to '1', the capability to configure a VNIC to + * receive only RoCE traffic is supported. When this flag is set to '0', + * the VNIC capability to configure to receive only RoCE traffic is not + * supported. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10) + /* + * When this bit is set to '1', then the capability to enable a VNIC in + * a mode where RSS context without configuring RSS indirection table is + * supported (for RSS hash computation). When this bit is set to '0', + * then a VNIC can not be configured with a mode to enable RSS context + * without configuring RSS indirection table. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20) + uint32_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t unused_5; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_tpa_cfg */ +/* Description: This function is used to enable/configure TPA on the VNIC. */ +/* Input (40 bytes) */ + +struct hwrm_vnic_tpa_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) of non-tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1) + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) of tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) according to Windows Receive + * Segment Coalescing (RSC) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) according to Linux Generic + * Receive Offload (GRO) rules. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8) + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) for TCP packets with IP ECN set + * to non-zero. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) + /* + * When this bit is '1', the VNIC shall be configured to perform + * transparent packet aggregation (TPA) for GRE tunneled TCP packets + * only if all packets have the same GRE sequence. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) + /* + * When this bit is '1' and the GRO mode is enabled, the VNIC shall be + * configured to perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. In other words, + * the last packet that is being aggregated to an already existing + * aggregation context shall have IPID 1 more than the IPID of the last + * packet that was aggregated in that aggregation context. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) + /* + * When this bit is '1' and the GRO mode is enabled, the VNIC shall be + * configured to perform transparent packet aggregation (TPA) for TCP + * packets with the same TTL (IPv4) or Hop limit (IPv6) value. + */ + #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) + uint32_t enables; + /* This bit must be '1' for the max_agg_segs field to be configured. */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1) + /* This bit must be '1' for the max_aggs field to be configured. */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2) + /* This bit must be '1' for the max_agg_timer field to be configured. */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4) + /* This bit must be '1' for the min_agg_len field to be configured. */ + #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8) + uint16_t vnic_id; + /* Logical vnic ID */ + uint16_t max_agg_segs; + /* + * This is the maximum number of TCP segments that can be aggregated + * (unit is Log2). Max value is 31. + */ + /* 1 segment */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + uint16_t max_aggs; + /* + * This is the maximum number of aggregations this VNIC is allowed (unit + * is Log2). Max value is 7 + */ + /* 1 aggregation */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7) + uint8_t unused_0; + uint8_t unused_1; + uint32_t max_agg_timer; + /* + * This is the maximum amount of time allowed for an aggregation context + * to complete after it was initiated. + */ + uint32_t min_agg_len; + /* + * This is the minimum amount of payload length required to start an + * aggregation context. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_tpa_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_tpa_qcfg */ +/* + * Description: This function can be used to query TPA configuration on the + * VNIC. + */ +/* Input (24 bytes) */ + +struct hwrm_vnic_tpa_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t vnic_id; + /* Logical vnic ID */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_vnic_tpa_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t flags; + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) of non-tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) of tunneled TCP packets. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) according to Windows Receive Segment + * Coalescing (RSC) rules. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) according to Linux Generic Receive Offload + * (GRO) rules. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8) + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) for TCP packets with IP ECN set to non-zero. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10) + /* + * When this bit is '1', the VNIC is configured to perform transparent + * packet aggregation (TPA) for GRE tunneled TCP packets only if all + * packets have the same GRE sequence. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20) + /* + * When this bit is '1' and the GRO mode is enabled, the VNIC is + * configured to perform transparent packet aggregation (TPA) for + * TCP/IPv4 packets with consecutively increasing IPIDs. In other words, + * the last packet that is being aggregated to an already existing + * aggregation context shall have IPID 1 more than the IPID of the last + * packet that was aggregated in that aggregation context. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40) + /* + * When this bit is '1' and the GRO mode is enabled, the VNIC is + * configured to perform transparent packet aggregation (TPA) for TCP + * packets with the same TTL (IPv4) or Hop limit (IPv6) value. + */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80) + uint16_t max_agg_segs; + /* + * This is the maximum number of TCP segments that can be aggregated + * (unit is Log2). Max value is 31. + */ + /* 1 segment */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0) + /* 2 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1) + /* 4 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2) + /* 8 segments */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3) + /* Any segment size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f) + uint16_t max_aggs; + /* + * This is the maximum number of aggregations this VNIC is allowed (unit + * is Log2). Max value is 7 + */ + /* 1 aggregation */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0) + /* 2 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1) + /* 4 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2) + /* 8 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3) + /* 16 aggregations */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4) + /* Any aggregation size larger than this is not valid */ + #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7) + uint32_t max_agg_timer; + /* + * This is the maximum amount of time allowed for an aggregation context + * to complete after it was initiated. + */ + uint32_t min_agg_len; + /* + * This is the minimum amount of payload length required to start an + * aggregation context. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_rss_cfg */ +/* Description: This function is used to enable RSS configuration. */ +/* Input (48 bytes) */ + +struct hwrm_vnic_rss_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed over source and + * destination IPv4 addresses of IPv4 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and source/destination ports of + * TCP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and source/destination ports of + * UDP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed over source and + * destination IPv4 addresses of IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and source/destination ports of + * TCP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and source/destination ports of + * UDP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint32_t unused_0; + uint64_t ring_grp_tbl_addr; + /* This is the address for rss ring group table */ + uint64_t hash_key_tbl_addr; + /* This is the address for rss hash key table */ + uint16_t rss_ctx_idx; + /* Index to the rss indirection table. */ + uint16_t unused_1[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_rss_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_rss_qcfg */ +/* Description: This function is used to query RSS context configuration. */ +/* Input (24 bytes) */ + +struct hwrm_vnic_rss_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t rss_ctx_idx; + /* Index to the rss indirection table. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (64 bytes) */ + +struct hwrm_vnic_rss_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t hash_type; + /* + * When this bit is '1', the RSS hash shall be computed over source and + * destination IPv4 addresses of IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and source/destination ports of + * TCP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and source/destination ports of + * UDP/IPv4 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the RSS hash shall be computed over source and + * destination IPv4 addresses of IPv6 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and source/destination ports of + * TCP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and source/destination ports of + * UDP/IPv6 packets. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + uint32_t unused_0; + uint32_t hash_key[10]; + /* This is the value of rss hash key */ + uint32_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_plcmodes_cfg */ +/* + * Description: This function can be used to set placement mode configuration of + * the VNIC. + */ +/* Input (40 bytes) */ + +struct hwrm_vnic_plcmodes_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * When this bit is '1', the VNIC shall be configured to use regular + * placement algorithm. By default, the regular placement algorithm + * shall be enabled on the VNIC. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) + /* + * When this bit is '1', the VNIC shall be configured use the jumbo + * placement algorithm. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) + /* + * When this bit is '1', the VNIC shall be configured to enable Header- + * Data split for IPv4 packets according to the following rules: # If + * the packet is identified as TCP/IPv4, then the packet is split at the + * beginning of the TCP payload. # If the packet is identified as + * UDP/IPv4, then the packet is split at the beginning of UDP payload. # + * If the packet is identified as non-TCP and non-UDP IPv4 packet, then + * the packet is split at the beginning of the upper layer protocol + * header carried in the IPv4 packet. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the VNIC shall be configured to enable Header- + * Data split for IPv6 packets according to the following rules: # If + * the packet is identified as TCP/IPv6, then the packet is split at the + * beginning of the TCP payload. # If the packet is identified as + * UDP/IPv6, then the packet is split at the beginning of UDP payload. # + * If the packet is identified as non-TCP and non-UDP IPv6 packet, then + * the packet is split at the beginning of the upper layer protocol + * header carried in the IPv6 packet. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the VNIC shall be configured to enable Header- + * Data split for FCoE packets at the beginning of FC payload. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10) + /* + * When this bit is '1', the VNIC shall be configured to enable Header- + * Data split for RoCE packets at the beginning of RoCE payload (after + * BTH/GRH headers). + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20) + uint32_t enables; + /* + * This bit must be '1' for the jumbo_thresh_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1) + /* This bit must be '1' for the hds_offset_valid field to be configured. */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2) + /* + * This bit must be '1' for the hds_threshold_valid field to be + * configured. + */ + #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4) + uint32_t vnic_id; + /* Logical vnic ID */ + uint16_t jumbo_thresh; + /* + * When jumbo placement algorithm is enabled, this value is used to + * determine the threshold for jumbo placement. Packets with length + * larger than this value will be placed according to the jumbo + * placement algorithm. + */ + uint16_t hds_offset; + /* + * This value is used to determine the offset into packet buffer where + * the split data (payload) will be placed according to one of of HDS + * placement algorithm. The lengths of packet buffers provided for split + * data shall be larger than this value. + */ + uint16_t hds_threshold; + /* + * When one of the HDS placement algorithm is enabled, this value is + * used to determine the threshold for HDS placement. Packets with + * length larger than this value will be placed according to the HDS + * placement algorithm. This value shall be in multiple of 4 bytes. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_plcmodes_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_plcmodes_qcfg */ +/* + * Description: This function can be used to query placement mode configuration + * of the VNIC. + */ +/* Input (24 bytes) */ + +struct hwrm_vnic_plcmodes_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t vnic_id; + /* Logical vnic ID */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_vnic_plcmodes_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t flags; + /* + * When this bit is '1', the VNIC is configured to use regular placement + * algorithm. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1) + /* + * When this bit is '1', the VNIC is configured to use the jumbo + * placement algorithm. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2) + /* + * When this bit is '1', the VNIC is configured to enable Header-Data + * split for IPv4 packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4) + /* + * When this bit is '1', the VNIC is configured to enable Header-Data + * split for IPv6 packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8) + /* + * When this bit is '1', the VNIC is configured to enable Header-Data + * split for FCoE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10) + /* + * When this bit is '1', the VNIC is configured to enable Header-Data + * split for RoCE packets. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20) + /* + * When this bit is '1', the VNIC is configured to be the default VNIC + * of the requesting function. + */ + #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40) + uint16_t jumbo_thresh; + /* + * When jumbo placement algorithm is enabled, this value is used to + * determine the threshold for jumbo placement. Packets with length + * larger than this value will be placed according to the jumbo + * placement algorithm. + */ + uint16_t hds_offset; + /* + * This value is used to determine the offset into packet buffer where + * the split data (payload) will be placed according to one of of HDS + * placement algorithm. The lengths of packet buffers provided for split + * data shall be larger than this value. + */ + uint16_t hds_threshold; + /* + * When one of the HDS placement algorithm is enabled, this value is + * used to determine the threshold for HDS placement. Packets with + * length larger than this value will be placed according to the HDS + * placement algorithm. This value shall be in multiple of 4 bytes. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_rss_cos_lb_ctx_alloc */ +/* Description: This function is used to allocate COS/Load Balance context. */ +/* Input (16 bytes) */ + +struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t rss_cos_lb_ctx_id; + /* rss_cos_lb_ctx_id is 16 b */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_vnic_rss_cos_lb_ctx_free */ +/* Description: This function can be used to free COS/Load Balance context. */ +/* Input (24 bytes) */ + +struct hwrm_vnic_rss_cos_lb_ctx_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t rss_cos_lb_ctx_id; + /* rss_cos_lb_ctx_id is 16 b */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_vnic_rss_cos_lb_ctx_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_alloc */ +/* + * Description: This command allocates and does basic preparation for a ring. + */ +/* Input (80 bytes) */ + +struct hwrm_ring_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the Reserved1 field to be configured. */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1) + /* This bit must be '1' for the Reserved2 field to be configured. */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED2 UINT32_C(0x2) + /* This bit must be '1' for the Reserved3 field to be configured. */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4) + /* + * This bit must be '1' for the stat_ctx_id_valid field to be + * configured. + */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8) + /* This bit must be '1' for the Reserved4 field to be configured. */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4 UINT32_C(0x10) + /* This bit must be '1' for the max_bw_valid field to be configured. */ + #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20) + uint8_t ring_type; + /* Ring Type. */ + /* Completion Ring (CR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2) + uint8_t unused_0; + uint16_t unused_1; + uint64_t page_tbl_addr; + /* This value is a pointer to the page table for the Ring. */ + uint32_t fbo; + /* First Byte Offset of the first entry in the first page. */ + uint8_t page_size; + /* + * Actual page size in 2^page_size. The supported range is increments in + * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12 + * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB + * Page size is 64 KB. - 21 = 2 MB Page size is 2 MB. - 22 = 4 MB Page + * size is 4 MB. - 30 = 1 GB Page size is 1 GB. + */ + uint8_t page_tbl_depth; + /* + * This value indicates the depth of page table. For this version of the + * specification, value other than 0 or 1 shall be considered as an + * invalid value. When the page_tbl_depth = 0, then it is treated as a + * special case with the following. 1. FBO and page size fields are not + * valid. 2. page_tbl_addr is the physical address of the first element + * of the ring. + */ + uint8_t unused_2; + uint8_t unused_3; + uint32_t length; + /* + * Number of 16B units in the ring. Minimum size for a ring is 16 16B + * entries. + */ + uint16_t logical_id; + /* + * Logical ring number for the ring to be allocated. This value + * determines the position in the doorbell area where the update to the + * ring will be made. For completion rings, this value is also the MSI-X + * vector number for the function the completion ring is associated + * with. + */ + uint16_t cmpl_ring_id; + /* + * This field is used only when ring_type is a TX ring. This value + * indicates what completion ring the TX ring is associated with. + */ + uint16_t queue_id; + /* + * This field is used only when ring_type is a TX ring. This value + * indicates what CoS queue the TX ring is associated with. + */ + uint8_t unused_4; + uint8_t unused_5; + uint32_t reserved1; + /* This field is reserved for the future use. It shall be set to 0. */ + uint16_t reserved2; + /* This field is reserved for the future use. It shall be set to 0. */ + uint8_t unused_6; + uint8_t unused_7; + uint32_t reserved3; + /* This field is reserved for the future use. It shall be set to 0. */ + uint32_t stat_ctx_id; + /* + * This field is used only when ring_type is a TX ring. This input + * indicates what statistics context this ring should be associated + * with. + */ + uint32_t reserved4; + /* This field is reserved for the future use. It shall be set to 0. */ + uint32_t max_bw; + /* + * This field is used only when ring_type is a TX ring. Maximum BW + * allocated to this TX ring in Mbps. The HWRM will translate this value + * into byte counter and time interval used for this ring inside the + * device. + */ + uint8_t int_mode; + /* + * This field is used only when ring_type is a Completion ring. This + * value indicates what interrupt mode should be used on this completion + * ring. Note: In the legacy interrupt mode, no more than 16 completion + * rings are allowed. + */ + /* Legacy INTA */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) + /* Reserved */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) + /* MSI-X */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2) + /* No Interrupt - Polled mode */ + #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3) + uint8_t unused_8[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t ring_id; + /* Physical number of ring allocated. */ + uint16_t logical_ring_id; + /* Logical number of ring allocated. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_free */ +/* + * Description: This command is used to free a ring and associated resources. + */ +/* Input (24 bytes) */ + +struct hwrm_ring_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t ring_type; + /* Ring Type. */ + /* Completion Ring (CR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2) + uint8_t unused_0; + uint16_t ring_id; + /* Physical number of ring allocated. */ + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_cmpl_ring_qaggint_params */ +/* + * Description: This command is used to query aggregation and interrupt related + * parameters specified on a given completion ring. + */ +/* Input (24 bytes) */ + +struct hwrm_ring_cmpl_ring_qaggint_params_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t ring_id; + /* Physical number of completion ring. */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_ring_cmpl_ring_qaggint_params_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t flags; + /* + * When this bit is set to '1', interrupt max timer is reset whenever a + * completion is received. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode aggregation will be + * enabled. + */ + #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2) + uint16_t num_cmpl_dma_aggr; + /* Number of completions to aggregate before DMA during the normal mode. */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Number of completions to aggregate before DMA during the interrupt + * mode. + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer in unit of 80-nsec used to aggregate completions before DMA + * during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* + * Timer in unit of 80-nsec used to aggregate completions before DMA + * during the interrupt mode. + */ + uint16_t int_lat_tmr_min; + /* Minimum time (in unit of 80-nsec) between two interrupts. */ + uint16_t int_lat_tmr_max; + /* + * Maximum wait time (in unit of 80-nsec) spent aggregating completions + * before signaling the interrupt after the interrupt is enabled. + */ + uint16_t num_cmpl_aggr_int; + /* + * Minimum number of completions aggregated before signaling an + * interrupt. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_cmpl_ring_cfg_aggint_params */ +/* + * Description: This command is used to configure aggregation and interrupt + * related parameters specified on a given completion ring. + */ +/* Input (40 bytes) */ + +struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t ring_id; + /* Physical number of completion ring. */ + uint16_t flags; + /* + * When this bit is set to '1', interrupt latency max timer is reset + * whenever a completion is received. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1) + /* + * When this bit is set to '1', ring idle mode aggregation will be + * enabled. + */ + #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2) + uint16_t num_cmpl_dma_aggr; + /* Number of completions to aggregate before DMA during the normal mode. */ + uint16_t num_cmpl_dma_aggr_during_int; + /* + * Number of completions to aggregate before DMA during the interrupt + * mode. + */ + uint16_t cmpl_aggr_dma_tmr; + /* + * Timer in unit of 80-nsec used to aggregate completions before DMA + * during the normal mode (not in interrupt mode). + */ + uint16_t cmpl_aggr_dma_tmr_during_int; + /* + * Timer in unit of 80-nsec used to aggregate completions before DMA + * during the interrupt mode. + */ + uint16_t int_lat_tmr_min; + /* Minimum time (in unit of 80-nsec) between two interrupts. */ + uint16_t int_lat_tmr_max; + /* + * Maximum wait time (in unit of 80-nsec) spent aggregating cmpls before + * signaling the interrupt after the interrupt is enabled. + */ + uint16_t num_cmpl_aggr_int; + /* + * Minimum number of completions aggregated before signaling an + * interrupt. + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_reset */ +/* + * Description: This command is used to reset a given ring. When an RX ring is + * being reset, the HWRM shall perform TPA flush on all VNICs associated with + * the RX ring that is being reset. + */ +/* Input (24 bytes) */ + +struct hwrm_ring_reset_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t ring_type; + /* Ring Type. */ + /* Completion Ring (CR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_CMPL UINT32_C(0x0) + /* TX Ring (TR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1) + /* RX Ring (RR) */ + #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2) + uint8_t unused_0; + uint16_t ring_id; + /* Physical number of the ring. */ + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_reset_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_grp_alloc */ +/* + * Description: This API allocates and does basic preparation for a ring group. + */ +/* Input (24 bytes) */ + +struct hwrm_ring_grp_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t cr; + /* This value identifies the CR associated with the ring group. */ + uint16_t rr; + /* This value identifies the main RR associated with the ring group. */ + uint16_t ar; + /* + * This value identifies the aggregation RR associated with the ring + * group. If this value is 0xFF... (All Fs), then no Aggregation ring + * will be set. + */ + uint16_t sc; + /* + * This value identifies the statistics context associated with the ring + * group. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_grp_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t ring_group_id; + /* + * This is the ring group ID value. Use this value to program the + * default ring group for the VNIC or as table entries in an RSS/COS + * context. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_ring_grp_free */ +/* + * Description: This API frees a ring group and associated resources. # If a + * ring in the ring group is reset or free, then the associated rings in the + * ring group shall also be reset/free using hwrm_ring_free. # A function driver + * shall always use hwrm_ring_grp_free after freeing all rings in a group. # As + * a part of executing this command, the HWRM shall reset all associated ring + * group resources. + */ +/* Input (24 bytes) */ + +struct hwrm_ring_grp_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t ring_group_id; + /* This is the ring group ID value. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_ring_grp_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_alloc */ +/* + * Description: An L2 filter is a filter resource that is used to identify a + * vnic or ring for a packet based on layer 2 fields. Layer 2 fields for + * encapsulated packets include both outer L2 header and/or inner l2 header of + * encapsulated packet. The L2 filter resource covers the following OS specific + * L2 filters. Linux/FreeBSD (per function): # Broadcast enable/disable # List + * of individual multicast filters # All multicast enable/disable filter # + * Unicast filters # Promiscuous mode VMware: # Broadcast enable/disable (per + * physical function) # All multicast enable/disable (per function) # Unicast + * filters per ring or vnic # Promiscuous mode per PF Windows: # Broadcast + * enable/disable (per physical function) # List of individual multicast filters + * (Driver needs to advertise the maximum number of filters supported) # All + * multicast enable/disable per physical function # Unicast filters per vnic # + * Promiscuous mode per PF Implementation notes on the use of VNIC in this + * command: # By default, these filters belong to default vnic for the function. + * # Once these filters are set up, only destination VNIC can be modified. # If + * the destination VNIC is not specified in this command, then the HWRM shall + * only create an l2 context id. HWRM Implementation notes for multicast + * filters: # The hwrm_filter_alloc command can be used to set up multicast + * filters (perfect match or partial match). Each individual function driver can + * set up multicast filters independently. # The HWRM needs to keep track of + * multicast filters set up by function drivers and maintain multicast group + * replication records to enable a subset of functions to receive traffic for a + * specific multicast address. # When a specific multicast filter cannot be set, + * the HWRM shall return an error. In this error case, the driver should fall + * back to using one general filter (rather than specific) for all multicast + * traffic. # When the SR-IOV is enabled, the HWRM needs to additionally track + * source knockout per multicast group record. Examples of setting unicast + * filters: For a unicast MAC based filter, one can use a combination of the + * fields and masks provided in this command to set up the filter. Below are + * some examples: # MAC + no VLAN filter: This filter is used to identify + * traffic that does not contain any VLAN tags and matches destination (or + * source) MAC address. This filter can be set up by setting only l2_addr field + * to be a valid field. All other fields are not valid. The following value is + * set for l2_addr. l2_addr = MAC # MAC + Any VLAN filter: This filter is used + * to identify traffic that carries single VLAN tag and matches (destination or + * source) MAC address. This filter can be set up by setting only l2_addr and + * l2_ovlan_mask fields to be valid fields. All other fields are not valid. The + * following values are set for those two valid fields. l2_addr = MAC, + * l2_ovlan_mask = 0xFFFF # MAC + no VLAN or VLAN ID=0: This filter is used to + * identify untagged traffic that does not contain any VLAN tags or a VLAN tag + * with VLAN ID = 0 and matches destination (or source) MAC address. This filter + * can be set up by setting only l2_addr and l2_ovlan fields to be valid fields. + * All other fields are not valid. The following value are set for l2_addr and + * l2_ovlan. l2_addr = MAC, l2_ovlan = 0x0 # MAC + no VLAN or any VLAN: This + * filter is used to identify traffic that contains zero or 1 VLAN tag and + * matches destination (or source) MAC address. This filter can be set up by + * setting only l2_addr, l2_ovlan, and l2_mask fields to be valid fields. All + * other fields are not valid. The following value are set for l2_addr, + * l2_ovlan, and l2_mask fields. l2_addr = MAC, l2_ovlan = 0x0, l2_ovlan_mask = + * 0xFFFF # MAC + VLAN ID filter: This filter can be set up by setting only + * l2_addr, l2_ovlan, and l2_ovlan_mask fields to be valid fields. All other + * fields are not valid. The following values are set for those three valid + * fields. l2_addr = MAC, l2_ovlan = VLAN ID, l2_ovlan_mask = 0xF000 + */ +/* Input (96 bytes) */ + +struct hwrm_cfa_l2_filter_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0) + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4) + /* + * If this flag is set, all t_l2_* fields are invalid and they should + * not be specified. If this flag is set, then l2_* fields refer to + * fields of outermost L2 header. + */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8) + uint32_t enables; + /* This bit must be '1' for the l2_addr field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1) + /* This bit must be '1' for the l2_addr_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2) + /* This bit must be '1' for the l2_ovlan field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4) + /* This bit must be '1' for the l2_ovlan_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8) + /* This bit must be '1' for the l2_ivlan field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10) + /* This bit must be '1' for the l2_ivlan_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20) + /* This bit must be '1' for the t_l2_addr field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40) + /* This bit must be '1' for the t_l2_addr_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80) + /* This bit must be '1' for the t_l2_ovlan field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100) + /* This bit must be '1' for the t_l2_ovlan_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200) + /* This bit must be '1' for the t_l2_ivlan field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400) + /* This bit must be '1' for the t_l2_ivlan_mask field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800) + /* This bit must be '1' for the src_type field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000) + /* This bit must be '1' for the src_id field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000) + /* This bit must be '1' for the tunnel_type field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000) + /* This bit must be '1' for the dst_id field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000) + /* This bit must be '1' for the mirror_vnic_id field to be configured. */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000) + uint8_t l2_addr[6]; + /* + * This value sets the match value for the L2 MAC address. Destination + * MAC address for RX path. Source MAC address for TX path. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t l2_addr_mask[6]; + /* + * This value sets the mask value for the L2 address. A value of 0 will + * mask the corresponding bit from compare. + */ + uint16_t l2_ovlan; + /* This value sets VLAN ID value for outer VLAN. */ + uint16_t l2_ovlan_mask; + /* + * This value sets the mask value for the ovlan id. A value of 0 will + * mask the corresponding bit from compare. + */ + uint16_t l2_ivlan; + /* This value sets VLAN ID value for inner VLAN. */ + uint16_t l2_ivlan_mask; + /* + * This value sets the mask value for the ivlan id. A value of 0 will + * mask the corresponding bit from compare. + */ + uint8_t unused_2; + uint8_t unused_3; + uint8_t t_l2_addr[6]; + /* + * This value sets the match value for the tunnel L2 MAC address. + * Destination MAC address for RX path. Source MAC address for TX path. + */ + uint8_t unused_4; + uint8_t unused_5; + uint8_t t_l2_addr_mask[6]; + /* + * This value sets the mask value for the tunnel L2 address. A value of + * 0 will mask the corresponding bit from compare. + */ + uint16_t t_l2_ovlan; + /* This value sets VLAN ID value for tunnel outer VLAN. */ + uint16_t t_l2_ovlan_mask; + /* + * This value sets the mask value for the tunnel ovlan id. A value of 0 + * will mask the corresponding bit from compare. + */ + uint16_t t_l2_ivlan; + /* This value sets VLAN ID value for tunnel inner VLAN. */ + uint16_t t_l2_ivlan_mask; + /* + * This value sets the mask value for the tunnel ivlan id. A value of 0 + * will mask the corresponding bit from compare. + */ + uint8_t src_type; + /* This value identifies the type of source of the packet. */ + /* Network port */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0) + /* Physical function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1) + /* Virtual function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2) + /* Virtual NIC of a function */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3) + /* Embedded processor for CFA management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4) + /* Embedded processor for OOB management */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5) + /* Embedded processor for RoCE */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6) + /* Embedded processor for network proxy functions */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7) + uint8_t unused_6; + uint32_t src_id; + /* + * This value is the id of the source. For a network port, it represents + * port_id. For a physical function, it represents fid. For a virtual + * function, it represents vf_id. For a vnic, it represents vnic_id. For + * embedded processors, this id is not valid. Notes: 1. The function ID + * is implied if it src_id is not provided for a src_type that is either + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Non-tunnel */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* Any tunneled traffic */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + uint8_t unused_7; + uint16_t dst_id; + /* + * If set, this value shall represent the Logical VNIC ID of the + * destination VNIC for the RX path and network port id of the + * destination port for the TX path. + */ + uint16_t mirror_vnic_id; + /* Logical VNIC ID of the VNIC where traffic is mirrored. */ + uint8_t pri_hint; + /* + * This hint is provided to help in placing the filter in the filter + * table. + */ + /* No preference */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4) + uint8_t unused_8; + uint32_t unused_9; + uint64_t l2_filter_id_hint; + /* + * This is the ID of the filter that goes along with the pri_hint. This + * field is valid only for the following values. 1 - Above the given + * filter 2 - Below the given filter + */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_cfa_l2_filter_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint32_t flow_id; + /* + * This is the ID of the flow associated with this filter. This value + * shall be used to match and associate the flow identifier returned in + * completion records. A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_free */ +/* + * Description: Free a L2 filter. The HWRM shall free all associated filter + * resources with the L2 filter. + */ +/* Input (24 bytes) */ + +struct hwrm_cfa_l2_filter_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_l2_filter_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_l2_filter_cfg */ +/* Description: Change the configuration of an existing L2 filter */ +/* Input (40 bytes) */ + +struct hwrm_cfa_l2_filter_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0) + /* rx path */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0) + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2) + uint32_t enables; + /* This bit must be '1' for the dst_id field to be configured. */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint32_t dst_id; + /* + * If set, this value shall represent the Logical VNIC ID of the + * destination VNIC for the RX path and network port id of the + * destination port for the TX path. + */ + uint32_t new_mirror_vnic_id; + /* New Logical VNIC ID of the VNIC where traffic is mirrored. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_l2_filter_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_l2_set_rx_mask */ +/* Description: This command will set rx mask of the function. */ +/* Input (56 bytes) */ + +struct hwrm_cfa_l2_set_rx_mask_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t vnic_id; + /* VNIC ID */ + uint32_t mask; + /* Reserved for future use. */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_RESERVED UINT32_C(0x1) + /* + * When this bit is '1', the function is requested to accept multi-cast + * packets specified by the multicast addr table. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2) + /* + * When this bit is '1', the function is requested to accept all multi- + * cast packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4) + /* + * When this bit is '1', the function is requested to accept broadcast + * packets. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8) + /* + * When this bit is '1', the function is requested to be put in the + * promiscuous mode. The HWRM should accept any function to set up + * promiscuous mode. The HWRM shall follow the semantics below for the + * promiscuous mode support. # When partitioning is not enabled on a + * port (i.e. single PF on the port), then the PF shall be allowed to be + * in the promiscuous mode. When the PF is in the promiscuous mode, then + * it shall receive all host bound traffic on that port. # When + * partitioning is enabled on a port (i.e. multiple PFs per port) and a + * PF on that port is in the promiscuous mode, then the PF receives all + * traffic within that partition as identified by a unique identifier + * for the PF (e.g. S-Tag). If a unique outer VLAN for the PF is + * specified, then the setting of promiscuous mode on that PF shall + * result in the PF receiving all host bound traffic with matching outer + * VLAN. # A VF shall can be set in the promiscuous mode. In the + * promiscuous mode, the VF does not receive any traffic unless a unique + * outer VLAN for the VF is specified. If a unique outer VLAN for the VF + * is specified, then the setting of promiscuous mode on that VF shall + * result in the VF receiving all host bound traffic with the matching + * outer VLAN. # The HWRM shall allow the setting of promiscuous mode on + * a function independently from the promiscuous mode settings on other + * functions. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10) + /* + * If this flag is set, the corresponding RX filters shall be set up to + * cover multicast/broadcast filters for the outermost Layer 2 + * destination MAC address field. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20) + /* + * If this flag is set, the corresponding RX filters shall be set up to + * cover multicast/broadcast filters for the VLAN-tagged packets that + * match the TPID and VID fields of VLAN tags in the VLAN tag table + * specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40) + /* + * If this flag is set, the corresponding RX filters shall be set up to + * cover multicast/broadcast filters for non-VLAN tagged packets and + * VLAN-tagged packets that match the TPID and VID fields of VLAN tags + * in the VLAN tag table specified in this command. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80) + /* + * If this flag is set, the corresponding RX filters shall be set up to + * cover multicast/broadcast filters for non-VLAN tagged packets and + * VLAN-tagged packets matching any VLAN tag. If this flag is set, then + * the HWRM shall ignore VLAN tags specified in vlan_tag_tbl. If none of + * vlanonly, vlan_nonvlan, and anyvlan_nonvlan flags is set, then the + * HWRM shall ignore VLAN tags specified in vlan_tag_tbl. The HWRM + * client shall set at most one flag out of vlanonly, vlan_nonvlan, and + * anyvlan_nonvlan. + */ + #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100) + uint64_t mc_tbl_addr; + /* This is the address for mcast address tbl. */ + uint32_t num_mc_entries; + /* + * This value indicates how many entries in mc_tbl are valid. Each entry + * is 6 bytes. + */ + uint32_t unused_0; + uint64_t vlan_tag_tbl_addr; + /* + * This is the address for VLAN tag table. Each VLAN entry in the table + * is 4 bytes of a VLAN tag including TPID, PCP, DEI, and VID fields in + * network byte order. + */ + uint32_t num_vlan_tags; + /* + * This value indicates how many entries in vlan_tag_tbl are valid. Each + * entry is 4 bytes. + */ + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_l2_set_rx_mask_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_tunnel_filter_alloc */ +/* + * Description: This is a tunnel filter that uses fields from tunnel header in + * addition to l2 context. The tunnel filter applies to receive side only. The + * l2_* fields in this command represent fields of inner L2 header. They are + * optional to be specified. It allows l2_filter_id to be created with outer L2 + * header fields that can be shared with multiple tunnel filters specified as + * combinations of inner L2 header fields, tunnel type, and VNI. + */ +/* Input (88 bytes) */ + +struct hwrm_cfa_tunnel_filter_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + uint32_t enables; + /* This bit must be '1' for the l2_filter_id field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + /* This bit must be '1' for the l2_addr field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2) + /* This bit must be '1' for the l2_ivlan field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4) + /* This bit must be '1' for the l3_addr field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8) + /* This bit must be '1' for the l3_addr_type field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10) + /* This bit must be '1' for the t_l3_addr_type field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20) + /* This bit must be '1' for the t_l3_addr field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40) + /* This bit must be '1' for the tunnel_type field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80) + /* This bit must be '1' for the vni field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100) + /* This bit must be '1' for the dst_vnic_id field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200) + /* This bit must be '1' for the mirror_vnic_id field to be configured. */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400) + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint8_t l2_addr[6]; + /* + * This value sets the match value for the inner L2 MAC address. + * Destination MAC address for RX path. Source MAC address for TX path. + */ + uint16_t l2_ivlan; + /* + * This value sets VLAN ID value for inner VLAN. Only 12-bits of VLAN ID + * are used in setting the filter. + */ + uint32_t l3_addr[4]; + /* + * The value of inner destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint32_t t_l3_addr[4]; + /* + * The value of tunnel destination IP address to be used in filtering. + * For IPv4, first four bytes represent the IP address. + */ + uint8_t l3_addr_type; + /* + * This value indicates the type of inner IP address. 4 - IPv4 6 - IPv6 + * All others are invalid. + */ + uint8_t t_l3_addr_type; + /* + * This value indicates the type of tunnel IP address. 4 - IPv4 6 - IPv6 + * All others are invalid. + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Non-tunnel */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* Any tunneled traffic */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + uint8_t unused_0; + uint32_t vni; + /* + * Virtual Network Identifier (VNI). Only valid with tunnel_types VXLAN, + * NVGRE, and Geneve. Only lower 24-bits of VNI field are used in + * setting up the filter. + */ + uint32_t dst_vnic_id; + /* Logical VNIC ID of the destination VNIC. */ + uint32_t mirror_vnic_id; + /* Logical VNIC ID of the VNIC where traffic is mirrored. */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_cfa_tunnel_filter_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t tunnel_filter_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t flow_id; + /* + * This is the ID of the flow associated with this filter. This value + * shall be used to match and associate the flow identifier returned in + * completion records. A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_tunnel_filter_free */ +/* Description: Free a tunnel filter */ +/* Input (24 bytes) */ + +struct hwrm_cfa_tunnel_filter_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t tunnel_filter_id; + /* This value is an opaque id into CFA data structures. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_tunnel_filter_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_encap_record_alloc */ +/* + * Description: This command is used to create an encapsulation record. The + * source MAC address and source IP address specified for the source property + * checks shall be used in the encapsulation where applicable. + */ +/* Input (32 bytes) */ + +struct hwrm_cfa_encap_record_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + uint8_t encap_type; + /* Encapsulation Type. */ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6) + /* VLAN */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8) + uint8_t unused_0; + uint16_t unused_1; + uint32_t encap_data[16]; + /* This value is encap data used for the given encap type. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_encap_record_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t encap_record_id; + /* This value is an opaque id into CFA data structures. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_encap_record_free */ +/* Description: Free an encap record */ +/* Input (24 bytes) */ + +struct hwrm_cfa_encap_record_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t encap_record_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_encap_record_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_ntuple_filter_alloc */ +/* + * Description: This is a ntuple filter that uses fields from L4/L3 header and + * optionally fields from L2. The ntuple filters apply to receive traffic only. + * All L2/L3/L4 header fields are specified in network byte order. These filters + * can be used for Receive Flow Steering (RFS). # For ethertype value, only + * 0x0800 (IPv4) and 0x86dd (IPv6) shall be supported for ntuple filters. # If a + * field specified in this command is not enabled as a valid field, then that + * field shall not be used in matching packet header fields against this filter. + */ +/* Input (128 bytes) */ + +struct hwrm_cfa_ntuple_filter_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Setting of this flag indicates the applicability to the loopback + * path. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2) + uint32_t enables; + /* This bit must be '1' for the l2_filter_id field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + /* This bit must be '1' for the ethertype field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2) + /* This bit must be '1' for the tunnel_type field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4) + /* This bit must be '1' for the src_macaddr field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) + /* This bit must be '1' for the ipaddr_type field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10) + /* This bit must be '1' for the src_ipaddr field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20) + /* This bit must be '1' for the src_ipaddr_mask field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40) + /* This bit must be '1' for the dst_ipaddr field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80) + /* This bit must be '1' for the dst_ipaddr_mask field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100) + /* This bit must be '1' for the ip_protocol field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200) + /* This bit must be '1' for the src_port field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400) + /* This bit must be '1' for the src_port_mask field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800) + /* This bit must be '1' for the dst_port field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000) + /* This bit must be '1' for the dst_port_mask field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000) + /* This bit must be '1' for the pri_hint field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000) + /* This bit must be '1' for the ntuple_filter_id field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000) + /* This bit must be '1' for the dst_id field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000) + /* This bit must be '1' for the mirror_vnic_id field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000) + /* This bit must be '1' for the dst_macaddr field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000) + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint8_t src_macaddr[6]; + /* This value indicates the source MAC address in the Ethernet header. */ + uint16_t ethertype; /* big endian */ + /* This value indicates the ethertype in the Ethernet header. */ + uint8_t ip_addr_type; + /* + * This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All + * others are invalid. + */ + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + uint8_t ip_protocol; + /* + * The value of protocol filed in IP header. Applies to UDP and TCP + * traffic. 6 - UDP 17 - TCP + */ + /* invalid */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* UDP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x6) + /* TCP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x11) + uint16_t dst_id; + /* + * If set, this value shall represent the Logical VNIC ID of the + * destination VNIC for the RX path and network port id of the + * destination port for the TX path. + */ + uint16_t mirror_vnic_id; + /* Logical VNIC ID of the VNIC where traffic is mirrored. */ + uint8_t tunnel_type; + /* + * This value indicates the tunnel type for this filter. If this field + * is not specified, then the filter shall apply to both non-tunneled + * and tunneled packets. If this field conflicts with the tunnel_type + * specified in the l2_filter_id, then the HWRM shall return an error + * for this command. + */ + /* Non-tunnel */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* Any tunneled traffic */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + uint8_t pri_hint; + /* + * This hint is provided to help in placing the filter in the filter + * table. + */ + /* No preference */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0) + /* Above the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1) + /* Below the given filter */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2) + /* As high as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3) + /* As low as possible */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4) + uint32_t src_ipaddr[4]; /* big endian */ + /* + * The value of source IP address to be used in filtering. For IPv4, + * first four bytes represent the IP address. + */ + uint32_t src_ipaddr_mask[4]; /* big endian */ + /* + * The value of source IP address mask to be used in filtering. For + * IPv4, first four bytes represent the IP address mask. + */ + uint32_t dst_ipaddr[4]; /* big endian */ + /* + * The value of destination IP address to be used in filtering. For + * IPv4, first four bytes represent the IP address. + */ + uint32_t dst_ipaddr_mask[4]; /* big endian */ + /* + * The value of destination IP address mask to be used in filtering. For + * IPv4, first four bytes represent the IP address mask. + */ + uint16_t src_port; /* big endian */ + /* + * The value of source port to be used in filtering. Applies to UDP and + * TCP traffic. + */ + uint16_t src_port_mask; /* big endian */ + /* + * The value of source port mask to be used in filtering. Applies to UDP + * and TCP traffic. + */ + uint16_t dst_port; /* big endian */ + /* + * The value of destination port to be used in filtering. Applies to UDP + * and TCP traffic. + */ + uint16_t dst_port_mask; /* big endian */ + /* + * The value of destination port mask to be used in filtering. Applies + * to UDP and TCP traffic. + */ + uint64_t ntuple_filter_id_hint; + /* This is the ID of the filter that goes along with the pri_hint. */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_cfa_ntuple_filter_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t ntuple_filter_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t flow_id; + /* + * This is the ID of the flow associated with this filter. This value + * shall be used to match and associate the flow identifier returned in + * completion records. A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_ntuple_filter_free */ +/* Description: Free an ntuple filter */ +/* Input (24 bytes) */ + +struct hwrm_cfa_ntuple_filter_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t ntuple_filter_id; + /* This value is an opaque id into CFA data structures. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_ntuple_filter_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_ntuple_filter_cfg */ +/* Description: Configure an ntuple filter with new destination VNIC */ +/* Input (40 bytes) */ + +struct hwrm_cfa_ntuple_filter_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the new_dst_id field to be configured. */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + uint32_t unused_0; + uint64_t ntuple_filter_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t new_dst_id; + /* + * If set, this value shall represent the new Logical VNIC ID of the + * destination VNIC for the RX path and new network port id of the + * destination port for the TX path. + */ + uint32_t new_mirror_vnic_id; + /* New Logical VNIC ID of the VNIC where traffic is mirrored. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_ntuple_filter_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_em_flow_alloc */ +/* + * Description: This is a generic Exact Match (EM) flow that uses fields from + * L4/L3/L2 headers. The EM flows apply to transmit and receive traffic. All + * L2/L3/L4 header fields are specified in network byte order. For each EM flow, + * there is an associated set of actions specified. For tunneled packets, all + * L2/L3/L4 fields specified are fields of inner headers unless otherwise + * specified. # If a field specified in this command is not enabled as a valid + * field, then that field shall not be used in matching packet header fields + * against this EM flow entry. + */ +/* Input (112 bytes) */ + +struct hwrm_cfa_em_flow_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * Enumeration denoting the RX, TX type of the resource. This + * enumeration is used for resources that are similar for both TX and RX + * paths of the chip. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1) + /* tx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0) + /* rx path */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0) + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX + /* + * Setting of this flag indicates enabling of a byte counter for a given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2) + /* + * Setting of this flag indicates enabling of a packet counter for a + * given flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4) + /* + * Setting of this flag indicates de-capsulation action for the given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8) + /* + * Setting of this flag indicates encapsulation action for the given + * flow. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10) + /* + * Setting of this flag indicates drop action. If this flag is not set, + * then it should be considered accept action. + */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20) + uint32_t enables; + /* This bit must be '1' for the l2_filter_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1) + /* This bit must be '1' for the tunnel_type field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2) + /* This bit must be '1' for the tunnel_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4) + /* This bit must be '1' for the src_macaddr field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8) + /* This bit must be '1' for the dst_macaddr field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10) + /* This bit must be '1' for the ovlan_vid field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20) + /* This bit must be '1' for the ivlan_vid field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40) + /* This bit must be '1' for the ethertype field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80) + /* This bit must be '1' for the src_ipaddr field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100) + /* This bit must be '1' for the dst_ipaddr field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200) + /* This bit must be '1' for the ipaddr_type field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400) + /* This bit must be '1' for the ip_protocol field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800) + /* This bit must be '1' for the src_port field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000) + /* This bit must be '1' for the dst_port field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000) + /* This bit must be '1' for the dst_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000) + /* This bit must be '1' for the mirror_vnic_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000) + /* This bit must be '1' for the encap_record_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000) + uint64_t l2_filter_id; + /* + * This value identifies a set of CFA data structures used for an L2 + * context. + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Non-tunnel */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0) + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Network Virtualization Generic Routing Encapsulation (NVGRE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2) + /* Generic Routing Encapsulation (GRE) inside Ethernet payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3) + /* IP in IP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + /* Multi-Protocol Lable Switching (MPLS) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6) + /* Stateless Transport Tunnel (STT) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7) + /* Generic Routing Encapsulation (GRE) inside IP datagram payload */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8) + /* Any tunneled traffic */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff) + uint8_t unused_0; + uint16_t unused_1; + uint32_t tunnel_id; + /* + * Tunnel identifier. Virtual Network Identifier (VNI). Only valid with + * tunnel_types VXLAN, NVGRE, and Geneve. Only lower 24-bits of VNI + * field are used in setting up the filter. + */ + uint8_t src_macaddr[6]; + /* This value indicates the source MAC address in the Ethernet header. */ + uint8_t unused_2; + uint8_t unused_3; + uint8_t dst_macaddr[6]; + /* + * This value indicates the destination MAC address in the Ethernet + * header. + */ + uint16_t ovlan_vid; + /* + * This value indicates the VLAN ID of the outer VLAN tag in the + * Ethernet header. + */ + uint16_t ivlan_vid; + /* + * This value indicates the VLAN ID of the inner VLAN tag in the + * Ethernet header. + */ + uint16_t ethertype; /* big endian */ + /* This value indicates the ethertype in the Ethernet header. */ + uint8_t ip_addr_type; + /* + * This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All + * others are invalid. + */ + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0) + /* IPv4 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4) + /* IPv6 */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6) + uint8_t ip_protocol; + /* + * The value of protocol filed in IP header. Applies to UDP and TCP + * traffic. 6 - UDP 17 - TCP + */ + /* invalid */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0) + /* UDP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x6) + /* TCP */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x11) + uint8_t unused_4; + uint8_t unused_5; + uint32_t src_ipaddr[4]; /* big endian */ + /* + * The value of source IP address to be used in filtering. For IPv4, + * first four bytes represent the IP address. + */ + uint32_t dst_ipaddr[4]; /* big endian */ + /* + * The value of destination IP address to be used in filtering. For + * IPv4, first four bytes represent the IP address. + */ + uint16_t src_port; /* big endian */ + /* + * The value of source port to be used in filtering. Applies to UDP and + * TCP traffic. + */ + uint16_t dst_port; /* big endian */ + /* + * The value of destination port to be used in filtering. Applies to UDP + * and TCP traffic. + */ + uint16_t dst_id; + /* + * If set, this value shall represent the Logical VNIC ID of the + * destination VNIC for the RX path and network port id of the + * destination port for the TX path. + */ + uint16_t mirror_vnic_id; + /* Logical VNIC ID of the VNIC where traffic is mirrored. */ + uint32_t encap_record_id; + /* Logical ID of the encapsulation record. */ + uint32_t unused_6; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_cfa_em_flow_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t em_filter_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t flow_id; + /* + * This is the ID of the flow associated with this filter. This value + * shall be used to match and associate the flow identifier returned in + * completion records. A value of 0xFFFFFFFF shall indicate no flow id. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_em_flow_free */ +/* Description: Free an EM flow table entry */ +/* Input (24 bytes) */ + +struct hwrm_cfa_em_flow_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t em_filter_id; + /* This value is an opaque id into CFA data structures. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_em_flow_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_cfa_em_flow_cfg */ +/* Description: Configure an EM flow with new destination VNIC */ +/* Input (40 bytes) */ + +struct hwrm_cfa_em_flow_cfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the new_dst_id field to be configured. */ + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1) + /* + * This bit must be '1' for the new_mirror_vnic_id field to be + * configured. + */ + #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2) + uint32_t unused_0; + uint64_t em_filter_id; + /* This value is an opaque id into CFA data structures. */ + uint32_t new_dst_id; + /* + * If set, this value shall represent the new Logical VNIC ID of the + * destination VNIC for the RX path and network port id of the + * destination port for the TX path. + */ + uint32_t new_mirror_vnic_id; + /* New Logical VNIC ID of the VNIC where traffic is mirrored. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_cfa_em_flow_cfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_tunnel_dst_port_query */ +/* + * Description: This function is called by a driver to query tunnel type + * specific destination port configuration. + */ +/* Input (24 bytes) */ + +struct hwrm_tunnel_dst_port_query_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_tunnel_dst_port_query_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t tunnel_dst_port_id; + /* + * This field represents the identifier of L4 destination port used for + * the given tunnel type. This field is valid for specific tunnel types + * that use layer 4 (e.g. UDP) transports for tunneling. + */ + uint16_t tunnel_dst_port_val; /* big endian */ + /* + * This field represents the value of L4 destination port identified by + * tunnel_dst_port_id. This field is valid for specific tunnel types + * that use layer 4 (e.g. UDP) transports for tunneling. This field is + * in network byte order. A value of 0 means that the destination port + * is not configured. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_tunnel_dst_port_alloc */ +/* + * Description: This function is called by a driver to allocate l4 destination + * port for a specific tunnel type. The destination port value is provided in + * the input. If the HWRM supports only one global destination port for a tunnel + * type, then the HWRM shall keep track of its usage as described below. # The + * first caller that allocates a destination port shall always succeed and the + * HWRM shall save the destination port configuration for that tunnel type and + * increment the usage count to 1. # Subsequent callers allocating the same + * destination port for that tunnel type shall succeed and the HWRM shall + * increment the usage count for that port for each subsequent caller that + * succeeds. # Any subsequent caller trying to allocate a different destination + * port for that tunnel type shall fail until the usage count for the original + * destination port goes to zero. # A caller that frees a port will cause the + * usage count for that port to decrement. + */ +/* Input (24 bytes) */ + +struct hwrm_tunnel_dst_port_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + uint8_t unused_0; + uint16_t tunnel_dst_port_val; /* big endian */ + /* + * This field represents the value of L4 destination port used for the + * given tunnel type. This field is valid for specific tunnel types that + * use layer 4 (e.g. UDP) transports for tunneling. This field is in + * network byte order. A value of 0 shall fail the command. + */ + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_tunnel_dst_port_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t tunnel_dst_port_id; + /* + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_tunnel_dst_port_free */ +/* + * Description: This function is called by a driver to free l4 destination port + * for a specific tunnel type. + */ +/* Input (24 bytes) */ + +struct hwrm_tunnel_dst_port_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t tunnel_type; + /* Tunnel Type. */ + /* Virtual eXtensible Local Area Network (VXLAN) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1) + /* Generic Network Virtualization Encapsulation (Geneve) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5) + uint8_t unused_0; + uint16_t tunnel_dst_port_id; + /* + * Identifier of a tunnel L4 destination port value. Only applies to + * tunnel types that has l4 destination port parameters. + */ + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_tunnel_dst_port_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_stat_ctx_alloc */ +/* + * Description: This command allocates and does basic preparation for a stat + * context. + */ +/* Input (32 bytes) */ + +struct hwrm_stat_ctx_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t stats_dma_addr; + /* This is the address for statistic block. */ + uint32_t update_period_ms; + /* + * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms, + * 1000ms. + */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_stat_ctx_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t stat_ctx_id; + /* This is the statistics context ID value. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_stat_ctx_free */ +/* Description: This command is used to free a stat context. */ +/* Input (24 bytes) */ + +struct hwrm_stat_ctx_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t stat_ctx_id; + /* ID of the statistics context that is being queried. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_stat_ctx_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t stat_ctx_id; + /* This is the statistics context ID value. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_stat_ctx_query */ +/* Description: This command returns statistics of a context. */ +/* Input (24 bytes) */ + +struct hwrm_stat_ctx_query_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t stat_ctx_id; + /* ID of the statistics context that is being queried. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (176 bytes) */ + +struct hwrm_stat_ctx_query_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t tx_ucast_pkts; + /* Number of transmitted unicast packets */ + uint64_t tx_mcast_pkts; + /* Number of transmitted multicast packets */ + uint64_t tx_bcast_pkts; + /* Number of transmitted broadcast packets */ + uint64_t tx_err_pkts; + /* Number of transmitted packets with error */ + uint64_t tx_drop_pkts; + /* Number of dropped packets on transmit path */ + uint64_t tx_ucast_bytes; + /* Number of transmitted bytes for unicast traffic */ + uint64_t tx_mcast_bytes; + /* Number of transmitted bytes for multicast traffic */ + uint64_t tx_bcast_bytes; + /* Number of transmitted bytes for broadcast traffic */ + uint64_t rx_ucast_pkts; + /* Number of received unicast packets */ + uint64_t rx_mcast_pkts; + /* Number of received multicast packets */ + uint64_t rx_bcast_pkts; + /* Number of received broadcast packets */ + uint64_t rx_err_pkts; + /* Number of received packets with error */ + uint64_t rx_drop_pkts; + /* Number of dropped packets on received path */ + uint64_t rx_ucast_bytes; + /* Number of received bytes for unicast traffic */ + uint64_t rx_mcast_bytes; + /* Number of received bytes for multicast traffic */ + uint64_t rx_bcast_bytes; + /* Number of received bytes for broadcast traffic */ + uint64_t rx_agg_pkts; + /* Number of aggregated unicast packets */ + uint64_t rx_agg_bytes; + /* Number of aggregated unicast bytes */ + uint64_t rx_agg_events; + /* Number of aggregation events */ + uint64_t rx_agg_aborts; + /* Number of aborted aggregations */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_stat_ctx_clr_stats */ +/* Description: This command clears statistics of a context. */ +/* Input (24 bytes) */ + +struct hwrm_stat_ctx_clr_stats_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t stat_ctx_id; + /* ID of the statistics context that is being queried. */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_stat_ctx_clr_stats_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fw_reset */ +/* + * Description: This function is called by a driver to self reset the firmware + * running on the processor indicated by the embedded_proc_type. + */ +/* Input (24 bytes) */ + +struct hwrm_fw_reset_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t embedded_proc_type; + /* Type of embedded processor. */ + /* Boot Processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) + /* Management Processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) + /* Network control processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) + /* RoCE control processor */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) + /* Reserved */ + #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_RSVD UINT32_C(0x4) + uint8_t selfrst_status; + /* Type of self reset. */ + /* No Self Reset */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_fw_reset_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t selfrst_status; + /* Type of self reset. */ + /* No Self Reset */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + uint8_t unused_0; + uint16_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fw_qstatus */ +/* + * Description: This function is called by a driver to query the status of the + * firmware running on the processor indicated by the embedded_proc_type. + */ +/* Input (24 bytes) */ + +struct hwrm_fw_qstatus_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint8_t embedded_proc_type; + /* Type of embedded processor. */ + /* Boot Processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0) + /* Management Processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1) + /* Network control processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2) + /* RoCE control processor */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3) + /* Reserved */ + #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_RSVD UINT32_C(0x4) + uint8_t unused_0[7]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_fw_qstatus_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t selfrst_status; + /* Type of self reset. */ + /* No Self Reset */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0) + /* Self Reset as soon as possible to do so safely */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1) + /* Self Reset on PCIe Reset */ + #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2) + uint8_t unused_0; + uint16_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fw_set_time */ +/* + * Description: Inform the HWRM firmware of the current date/time. Ideally, the + * date/time will be current time in GMT/UTC and the zone value will be 0 + * (indicating UTC). If the time zone is not known, the zone value shall be + * 0xffff. Other values for zone are discouraged, but if specified, they + * indicate the number of minutes east of UTC, while zones west of UTC are + * represented with a 2's complement negative value (e.g. PST would be -480 + * while PDT would be -420). + */ +/* Input (32 bytes) */ + +struct hwrm_fw_set_time_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t year; + /* Current year */ + /* Date/time is not known */ + #define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0) + uint8_t month; + /* Current month of year (1-12) */ + uint8_t day; + /* Current day of month (1-31) */ + uint8_t hour; + /* Current hour (0-23) */ + uint8_t minute; + /* Current minute (0-59) */ + uint8_t second; + /* Current second (0-59) */ + uint8_t unused_0; + uint16_t millisecond; + /* Current millisecond (0-999) */ + uint16_t zone; + /* Minutes east of UTC, 0xffff if TZ is not known */ + /* Time zone is Coordinated Universal Time (UTC) */ + #define HWRM_FW_SET_TIME_INPUT_ZONE_UTC UINT32_C(0x0) + /* Time zone is not known */ + #define HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN UINT32_C(0xffff) + uint32_t unused_1; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_fw_set_time_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fw_get_time */ +/* Description: Query the HWRM firmware's notion of the current date/time. */ +/* Input (16 bytes) */ + +struct hwrm_fw_get_time_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_fw_get_time_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t year; + /* Current year */ + /* Date/time is not known */ + #define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0) + uint8_t month; + /* Current month of year (1-12) */ + uint8_t day; + /* Current day of month (1-31) */ + uint8_t hour; + /* Current hour (0-23) */ + uint8_t minute; + /* Current minute (0-59) */ + uint8_t second; + /* Current second (0-59) */ + uint8_t unused_0; + uint16_t millisecond; + /* Current millisecond (0-999) */ + uint16_t zone; + /* Minutes east of UTC, 0xffff if TZ is not known */ + /* Time zone is Coordinated Universal Time (UTC) */ + #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC UINT32_C(0x0) + /* Time zone is not known */ + #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN UINT32_C(0xffff) + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_exec_fwd_resp */ +/* + * Description: This command is used to send an encapsulated request to the + * HWRM. This command instructs the HWRM to execute the request and forward the + * response of the encapsulated request to the location specified in the + * original request that is encapsulated. The target id of this command shall be + * set to 0xFFFF (HWRM). The response location in this command shall be used to + * acknowledge the receipt of the encapsulated request and forwarding of the + * response. + */ +/* Input (128 bytes) */ + +struct hwrm_exec_fwd_resp_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t encap_request[26]; + /* + * This is an encapsulated request. This request should be executed by + * the HWRM and the response should be provided in the response buffer + * inside the encapsulated request. + */ + uint16_t encap_resp_target_id; + /* + * This value indicates the target id of the response to the + * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - + * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_exec_fwd_resp_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_reject_fwd_resp */ +/* + * Description: This command is used to send an encapsulated request to the + * HWRM. This command instructs the HWRM to reject the request and forward the + * error response of the encapsulated request to the location specified in the + * original request that is encapsulated. The target id of this command shall be + * set to 0xFFFF (HWRM). The response location in this command shall be used to + * acknowledge the receipt of the encapsulated request and forwarding of the + * response. + */ +/* Input (128 bytes) */ + +struct hwrm_reject_fwd_resp_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t encap_request[26]; + /* + * This is an encapsulated request. This request should be rejected by + * the HWRM and the error response should be provided in the response + * buffer inside the encapsulated request. + */ + uint16_t encap_resp_target_id; + /* + * This value indicates the target id of the response to the + * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - + * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_reject_fwd_resp_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fwd_resp */ +/* + * Description: This command is used to send an encapsulated response to the + * HWRM. The HWRM shall forward this response based on the target id. The + * response address provided in this command shall be used to acknowledge the + * receipt of the encapsulated response. The encapsulated response address + * provided in this command shall be used to provide the encapsulated response. + */ +/* Input (40 bytes) */ + +struct hwrm_fwd_resp_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t encap_resp_target_id; + /* + * This value indicates the target id of the encapsulated response. 0x0 + * - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE - Reserved for + * internal processors 0xFFFF - HWRM + */ + uint16_t encap_resp_cmpl_ring; + /* + * This value indicates the completion ring the encapsulated response + * will be optionally completed on. If the value is -1, then no CR + * completion shall be generated for the encapsulated response. Any + * other value must be a valid CR ring_id value. If a valid + * encap_resp_cmpl_ring is provided, then a CR completion shall be + * generated for the encapsulated response. + */ + uint16_t encap_resp_len; + /* This field indicates the length of encapsulated response. */ + uint8_t unused_0; + uint8_t unused_1; + uint64_t encap_resp_addr; + /* + * This is the host address where the encapsulated response will be + * written. This area must be 16B aligned and must be cleared to zero + * before the original request is made. + */ + uint32_t encap_resp[24]; + /* This is an encapsulated response. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_fwd_resp_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_fwd_async_event_cmpl */ +/* + * Description: This command is used to send an encapsulated asynchronous event + * completion to the HWRM. The HWRM shall forward this asynchronous event + * completion to target(s) specified in the command. The HWRM shall complete + * this command only after forwarding asynchronous event completion to specified + * targets. + */ +/* Input (32 bytes) */ + +struct hwrm_fwd_async_event_cmpl_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t encap_async_event_target_id; + /* + * This value indicates the target id of the encapsulated asynchronous + * event. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE - + * Reserved for internal processors 0xFFFF - Broadcast to all children + * VFs (only applicable when a PF is the requester) + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2[3]; + uint8_t unused_3; + uint32_t encap_async_event_cmpl[4]; + /* This is an encapsulated asynchronous event completion. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_fwd_async_event_cmpl_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_temp_monitor_query */ +/* + * Description: A temperature monitor is used to query the device temperature. + */ +/* Input (16 bytes) */ + +struct hwrm_temp_monitor_query_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_temp_monitor_query_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t temp; + /* The HWRM shall provide the current temperature of device in Celsius. */ + uint8_t unused_0; + uint16_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_wol_filter_alloc */ +/* + * Description: A Wake-On-LAN (WoL) filter is a filter resource that is used to + * identify a WoL packet. # Among all function drivers, the HWRM shall only + * allow PF drivers to allocate WoL filters. # The HWRM shall not allow VF + * drivers to allocate any WoL filters. # When partitioning is enabled and WoL + * is supported, the HWRM shall support at least one WoL filter per partition. # + * The HWRM shall retain a WoL filter setting until the filter is freed. # If + * the HWRM client is a function driver, then the HWRM shall not allow the HWRM + * client to set up WoL filters on the port that the function is not associated + * with. # If the HWRM client is one of the trusted embedded services (e.g. + * management service), the the HWRM shall allow the HWRM client to set up WoL + * filters on any port of the device. + */ +/* Input (64 bytes) */ + +struct hwrm_wol_filter_alloc_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + uint32_t enables; + /* This bit must be '1' for the mac_address field to be configured. */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1) + /* This bit must be '1' for the pattern_offset field to be configured. */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2) + /* This bit must be '1' for the pattern_buf_size field to be configured. */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4) + /* This bit must be '1' for the pattern_buf_addr field to be configured. */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8) + /* + * This bit must be '1' for the pattern_mask_addr field to be + * configured. + */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10) + /* + * This bit must be '1' for the pattern_mask_size field to be + * configured. + */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20) + uint16_t port_id; + /* Port ID of port on which WoL filter is configured. */ + uint8_t wol_type; + /* This value represents a Wake-on-LAN type. */ + /* Magic Paket */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff) + uint8_t unused_0; + uint32_t unused_1; + uint8_t mac_address[6]; + /* + * # If this field is enabled and magic packet WoL filter type is + * specified in this command, the value set in this field shall be used + * in setting the magic packet based WoL filter. # If this field is not + * enabled and magic packet WoL filter type is specified and port id is + * specified to 0xFF in this command, then the HWRM shall use default + * MAC address configured on the function associated with the HWRM + * client. # If this field is not enabled and magic packet WoL filter + * type is specified and port id is not specified to 0xFF in this + * command, then the HWRM shall use default MAC address configured on + * the port. + */ + uint16_t pattern_offset; + /* + * The offset from the beginning of MAC header where pattern should be + * matched. Applies to bitmap WoL. + */ + uint16_t pattern_buf_size; + /* The size of the pattern that is being matched. Applies to bitmap WoL. */ + uint16_t pattern_mask_size; + /* The size of the pattern mask. Applies to bitmap WoL. */ + uint32_t unused_2; + uint64_t pattern_buf_addr; + /* Physical address of the pattern buffer. Applies to bitmap WoL. */ + uint64_t pattern_mask_addr; + /* Physical address of the pattern mask. Applies to bitmap WoL. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_wol_filter_alloc_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t wol_filter_id; + /* This value identifies a Wake-on-LAN (WoL) filter. */ + uint8_t unused_0; + uint16_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_wol_filter_free */ +/* + * Description: Free a WoL filter. # Among all function drivers, the HWRM shall + * only allow PF drivers to free WoL filters. # The HWRM shall not allow VF + * drivers to free any WoL filters. # The HWRM shall not allow a function driver + * to free an Out-Of-Box WoL filter. # The HWRM shall not allow a function + * driver to free a WoL filter on a port that the corresponding function is not + * associated with. # The HWRM shall not allow a function driver to free a WoL + * filter on a function that the function driver is not associated with. + */ +/* Input (32 bytes) */ + +struct hwrm_wol_filter_free_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t flags; + /* + * # When this bit is set to '1', then all active WoL filters on the + * port are requested to be freed. # If the a function driver sets this + * flag to '1', then the HWRM shall free all active WoL filters that are + * not set by other function drivers on that port. + */ + #define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1) + uint32_t enables; + /* This bit must be '1' for the wol_filter_id field to be configured. */ + #define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1) + uint16_t port_id; + /* Port ID of the port on which WoL filter(s) is (are) being freed. */ + uint8_t wol_filter_id; + /* The HWRM shall ignore this field if free_all_wol_filters flag is set. */ + uint8_t unused_0[5]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_wol_filter_free_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_wol_filter_qcfg */ +/* + * Description: Query WoL filter configuration. # Among all function drivers, + * the HWRM shall only allow PF drivers to query WoL filters. # The HWRM shall + * not allow VF drivers to query any WoL filters. # The HWRM shall return WoL + * filters that are active on the associated port for which this query is being + * performed. # If the HWRM client is a function driver, then the HWRM shall not + * allow the HWRM client to query WoL filters that are set up by other function + * drivers. # If the HWRM client is a function driver, then the HWRM shall not + * allow the HWRM client to query WoL filters on the port that the function is + * not associated with. # If the HWRM client is one of the trusted embedded + * service (e.g. management service), the the HWRM shall allow the HWRM client + * to query WoL filters on any port of the device. + */ +/* Input (56 bytes) */ + +struct hwrm_wol_filter_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port on which WoL filter that is being queried. */ + uint16_t handle; + /* + * This is an opaque handle used to access filters. # The HWRM client + * shall set this field to 0x0000 to begin the query. # After the first + * query, the HWRM client shall retrieve next filters (if they exist) + * using the HWRM provided handle in the response. + */ + uint32_t unused_0; + uint64_t pattern_buf_addr; + /* + * Physical address of the pattern buffer. Applies to bitmap WoL filter + * only. # Value of 0 indicates an invalid buffer address. If this field + * is set to 0, then HWRM shall ignore pattern_buf_size. # If the HWRM + * client provides an invalid buffer address for the pattern, then the + * HWRM is not required to provide pattern when the response contains a + * bitmap WoL filter. + */ + uint64_t pattern_buf_size; + /* The sixe of the pattern buffer. Applies to bitmap WoL filter only. */ + uint64_t pattern_mask_addr; + /* + * Physical address of the pattern mask. Applies to bitmap WoL filter + * only. # Value of 0 indicates an invalid pattern mask address. If this + * field is set to 0, then HWRM shall ignore pattern_mask_size. # If the + * HWRM client provides an invalid mask address for the pattern, then + * the HWRM is not required to provide mask when the response contains a + * bitmap WoL filter. + */ + uint64_t pattern_mask_size; + /* + * The size of the buffer for pattern mask. Applies to bitmap WoL filter + * only. + */ +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_wol_filter_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t next_handle; + /* + * This is the next handle that is used to access filters. # If this + * field is set to 0x0000, then no WoL filters are currently configured + * on this port and all other fields in the output shall be ignored by + * the HWRM client. # If this field is set to neither 0x0000 nor 0xFFFF, + * then the wol_filter_id is valid and the parameters provided in the + * response are based on the wol_type. # If this field is set to 0xFFFF, + * then there are no remaining configured WoL filters to be queried for + * the queried function after this response, wol_filter_id is valid and + * the parameters provided in the response are based on the wol_type. + */ + uint8_t wol_filter_id; + /* This value identifies the filter returned in this response. */ + uint8_t wol_type; + /* + * This value identifies the type of WoL filter returned in this + * response. + */ + /* Magic Paket */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff) + uint32_t unused_0; + uint8_t mac_address[6]; + /* + * The MAC address value used by the WoL filter. Applies to magic packet + * based WoL. + */ + uint16_t pattern_offset; + /* + * The offset from the beginning of MAC header where pattern should be + * matched. Applies to bitmap WoL. + */ + uint16_t pattern_size; + /* + * The actual size of the pattern that is being returned. Applies to + * bitmap WoL. + */ + uint16_t pattern_mask_size; + /* + * The actual size of the pattern mask that is being returned. Applies + * to bitmap WoL. + */ + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_wol_reason_qcfg */ +/* Description: Query WoL reason for the last system wake up. */ +/* Input (40 bytes) */ + +struct hwrm_wol_reason_qcfg_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t port_id; + /* Port ID of port for which this query is for. */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2[3]; + uint8_t unused_3; + uint64_t wol_pkt_buf_addr; + /* Physical address of the packet buffer for querying WoL packet. */ + uint64_t wol_pkt_buf_size; + /* The size of the buffer for the WoL packet. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_wol_reason_qcfg_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint8_t wol_filter_id; + /* + * This value identifies the filter that matched the last WoL packet. + * This id is only valid with valid WoL reason. + */ + uint8_t wol_reason; + /* + * This value identifies the type of WoL reason returned in this + * response. When the wol_type is set to invalid, then there is no WoL + * event that happened during last system wake-up. + */ + /* Magic Paket */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0) + /* Bitmap */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1) + /* Invalid */ + #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff) + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t unused_4; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_dbg_dump */ +/* + * Description: This command is used by to initiate the dump of debug + * information to a driver specified address. + */ +/* Input (40 bytes) */ + +struct hwrm_dbg_dump_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t handle; + /* + * Handle used to dump debug data. handle = 0 indicates the beginning of + * the dump. handle != 0 indicates the request to dump the next part. + */ + uint32_t unused_0; + uint64_t host_dbg_dump_addr; + /* + * Address of the host buffer where the debug data is requested to be + * dumped. + */ + uint64_t host_dbg_dump_addr_len; + /* Length of host buffer used for transferring debug data. */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_dbg_dump_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t nexthandle; + /* + * Handle used to indicate availability of additional debug data. + * nexthandle = 0 indicates that there is no more debug data available. + * nexthandle != 0 indicates the handle value that should be used to + * request the next part of debug data. + */ + uint32_t dbg_data_len; + /* The number of bytes of debug data written to debug dump buffer. */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_raw_write_blk */ +/* + * Note: Write an unmanaged block of data at any physical offset within the + * NVRAM. Used for initial provisioning/manufacturing purposes only. Implemented + * in the ChiMP boot-strap firmware (fwutil.bin) only. + */ +/* Input (32 bytes) */ + +struct hwrm_nvm_raw_write_blk_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_src_addr; + /* + * 64-bit Host Source Address. This is the loation of the source data to + * be written. + */ + uint32_t dest_addr; + /* + * 32-bit Destination Address. This is the NVRAM byte-offset where the + * source data will be written to. + */ + uint32_t len; + /* Length of data to be written, in bytes. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_raw_write_blk_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_read */ +/* + * Note: Read the contents of an NVRAM item as referenced (indexed) by an + * existing directory entry. + */ +/* Input (40 bytes) */ + +struct hwrm_nvm_read_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_dest_addr; + /* + * 64-bit Host Destination Address. This is the host address where the + * data will be written to. + */ + uint16_t dir_idx; + /* The 0-based index of the directory entry. */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t offset; + /* The NVRAM byte-offset to read from. */ + uint32_t len; + /* The length of the data to be read, in bytes. */ + uint32_t unused_2; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_read_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_raw_dump */ +/* Note: Dump a raw block of data from NVRAM. */ +/* Input (32 bytes) */ + +struct hwrm_nvm_raw_dump_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_dest_addr; + /* + * 64-bit Host Destination Address. This is the host address where the + * data will be written to. + */ + uint32_t offset; + /* 32-bit NVRAM byte-offset to read from. */ + uint32_t len; + /* Total length of NVRAM contents to be read, in bytes. */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_raw_dump_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_get_dir_entries */ +/* + * Description: Read the NVRAM directory. Each directory entry is at least 24 + * bytes in length and contains the: - 16-bit directory entry type + * (BNX_DIR_TYPE_* value) - 16-bit ordinal (instance of this directory entry + * type) - 16-bit extension flags (identifies inactive entries and entries for + * firmware update) - 16-bit attribute flags (identifies entries with a + * purposely invalid chksum value) - 32-bit byte-offset into NVRAM where this + * item data is located - 32-bit length of allocated NVRAM for item, in bytes + * (multiple of block size) - 32-bit length of data (excluding padding), in + * bytes (may be 0) - 32-bit data checksum (CRC-32) See the + * bnxnvm_directory_entry_t definition in the file bnxnvm_defs.h. + */ +/* Input (24 bytes) */ + +struct hwrm_nvm_get_dir_entries_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_dest_addr; + /* + * 64-bit Host Destination Address. This is the host address where the + * directory will be written. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_get_dir_entries_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_get_dir_info */ +/* Note: Get Directory Header info. */ +/* Input (16 bytes) */ + +struct hwrm_nvm_get_dir_info_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_nvm_get_dir_info_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t entries; + /* Number of directory entries in the directory. */ + uint32_t entry_length; + /* Size of each directory entry, in bytes. */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_write */ +/* + * Note: Write to the allocated NVRAM of an item referenced by an existing + * directory entry. + */ +/* Input (48 bytes) */ + +struct hwrm_nvm_write_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_src_addr; + /* 64-bit Host Source Address. This is where the source data is. */ + uint16_t dir_type; + /* + * The Directory Entry Type (valid values are defined in the + * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). + */ + uint16_t dir_ordinal; + /* + * Directory ordinal. The 0-based instance of the combined Directory + * Entry Type and Extension. + */ + uint16_t dir_ext; + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file + * bnxnvm_defs.h). + */ + uint16_t dir_attr; + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file + * bnxnvm_defs.h). + */ + uint32_t dir_data_length; + /* + * Length of data to write, in bytes. May be less than or equal to the + * allocated size for the directory entry. The data length stored in the + * directory entry will be updated to reflect this value once the write + * is complete. + */ + uint16_t option; + /* Option. */ + uint16_t flags; + /* + * When this bit is '1', the original active image will not be removed. + * TBD: what purpose is this? + */ + #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1) + uint32_t dir_item_length; + /* + * The requested length of the allocated NVM for the item, in bytes. + * This value may be greater than or equal to the specified data length + * (dir_data_length). If this value is less than the specified data + * length, it will be ignored. The response will contain the actual + * allocated item length, which may be greater than the requested item + * length. The purpose for allocating more than the required number of + * bytes for an item's data is to pre-allocate extra storage (padding) + * to accommodate the potential future growth of an item (e.g. upgraded + * firmware with a size increase, log growth, expanded configuration + * data). + */ + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_write_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t dir_item_length; + /* + * Length of the allocated NVM for the item, in bytes. The value may be + * greater than or equal to the specified data length or the requested + * item length. The actual item length used when creating a new + * directory entry will be a multiple of an NVM block size. + */ + uint16_t dir_idx; + /* The directory index of the created or modified item. */ + uint8_t unused_0; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_modify */ +/* + * Note: Modify the contents of an NVRAM item as referenced (indexed) by an + * existing directory entry. + */ +/* Input (40 bytes) */ + +struct hwrm_nvm_modify_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint64_t host_src_addr; + /* 64-bit Host Source Address. This is where the modified data is. */ + uint16_t dir_idx; + /* 16-bit directory entry index. */ + uint8_t unused_0; + uint8_t unused_1; + uint32_t offset; + /* 32-bit NVRAM byte-offset to modify content from. */ + uint32_t len; + /* + * Length of data to be modified, in bytes. The length shall be non- + * zero. + */ + uint32_t unused_2; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_modify_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_find_dir_entry */ +/* + * Note: Search a directory entry in the directory by either directory entry + * index or directory entry parameters. + */ +/* Input (32 bytes) */ + +struct hwrm_nvm_find_dir_entry_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the dir_idx_valid field to be configured. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1) + uint16_t dir_idx; + /* Directory Entry Index */ + uint16_t dir_type; + /* Directory Entry (Image) Type */ + uint16_t dir_ordinal; + /* Directory ordinal. The instance of this Directory Type */ + uint16_t dir_ext; + /* The Directory Entry Extension flags. */ + uint8_t opt_ordinal; + /* This value indicates the search option using dir_ordinal. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3) + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0 + /* Equal to specified ordinal value. */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0) + /* Greater than or equal to specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1) + /* Greater than specified ordinal value */ + #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2) + uint8_t unused_1[3]; +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_nvm_find_dir_entry_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t dir_item_length; + /* Allocated NVRAM for this directory entry, in bytes. */ + uint32_t dir_data_length; + /* Size of the stored data for this directory entry, in bytes. */ + uint32_t fw_ver; + /* + * Firmware version. Only valid if the directory entry is for embedded + * firmware stored in APE_BIN Format. + */ + uint16_t dir_ordinal; + /* Directory ordinal. */ + uint16_t dir_idx; + /* Directory Entry Index */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_erase_dir_entry */ +/* + * Note: Remove a directory entry specified by the directory entry index from + * the directory. + */ +/* Input (24 bytes) */ + +struct hwrm_nvm_erase_dir_entry_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t dir_idx; + /* Directory Entry Index */ + uint16_t unused_0[3]; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_erase_dir_entry_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_get_dev_info */ +/* + * Note: Get device info. Return Manufacturer_ID, Device_ID, block_size, + * nvram_size, reserved_size and available_size. + */ +/* Input (16 bytes) */ + +struct hwrm_nvm_get_dev_info_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ +} __attribute__((packed)); + +/* Output (32 bytes) */ + +struct hwrm_nvm_get_dev_info_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint16_t manufacturer_id; + /* Manufacturer ID. */ + uint16_t device_id; + /* Device ID. */ + uint32_t sector_size; + /* Sector size of the NVRAM device. */ + uint32_t nvram_size; + /* Total size, in bytes of the NVRAM device. */ + uint32_t reserved_size; + uint32_t available_size; + /* + * Available size that can be used, in bytes. Available size is the + * NVRAM size take away the used size and reserved size. + */ + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_mod_dir_entry */ +/* Note: Modify a directory entry parameters in the directory. */ +/* Input (32 bytes) */ + +struct hwrm_nvm_mod_dir_entry_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t enables; + /* This bit must be '1' for the checksum field to be configured. */ + #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1) + uint16_t dir_idx; + /* Directory Entry Index */ + uint16_t dir_ordinal; + /* Directory ordinal. The (0-based) instance of this Directory Type. */ + uint16_t dir_ext; + /* + * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension + * flag definitions). + */ + uint16_t dir_attr; + /* + * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute + * flag definitions). + */ + uint32_t checksum; + /* + * If valid, then this field updates the checksum value of the content + * in the directory entry. + */ +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_mod_dir_entry_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_verify_update */ +/* + * Description: Verify updated content of a directory entry. Before this + * verification, there should be two valid directory entries of the given + * directory type (one with "UPDATE" directory extension flag and the current + * one "ACTIVE"). Below are steps the HWRM performs for executing this command: + * # The HWRM finds the directory entry with "UDPATE" extension flag based on + * input parameters. The new directory entry should already have updated + * contents. # The HWRM performs signature verification of the updated content. + * # If the signature verification is successful, the two directory entries are + * switched (the verified updated entry is made active and the current "ACTIVE" + * entry is marked with "UPDATE" extension flag). Implementation notes: # The + * HWRM shall allow this command to be requested against any dir_type value (and + * not limit it to a subset). # In the case of an updated HWRM firmware, the new + * firmware version shall not automatically take effect (i.e. be executed). + */ +/* Input (24 bytes) */ + +struct hwrm_nvm_verify_update_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint16_t dir_type; + /* Directory Entry Type, to be verified. */ + uint16_t dir_ordinal; + /* Directory ordinal. The instance of the Directory Type to be verified. */ + uint16_t dir_ext; + /* + * The Directory Entry Extension flags. The "UPDATE" extension flag must + * be set in this value. A corresponding directory entry with the same + * type and ordinal values but *without* the "UPDATE" extension flag + * must also exist. The other flags of the extension must be identical + * between the active and update entries. + */ + uint16_t unused_0; +} __attribute__((packed)); + +/* Output (16 bytes) */ + +struct hwrm_nvm_verify_update_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint32_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +/* hwrm_nvm_install_update */ +/* + * Description: Install a staged NVM package. A package file must first be + * staged into the "UPDATE" NVM item. This staging is accomplished using the + * nvm_write and/or nvm_modify HWRM commands. + */ +/* Input (24 bytes) */ + +struct hwrm_nvm_install_update_input { + uint16_t req_type; + /* + * This value indicates what type of request this is. The format for the + * rest of the command is determined by this field. + */ + uint16_t cmpl_ring; + /* + * This value indicates the what completion ring the request will be + * optionally completed on. If the value is -1, then no CR completion + * will be generated. Any other value must be a valid CR ring_id value + * for this function. + */ + uint16_t seq_id; + /* This value indicates the command sequence number. */ + uint16_t target_id; + /* + * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids + * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM + */ + uint64_t resp_addr; + /* + * This is the host address where the response will be written when the + * request is complete. This area must be 16B aligned and must be + * cleared to zero before the request is made. + */ + uint32_t install_type; + /* + * Installation type. If the value 3 through 0xffff is used, only + * packaged items with that type value will be installed and conditional + * installation directives for those packaged items will be over-ridden + * (i.e. 'create' or 'replace' will be treated as 'install'). + */ + /* + * Perform a normal package installation. Conditional + * installation directives (e.g. 'create' and 'replace') of + * packaged items will be followed. + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0) + /* + * Install all packaged items regardless of installation + * directive (i.e. treat all packaged items as though they have + * an installation directive of 'install'). + */ + #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff) + uint32_t unused_0; +} __attribute__((packed)); + +/* Output (24 bytes) */ + +struct hwrm_nvm_install_update_output { + uint16_t error_code; + /* + * Pass/Fail or error type Note: receiver to verify the in parameters, + * and fail the call with an error when appropriate + */ + uint16_t req_type; + /* This field returns the type of original request. */ + uint16_t seq_id; + /* This field provides original sequence number of the command. */ + uint16_t resp_len; + /* + * This field is the length of the response in bytes. The last byte of + * the response is a valid flag that will read as '1' when the command + * has been completely written to memory. + */ + uint64_t installed_items; + /* + * Bit-mask of successfully installed items. Bit-0 corresponding to the + * first packaged item, Bit-1 for the second item, etc. A value of 0 + * indicates that no items were successfully installed. + */ + uint8_t result; + /* result is 8 b */ + /* There was no problem with the package installation. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0) + uint8_t problem_item; + /* problem_item is 8 b */ + /* There was no problem with any packaged items. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0) + /* There was a problem with the NVM package itself. */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff) + uint8_t reset_required; + /* reset_required is 8 b */ + /* + * No reset is required for installed/updated firmware or + * microcode to take effect. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0) + /* + * A PCIe reset (e.g. system reboot) is required for newly + * installed/updated firmware or microcode to take effect. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1) + /* + * A controller power reset (e.g. system power-cycle) is + * required for newly installed/updated firmware or microcode to + * take effect. Some newly installed/updated firmware or + * microcode may still take effect upon the next PCIe reset. + */ + #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2) + uint8_t unused_0; + uint8_t unused_1; + uint8_t unused_2; + uint8_t unused_3; + uint8_t valid; + /* + * This field is used in Output records to indicate that the output is + * completely written to RAM. This field should be read as '1' to + * indicate that the output has been completely written. When writing a + * command completion or response to an internal processor, the order of + * writes has to be such that this field is written last. + */ +} __attribute__((packed)); + +#endif /* _HSI_STRUCT_DEF_EXTERNAL_H_ */ Index: sys/dev/bnxt/if_bnxt.c =================================================================== --- /dev/null +++ sys/dev/bnxt/if_bnxt.c @@ -0,0 +1,2359 @@ +/*- + * Broadcom NetXtreme-C/E network driver. + * + * Copyright (c) 2016 Broadcom, All Rights Reserved. + * The term Broadcom refers to Broadcom Limited and/or its subsidiaries + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "opt_inet.h" +#include "opt_inet6.h" +#include "opt_rss.h" + +#include "ifdi_if.h" + +#include "bnxt.h" +#include "bnxt_hwrm.h" +#include "bnxt_ioctl.h" +#include "bnxt_sysctl.h" +#include "hsi_struct_def.h" + +/* + * PCI Device ID Table + */ + +static pci_vendor_info_t bnxt_vendor_info_array[] = +{ + PVID(BROADCOM_VENDOR_ID, BCM57301, + "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57302, + "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57304, + "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57402, + "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57404, + "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57406, + "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57402_NPAR, + "Broadcom BCM57402 NetXtreme-E Partition"), + PVID(BROADCOM_VENDOR_ID, BCM57407, + "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57404_NPAR, + "Broadcom BCM57404 NetXtreme-E Partition"), + PVID(BROADCOM_VENDOR_ID, BCM57406_NPAR, + "Broadcom BCM57406 NetXtreme-E Partition"), + PVID(BROADCOM_VENDOR_ID, BCM57407_SFP, + "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet Controller"), + PVID(BROADCOM_VENDOR_ID, BCM57304_VF, + "Broadcom BCM57304 NetXtreme-C Virtual Function"), + PVID(BROADCOM_VENDOR_ID, BCM57404_VF, + "Broadcom BCM57404 NetXtreme-E Virtual Function"), + /* required last entry */ + + PVID_END +}; + +/* + * Function prototypes + */ + +static void *bnxt_register(device_t dev); + +/* Soft queue setup and teardown */ +static int bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, + uint64_t *paddrs, int ntxqs, int ntxqsets); +static int bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, + uint64_t *paddrs, int nrxqs, int nrxqsets); +static void bnxt_queues_free(if_ctx_t ctx); + +/* Device setup and teardown */ +static int bnxt_attach_pre(if_ctx_t ctx); +static int bnxt_attach_post(if_ctx_t ctx); +static int bnxt_detach(if_ctx_t ctx); + +/* Device configuration */ +static void bnxt_init(if_ctx_t ctx); +static void bnxt_stop(if_ctx_t ctx); +static void bnxt_multi_set(if_ctx_t ctx); +static int bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu); +static void bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr); +static int bnxt_media_change(if_ctx_t ctx); +static int bnxt_promisc_set(if_ctx_t ctx, int flags); +static uint64_t bnxt_get_counter(if_ctx_t, ift_counter); +static void bnxt_update_admin_status(if_ctx_t ctx); + +/* Interrupt enable / disable */ +static void bnxt_intr_enable(if_ctx_t ctx); +static int bnxt_queue_intr_enable(if_ctx_t ctx, uint16_t qid); +static void bnxt_disable_intr(if_ctx_t ctx); +static int bnxt_msix_intr_assign(if_ctx_t ctx, int msix); + +/* vlan support */ +static void bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag); +static void bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag); + +/* ioctl */ +static int bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data); + +/* Internal support functions */ +static int bnxt_probe_phy(struct bnxt_softc *softc); +static void bnxt_add_media_types(struct bnxt_softc *softc); +static int bnxt_pci_mapping(struct bnxt_softc *softc); +static void bnxt_pci_mapping_free(struct bnxt_softc *softc); +static int bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state); +static int bnxt_handle_def_cp(void *arg); +static int bnxt_handle_rx_cp(void *arg); +static void bnxt_clear_ids(struct bnxt_softc *softc); +static void inline bnxt_do_enable_intr(struct bnxt_cp_ring *cpr); +static void inline bnxt_do_disable_intr(struct bnxt_cp_ring *cpr); +static void bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr); +static void bnxt_def_cp_task(void *context); +static void bnxt_handle_async_event(struct bnxt_softc *softc, + struct cmpl_base *cmpl); +static uint8_t get_phy_type(struct bnxt_softc *softc); +static uint64_t bnxt_get_baudrate(struct bnxt_link_info *link); + +/* + * Device Interface Declaration + */ + +static device_method_t bnxt_methods[] = { + /* Device interface */ + DEVMETHOD(device_register, bnxt_register), + DEVMETHOD(device_probe, iflib_device_probe), + DEVMETHOD(device_attach, iflib_device_attach), + DEVMETHOD(device_detach, iflib_device_detach), + DEVMETHOD(device_shutdown, iflib_device_shutdown), + DEVMETHOD(device_suspend, iflib_device_suspend), + DEVMETHOD(device_resume, iflib_device_resume), + DEVMETHOD_END +}; + +static driver_t bnxt_driver = { + "bnxt", bnxt_methods, sizeof(struct bnxt_softc), +}; + +devclass_t bnxt_devclass; +DRIVER_MODULE(bnxt, pci, bnxt_driver, bnxt_devclass, 0, 0); + +MODULE_DEPEND(bnxt, pci, 1, 1, 1); +MODULE_DEPEND(bnxt, ether, 1, 1, 1); +MODULE_DEPEND(bnxt, iflib, 1, 1, 1); + +static device_method_t bnxt_iflib_methods[] = { + DEVMETHOD(ifdi_tx_queues_alloc, bnxt_tx_queues_alloc), + DEVMETHOD(ifdi_rx_queues_alloc, bnxt_rx_queues_alloc), + DEVMETHOD(ifdi_queues_free, bnxt_queues_free), + + DEVMETHOD(ifdi_attach_pre, bnxt_attach_pre), + DEVMETHOD(ifdi_attach_post, bnxt_attach_post), + DEVMETHOD(ifdi_detach, bnxt_detach), + + DEVMETHOD(ifdi_init, bnxt_init), + DEVMETHOD(ifdi_stop, bnxt_stop), + DEVMETHOD(ifdi_multi_set, bnxt_multi_set), + DEVMETHOD(ifdi_mtu_set, bnxt_mtu_set), + DEVMETHOD(ifdi_media_status, bnxt_media_status), + DEVMETHOD(ifdi_media_change, bnxt_media_change), + DEVMETHOD(ifdi_promisc_set, bnxt_promisc_set), + DEVMETHOD(ifdi_get_counter, bnxt_get_counter), + DEVMETHOD(ifdi_update_admin_status, bnxt_update_admin_status), + + DEVMETHOD(ifdi_intr_enable, bnxt_intr_enable), + DEVMETHOD(ifdi_queue_intr_enable, bnxt_queue_intr_enable), + DEVMETHOD(ifdi_intr_disable, bnxt_disable_intr), + DEVMETHOD(ifdi_msix_intr_assign, bnxt_msix_intr_assign), + + DEVMETHOD(ifdi_vlan_register, bnxt_vlan_register), + DEVMETHOD(ifdi_vlan_unregister, bnxt_vlan_unregister), + + DEVMETHOD(ifdi_priv_ioctl, bnxt_priv_ioctl), + + DEVMETHOD_END +}; + +static driver_t bnxt_iflib_driver = { + "bnxt", bnxt_iflib_methods, sizeof(struct bnxt_softc) +}; + +/* + * iflib shared context + */ + +char bnxt_driver_version[] = "https://github.com/Broadcom/freebsd-nxt/commits/bnxt-dev"; +extern struct if_txrx bnxt_txrx; +static struct if_shared_ctx bnxt_sctx_init = { + .isc_magic = IFLIB_MAGIC, + .isc_txrx = &bnxt_txrx, + .isc_driver = &bnxt_iflib_driver, + .isc_nfl = 2, // Number of Free Lists + .isc_flags = IFLIB_HAS_RXCQ | IFLIB_HAS_TXCQ, + .isc_q_align = PAGE_SIZE, + .isc_tx_maxsize = BNXT_TSO_SIZE, + .isc_tx_maxsegsize = BNXT_TSO_SIZE, + .isc_rx_maxsize = BNXT_TSO_SIZE, + .isc_rx_maxsegsize = BNXT_TSO_SIZE, + + // Only use a single segment to avoid page size constraints + .isc_rx_nsegments = 1, + .isc_ntxqs = 2, + .isc_nrxqs = 3, + .isc_nrxd_min = {16, 16, 16}, + .isc_nrxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 8, + PAGE_SIZE / sizeof(struct rx_prod_pkt_bd), + PAGE_SIZE / sizeof(struct rx_prod_pkt_bd)}, + .isc_nrxd_max = {INT32_MAX, INT32_MAX, INT32_MAX}, + .isc_ntxd_min = {16, 16, 16}, + .isc_ntxd_default = {PAGE_SIZE / sizeof(struct cmpl_base) * 2, + PAGE_SIZE / sizeof(struct tx_bd_short)}, + .isc_ntxd_max = {INT32_MAX, INT32_MAX, INT32_MAX}, + + .isc_admin_intrcnt = 1, + .isc_vendor_info = bnxt_vendor_info_array, + .isc_driver_version = bnxt_driver_version, +}; + +if_shared_ctx_t bnxt_sctx = &bnxt_sctx_init; + +/* + * Device Methods + */ + +static void * +bnxt_register(device_t dev) +{ + return bnxt_sctx; +} + +/* + * Device Dependent Configuration Functions +*/ + +/* Soft queue setup and teardown */ +static int +bnxt_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, + uint64_t *paddrs, int ntxqs, int ntxqsets) +{ + struct bnxt_softc *softc; + int i; + int rc; + + softc = iflib_get_softc(ctx); + + softc->tx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * ntxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->tx_cp_rings) { + device_printf(iflib_get_dev(ctx), + "unable to allocate TX completion rings\n"); + rc = ENOMEM; + goto cp_alloc_fail; + } + softc->tx_rings = malloc(sizeof(struct bnxt_ring) * ntxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->tx_rings) { + device_printf(iflib_get_dev(ctx), + "unable to allocate TX rings\n"); + rc = ENOMEM; + goto ring_alloc_fail; + } + rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats) * ntxqsets, + &softc->tx_stats, 0); + if (rc) + goto dma_alloc_fail; + bus_dmamap_sync(softc->tx_stats.idi_tag, softc->tx_stats.idi_map, + BUS_DMASYNC_PREREAD); + + for (i = 0; i < ntxqsets; i++) { + /* Set up the completion ring */ + softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; + softc->tx_cp_rings[i].ring.phys_id = + (uint16_t)HWRM_NA_SIGNATURE; + softc->tx_cp_rings[i].ring.softc = softc; + softc->tx_cp_rings[i].ring.id = + (softc->scctx->isc_nrxqsets * 2) + 1 + i; + softc->tx_cp_rings[i].ring.doorbell = + softc->tx_cp_rings[i].ring.id * 0x80; + softc->tx_cp_rings[i].ring.ring_size = + softc->scctx->isc_ntxd[0]; + softc->tx_cp_rings[i].ring.vaddr = vaddrs[i * ntxqs]; + softc->tx_cp_rings[i].ring.paddr = paddrs[i * ntxqs]; + + /* Set up the TX ring */ + softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->tx_rings[i].softc = softc; + softc->tx_rings[i].id = + (softc->scctx->isc_nrxqsets * 2) + 1 + i; + softc->tx_rings[i].doorbell = softc->tx_rings[i].id * 0x80; + softc->tx_rings[i].ring_size = softc->scctx->isc_ntxd[1]; + softc->tx_rings[i].vaddr = vaddrs[i * ntxqs + 1]; + softc->tx_rings[i].paddr = paddrs[i * ntxqs + 1]; + + bnxt_create_tx_sysctls(softc, i); + } + + softc->ntxqsets = ntxqsets; + return rc; + +dma_alloc_fail: + free(softc->tx_rings, M_DEVBUF); +ring_alloc_fail: + free(softc->tx_cp_rings, M_DEVBUF); +cp_alloc_fail: + return rc; +} + +static void +bnxt_queues_free(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + + // Free TX queues + iflib_dma_free(&softc->tx_stats); + free(softc->tx_rings, M_DEVBUF); + softc->tx_rings = NULL; + free(softc->tx_cp_rings, M_DEVBUF); + softc->tx_cp_rings = NULL; + softc->ntxqsets = 0; + + // Free RX queues + iflib_dma_free(&softc->rx_stats); + free(softc->grp_info, M_DEVBUF); + free(softc->ag_rings, M_DEVBUF); + free(softc->rx_rings, M_DEVBUF); + free(softc->rx_cp_rings, M_DEVBUF); +} + +static int +bnxt_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, + uint64_t *paddrs, int nrxqs, int nrxqsets) +{ + struct bnxt_softc *softc; + int i; + int rc; + + softc = iflib_get_softc(ctx); + + softc->rx_cp_rings = malloc(sizeof(struct bnxt_cp_ring) * nrxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->rx_cp_rings) { + device_printf(iflib_get_dev(ctx), + "unable to allocate RX completion rings\n"); + rc = ENOMEM; + goto cp_alloc_fail; + } + softc->rx_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->rx_rings) { + device_printf(iflib_get_dev(ctx), + "unable to allocate RX rings\n"); + rc = ENOMEM; + goto ring_alloc_fail; + } + softc->ag_rings = malloc(sizeof(struct bnxt_ring) * nrxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->ag_rings) { + device_printf(iflib_get_dev(ctx), + "unable to allocate aggregation rings\n"); + rc = ENOMEM; + goto ag_alloc_fail; + } + softc->grp_info = malloc(sizeof(struct bnxt_grp_info) * nrxqsets, + M_DEVBUF, M_NOWAIT | M_ZERO); + if (!softc->grp_info) { + device_printf(iflib_get_dev(ctx), + "unable to allocate ring groups\n"); + rc = ENOMEM; + goto grp_alloc_fail; + } + + rc = iflib_dma_alloc(ctx, sizeof(struct ctx_hw_stats) * nrxqsets, + &softc->rx_stats, 0); + if (rc) + goto hw_stats_alloc_fail; + bus_dmamap_sync(softc->rx_stats.idi_tag, softc->rx_stats.idi_map, + BUS_DMASYNC_PREREAD); + + for (i = 0; i < nrxqsets; i++) { + /* Allocation the completion ring */ + softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; + softc->rx_cp_rings[i].ring.phys_id = + (uint16_t)HWRM_NA_SIGNATURE; + softc->rx_cp_rings[i].ring.softc = softc; + softc->rx_cp_rings[i].ring.id = i + 1; + softc->rx_cp_rings[i].ring.doorbell = + softc->rx_cp_rings[i].ring.id * 0x80; + /* + * If this ring overflows, RX stops working. + */ + softc->rx_cp_rings[i].ring.ring_size = + softc->scctx->isc_nrxd[0]; + softc->rx_cp_rings[i].ring.vaddr = vaddrs[i * nrxqs]; + softc->rx_cp_rings[i].ring.paddr = paddrs[i * nrxqs]; + + /* Allocate the RX ring */ + softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->rx_rings[i].softc = softc; + softc->rx_rings[i].id = i + 1; + softc->rx_rings[i].doorbell = softc->rx_rings[i].id * 0x80; + softc->rx_rings[i].ring_size = softc->scctx->isc_nrxd[1]; + softc->rx_rings[i].vaddr = vaddrs[i * nrxqs + 1]; + softc->rx_rings[i].paddr = paddrs[i * nrxqs + 1]; + + /* Allocate the AG ring */ + softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->ag_rings[i].softc = softc; + softc->ag_rings[i].id = nrxqsets + i + 1; + softc->ag_rings[i].doorbell = softc->ag_rings[i].id * 0x80; + softc->ag_rings[i].ring_size = softc->scctx->isc_nrxd[2]; + softc->ag_rings[i].vaddr = vaddrs[i * nrxqs + 2]; + softc->ag_rings[i].paddr = paddrs[i * nrxqs + 2]; + + /* Allocate the ring group */ + softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->grp_info[i].stats_ctx = + softc->rx_cp_rings[i].stats_ctx_id; + softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; + softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; + softc->grp_info[i].cp_ring_id = + softc->rx_cp_rings[i].ring.phys_id; + + bnxt_create_rx_sysctls(softc, i); + } + + /* And finally, the VNIC */ + softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.flow_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.filter_id = -1; + softc->vnic_info.def_ring_grp = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.cos_rule = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.lb_rule = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.rx_mask = HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST; + softc->vnic_info.mc_list_count = 0; + softc->vnic_info.flags = BNXT_VNIC_FLAG_DEFAULT; + rc = iflib_dma_alloc(ctx, BNXT_MAX_MC_ADDRS * ETHER_ADDR_LEN, + &softc->vnic_info.mc_list, 0); + if (rc) + goto mc_list_alloc_fail; + + /* The VNIC RSS Hash Key */ + rc = iflib_dma_alloc(ctx, HW_HASH_KEY_SIZE, + &softc->vnic_info.rss_hash_key_tbl, 0); + if (rc) + goto rss_hash_alloc_fail; + bus_dmamap_sync(softc->vnic_info.rss_hash_key_tbl.idi_tag, + softc->vnic_info.rss_hash_key_tbl.idi_map, + BUS_DMASYNC_PREWRITE); + memcpy(softc->vnic_info.rss_hash_key_tbl.idi_vaddr, + softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE); + + /* Allocate the RSS tables */ + rc = iflib_dma_alloc(ctx, HW_HASH_INDEX_SIZE * sizeof(uint16_t), + &softc->vnic_info.rss_grp_tbl, 0); + if (rc) + goto rss_grp_alloc_fail; + bus_dmamap_sync(softc->vnic_info.rss_grp_tbl.idi_tag, + softc->vnic_info.rss_grp_tbl.idi_map, + BUS_DMASYNC_PREWRITE); + memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, + softc->vnic_info.rss_grp_tbl.idi_size); + + softc->nrxqsets = nrxqsets; + return rc; + +rss_grp_alloc_fail: + iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); +rss_hash_alloc_fail: + iflib_dma_free(&softc->vnic_info.mc_list); +mc_list_alloc_fail: + iflib_dma_free(&softc->rx_stats); +hw_stats_alloc_fail: + free(softc->grp_info, M_DEVBUF); +grp_alloc_fail: + free(softc->ag_rings, M_DEVBUF); +ag_alloc_fail: + free(softc->rx_rings, M_DEVBUF); +ring_alloc_fail: + free(softc->rx_cp_rings, M_DEVBUF); +cp_alloc_fail: + return rc; +} + +/* Device setup and teardown */ +static int +bnxt_attach_pre(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + if_softc_ctx_t scctx; + int rc = 0; + + softc->ctx = ctx; + softc->dev = iflib_get_dev(ctx); + softc->media = iflib_get_media(ctx); + softc->scctx = iflib_get_softc_ctx(ctx); + softc->sctx = iflib_get_sctx(ctx); + scctx = softc->scctx; + + switch (softc->sctx->isc_vendor_info->pvi_device_id) { + case BCM57402_NPAR: + case BCM57404_NPAR: + case BCM57406_NPAR: + softc->flags |= BNXT_FLAG_NPAR; + break; + case BCM57304_VF: + case BCM57404_VF: + softc->flags |= BNXT_FLAG_VF; + break; + } + + pci_enable_busmaster(softc->dev); + + if (bnxt_pci_mapping(softc)) + return (ENXIO); + + /* HWRM setup/init */ + BNXT_HWRM_LOCK_INIT(softc, device_get_nameunit(softc->dev)); + rc = bnxt_alloc_hwrm_dma_mem(softc); + if (rc) + goto dma_fail; + + /* Allocate the TPA start buffer */ + softc->tpa_start = malloc(sizeof(struct bnxt_full_tpa_start) * + (RX_TPA_START_CMPL_AGG_ID_MASK >> RX_TPA_START_CMPL_AGG_ID_SFT), + M_DEVBUF, M_NOWAIT | M_ZERO); + if (softc->tpa_start == NULL) { + rc = ENOMEM; + device_printf(softc->dev, + "Unable to allocate space for TPA\n"); + goto tpa_failed; + } + + /* Get firmware version and compare with driver */ + softc->ver_info = malloc(sizeof(struct bnxt_ver_info), + M_DEVBUF, M_NOWAIT | M_ZERO); + if (softc->ver_info == NULL) { + rc = ENOMEM; + device_printf(softc->dev, + "Unable to allocate space for version info\n"); + goto ver_alloc_fail; + } + /* Default minimum required HWRM version */ + softc->ver_info->hwrm_min_major = 1; + softc->ver_info->hwrm_min_minor = 2; + softc->ver_info->hwrm_min_update = 2; + + rc = bnxt_hwrm_ver_get(softc); + if (rc) { + device_printf(softc->dev, "attach: hwrm ver get failed\n"); + goto ver_fail; + } + + /* Get NVRAM info */ + softc->nvm_info = malloc(sizeof(struct bnxt_nvram_info), + M_DEVBUF, M_NOWAIT | M_ZERO); + if (softc->nvm_info == NULL) { + rc = ENOMEM; + device_printf(softc->dev, + "Unable to allocate space for NVRAM info\n"); + goto nvm_alloc_fail; + } + rc = bnxt_hwrm_nvm_get_dev_info(softc, &softc->nvm_info->mfg_id, + &softc->nvm_info->device_id, &softc->nvm_info->sector_size, + &softc->nvm_info->size, &softc->nvm_info->reserved_size, + &softc->nvm_info->available_size); + + /* Register the driver with the FW */ + rc = bnxt_hwrm_func_drv_rgtr(softc); + if (rc) { + device_printf(softc->dev, "attach: hwrm drv rgtr failed\n"); + goto drv_rgtr_fail; + } + + /* Get the HW capabilities */ + rc = bnxt_hwrm_func_qcaps(softc); + if (rc) + goto failed; + iflib_set_mac(ctx, softc->func.mac_addr); + + /* Get the queue config */ + rc = bnxt_hwrm_queue_qportcfg(softc); + if (rc) { + device_printf(softc->dev, "attach: hwrm qportcfg failed\n"); + goto failed; + } + + /* Now perform a function reset */ + rc = bnxt_hwrm_func_reset(softc); + bnxt_clear_ids(softc); + if (rc) + goto failed; + + /* Now set up iflib sc */ + scctx->isc_tx_nsegments = 31, + scctx->isc_tx_tso_segments_max = 31; + scctx->isc_tx_tso_size_max = BNXT_TSO_SIZE; + scctx->isc_tx_tso_segsize_max = BNXT_TSO_SIZE; + scctx->isc_vectors = softc->func.max_cp_rings; + if (scctx->isc_nrxd[0] < + ((scctx->isc_nrxd[1] * 4) + scctx->isc_nrxd[2])) + device_printf(softc->dev, + "WARNING: nrxd0 (%d) should be at least 4 * nrxd1 (%d) + nrxd2 (%d). Driver may be unstable\n", + scctx->isc_nrxd[0], scctx->isc_nrxd[1], scctx->isc_nrxd[2]); + if (scctx->isc_ntxd[0] < scctx->isc_ntxd[1] * 2) + device_printf(softc->dev, + "WARNING: ntxd0 (%d) should be at least 2 * ntxd1 (%d). Driver may be unstable\n", + scctx->isc_ntxd[0], scctx->isc_ntxd[1]); + scctx->isc_txqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_ntxd[0]; + scctx->isc_txqsizes[1] = sizeof(struct tx_bd_short) * + scctx->isc_ntxd[1]; + scctx->isc_rxqsizes[0] = sizeof(struct cmpl_base) * scctx->isc_nrxd[0]; + scctx->isc_rxqsizes[1] = sizeof(struct rx_prod_pkt_bd) * + scctx->isc_nrxd[1]; + scctx->isc_rxqsizes[2] = sizeof(struct rx_prod_pkt_bd) * + scctx->isc_nrxd[2]; + scctx->isc_max_rxqsets = min(pci_msix_count(softc->dev)-1, + softc->func.max_cp_rings - 1); + scctx->isc_max_rxqsets = min(scctx->isc_max_rxqsets, + softc->func.max_rx_rings); + scctx->isc_max_txqsets = min(softc->func.max_rx_rings, + softc->func.max_cp_rings - scctx->isc_max_rxqsets - 1); + scctx->isc_rss_table_size = HW_HASH_INDEX_SIZE; + scctx->isc_rss_table_mask = scctx->isc_rss_table_size - 1; + + /* iflib will map and release this bar */ + scctx->isc_msix_bar = pci_msix_table_bar(softc->dev); + + /* Allocate the default completion ring */ + softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; + softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->def_cp_ring.ring.softc = softc; + softc->def_cp_ring.ring.id = 0; + softc->def_cp_ring.ring.doorbell = softc->def_cp_ring.ring.id * 0x80; + softc->def_cp_ring.ring.ring_size = PAGE_SIZE / + sizeof(struct cmpl_base); + rc = iflib_dma_alloc(ctx, + sizeof(struct cmpl_base) * softc->def_cp_ring.ring.ring_size, + &softc->def_cp_ring_mem, 0); + softc->def_cp_ring.ring.vaddr = softc->def_cp_ring_mem.idi_vaddr; + softc->def_cp_ring.ring.paddr = softc->def_cp_ring_mem.idi_paddr; + iflib_config_gtask_init(ctx, &softc->def_cp_task, bnxt_def_cp_task, + "dflt_cp"); + + rc = bnxt_init_sysctl_ctx(softc); + if (rc) + goto init_sysctl_failed; + rc = bnxt_create_nvram_sysctls(softc->nvm_info); + if (rc) + goto failed; + + arc4rand(softc->vnic_info.rss_hash_key, HW_HASH_KEY_SIZE, 0); + softc->vnic_info.rss_hash_type = + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 | + HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; + rc = bnxt_create_config_sysctls_pre(softc); + if (rc) + goto failed; + + /* Initialize the vlan list */ + SLIST_INIT(&softc->vnic_info.vlan_tags); + softc->vnic_info.vlan_tag_list.idi_vaddr = NULL; + + return (rc); + +failed: + bnxt_free_sysctl_ctx(softc); +init_sysctl_failed: + bnxt_hwrm_func_drv_unrgtr(softc, false); +drv_rgtr_fail: + free(softc->nvm_info, M_DEVBUF); +nvm_alloc_fail: +ver_fail: + free(softc->ver_info, M_DEVBUF); +ver_alloc_fail: + free(softc->tpa_start, M_DEVBUF); +tpa_failed: + bnxt_free_hwrm_dma_mem(softc); +dma_fail: + BNXT_HWRM_LOCK_DESTROY(softc); + bnxt_pci_mapping_free(softc); + pci_disable_busmaster(softc->dev); + return (rc); +} + +static int +bnxt_attach_post(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + if_t ifp = iflib_get_ifp(ctx); + int capabilities, enabling; + int rc; + + bnxt_create_config_sysctls_post(softc); + + /* Update link state etc... */ + rc = bnxt_probe_phy(softc); + if (rc) + goto failed; + + /* Needs to be done after probing the phy */ + bnxt_create_ver_sysctls(softc); + bnxt_add_media_types(softc); + ifmedia_set(softc->media, IFM_ETHER | IFM_AUTO); + + if_sethwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_TCP_IPV6 | + CSUM_UDP_IPV6 | CSUM_TSO)); + + capabilities = + /* These are translated to hwassit bits */ + IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6 | IFCAP_TSO4 | IFCAP_TSO6 | + /* These are checked by iflib */ + IFCAP_LRO | IFCAP_VLAN_HWFILTER | + /* These are part of the iflib mask */ + IFCAP_RXCSUM | IFCAP_RXCSUM_IPV6 | IFCAP_VLAN_MTU | + IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | + /* These likely get lost... */ + IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU; + + if_setcapabilities(ifp, capabilities); + + enabling = capabilities; + + if_setcapenable(ifp, enabling); + + softc->scctx->isc_max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + + ETHER_CRC_LEN; + +failed: + return rc; +} + +static int +bnxt_detach(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct bnxt_vlan_tag *tag; + struct bnxt_vlan_tag *tmp; + int i; + + bnxt_do_disable_intr(&softc->def_cp_ring); + bnxt_free_sysctl_ctx(softc); + bnxt_hwrm_func_reset(softc); + bnxt_clear_ids(softc); + iflib_irq_free(ctx, &softc->def_cp_ring.irq); + iflib_config_gtask_deinit(&softc->def_cp_task); + /* We need to free() these here... */ + for (i = softc->nrxqsets-1; i>=0; i--) { + iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); + } + iflib_dma_free(&softc->vnic_info.mc_list); + iflib_dma_free(&softc->vnic_info.rss_hash_key_tbl); + iflib_dma_free(&softc->vnic_info.rss_grp_tbl); + if (softc->vnic_info.vlan_tag_list.idi_vaddr) + iflib_dma_free(&softc->vnic_info.vlan_tag_list); + SLIST_FOREACH_SAFE(tag, &softc->vnic_info.vlan_tags, next, tmp) + free(tag, M_DEVBUF); + iflib_dma_free(&softc->def_cp_ring_mem); + free(softc->tpa_start, M_DEVBUF); + free(softc->ver_info, M_DEVBUF); + free(softc->nvm_info, M_DEVBUF); + + bnxt_hwrm_func_drv_unrgtr(softc, false); + bnxt_free_hwrm_dma_mem(softc); + BNXT_HWRM_LOCK_DESTROY(softc); + + pci_disable_busmaster(softc->dev); + bnxt_pci_mapping_free(softc); + + return 0; +} + +/* Device configuration */ +static void +bnxt_init(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + int i, j; + int rc; + + rc = bnxt_hwrm_func_reset(softc); + if (rc) + return; + bnxt_clear_ids(softc); + + /* Allocate the default completion ring */ + softc->def_cp_ring.cons = UINT32_MAX; + softc->def_cp_ring.v_bit = 1; + bnxt_mark_cpr_invalid(&softc->def_cp_ring); + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL, + &softc->def_cp_ring.ring, + (uint16_t)HWRM_NA_SIGNATURE, + HWRM_NA_SIGNATURE, true); + if (rc) + goto fail; + + /* And now set the default CP ring as the async CP ring */ + rc = bnxt_hwrm_func_cfg(softc); + if (rc) + goto fail; + + for (i = 0; i < softc->nrxqsets; i++) { + /* Allocate the statistics context */ + rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->rx_cp_rings[i], + softc->rx_stats.idi_paddr + + (sizeof(struct ctx_hw_stats) * i)); + if (rc) + goto fail; + + /* Allocate the completion ring */ + softc->rx_cp_rings[i].cons = UINT32_MAX; + softc->rx_cp_rings[i].v_bit = 1; + softc->rx_cp_rings[i].last_idx = UINT32_MAX; + bnxt_mark_cpr_invalid(&softc->rx_cp_rings[i]); + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL, + &softc->rx_cp_rings[i].ring, (uint16_t)HWRM_NA_SIGNATURE, + HWRM_NA_SIGNATURE, true); + if (rc) + goto fail; + + /* Allocate the RX ring */ + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, + &softc->rx_rings[i], (uint16_t)HWRM_NA_SIGNATURE, + HWRM_NA_SIGNATURE, false); + if (rc) + goto fail; + BNXT_RX_DB(&softc->rx_rings[i], 0); + /* TODO: Cumulus+ doesn't need the double doorbell */ + BNXT_RX_DB(&softc->rx_rings[i], 0); + + /* Allocate the AG ring */ + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_RX, + &softc->ag_rings[i], (uint16_t)HWRM_NA_SIGNATURE, + HWRM_NA_SIGNATURE, false); + if (rc) + goto fail; + BNXT_RX_DB(&softc->rx_rings[i], 0); + /* TODO: Cumulus+ doesn't need the double doorbell */ + BNXT_RX_DB(&softc->ag_rings[i], 0); + + /* Allocate the ring group */ + softc->grp_info[i].stats_ctx = + softc->rx_cp_rings[i].stats_ctx_id; + softc->grp_info[i].rx_ring_id = softc->rx_rings[i].phys_id; + softc->grp_info[i].ag_ring_id = softc->ag_rings[i].phys_id; + softc->grp_info[i].cp_ring_id = + softc->rx_cp_rings[i].ring.phys_id; + rc = bnxt_hwrm_ring_grp_alloc(softc, &softc->grp_info[i]); + if (rc) + goto fail; + + } + + /* Allocate the VNIC RSS context */ + rc = bnxt_hwrm_vnic_ctx_alloc(softc, &softc->vnic_info.rss_id); + if (rc) + goto fail; + + /* Allocate the vnic */ + softc->vnic_info.def_ring_grp = softc->grp_info[0].grp_id; + softc->vnic_info.mru = softc->scctx->isc_max_frame_size; + rc = bnxt_hwrm_vnic_alloc(softc, &softc->vnic_info); + if (rc) + goto fail; + rc = bnxt_hwrm_vnic_cfg(softc, &softc->vnic_info); + if (rc) + goto fail; + rc = bnxt_hwrm_set_filter(softc, &softc->vnic_info); + if (rc) + goto fail; + + /* Enable RSS on the VNICs */ + for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) { + ((uint16_t *) + softc->vnic_info.rss_grp_tbl.idi_vaddr)[i] = + htole16(softc->grp_info[j].grp_id); + if (++j == softc->nrxqsets) + j = 0; + } + + rc = bnxt_hwrm_rss_cfg(softc, &softc->vnic_info, + softc->vnic_info.rss_hash_type); + if (rc) + goto fail; + +#ifdef notyet + /* Enable LRO/TPA/GRO */ + rc = bnxt_hwrm_vnic_tpa_cfg(softc, &softc->vnic_info, + (if_getcapenable(iflib_get_ifp(ctx)) & IFCAP_LRO) ? + HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA : 0); + if (rc) + goto fail; +#endif + + for (i = 0; i < softc->ntxqsets; i++) { + /* Allocate the statistics context */ + rc = bnxt_hwrm_stat_ctx_alloc(softc, &softc->tx_cp_rings[i], + softc->tx_stats.idi_paddr + + (sizeof(struct ctx_hw_stats) * i)); + if (rc) + goto fail; + + /* Allocate the completion ring */ + softc->tx_cp_rings[i].cons = UINT32_MAX; + softc->tx_cp_rings[i].v_bit = 1; + bnxt_mark_cpr_invalid(&softc->tx_cp_rings[i]); + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_CMPL, + &softc->tx_cp_rings[i].ring, (uint16_t)HWRM_NA_SIGNATURE, + HWRM_NA_SIGNATURE, false); + if (rc) + goto fail; + + /* Allocate the TX ring */ + rc = bnxt_hwrm_ring_alloc(softc, + HWRM_RING_ALLOC_INPUT_RING_TYPE_TX, + &softc->tx_rings[i], softc->tx_cp_rings[i].ring.phys_id, + softc->tx_cp_rings[i].stats_ctx_id, false); + if (rc) + goto fail; + BNXT_TX_DB(&softc->tx_rings[i], 0); + /* TODO: Cumulus+ doesn't need the double doorbell */ + BNXT_TX_DB(&softc->tx_rings[i], 0); + } + + bnxt_do_enable_intr(&softc->def_cp_ring); + return; + +fail: + bnxt_hwrm_func_reset(softc); + bnxt_clear_ids(softc); + return; +} + +static void +bnxt_stop(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + + bnxt_do_disable_intr(&softc->def_cp_ring); + bnxt_hwrm_func_reset(softc); + bnxt_clear_ids(softc); + return; +} + +static void +bnxt_multi_set(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + if_t ifp = iflib_get_ifp(ctx); + uint8_t *mta; + int cnt, mcnt; + + mcnt = if_multiaddr_count(ifp, -1); + + if (mcnt > BNXT_MAX_MC_ADDRS) { + softc->vnic_info.rx_mask |= + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; + bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); + } + else { + softc->vnic_info.rx_mask &= + ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; + mta = softc->vnic_info.mc_list.idi_vaddr; + bzero(mta, softc->vnic_info.mc_list.idi_size); + if_multiaddr_array(ifp, mta, &cnt, mcnt); + bus_dmamap_sync(softc->vnic_info.mc_list.idi_tag, + softc->vnic_info.mc_list.idi_map, BUS_DMASYNC_PREWRITE); + softc->vnic_info.mc_list_count = cnt; + softc->vnic_info.rx_mask |= + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST; + if (bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info)) + device_printf(softc->dev, + "set_multi: rx_mask set failed\n"); + } +} + +static int +bnxt_mtu_set(if_ctx_t ctx, uint32_t mtu) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + + if (mtu > BNXT_MAX_MTU) + return EINVAL; + + softc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; + return 0; +} + +static void +bnxt_media_status(if_ctx_t ctx, struct ifmediareq * ifmr) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct bnxt_link_info *link_info = &softc->link_info; + uint8_t phy_type = get_phy_type(softc); + + bnxt_update_link(softc, true); + + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + + if (link_info->link_up) + ifmr->ifm_status |= IFM_ACTIVE; + else + ifmr->ifm_status &= ~IFM_ACTIVE; + + if (link_info->duplex == HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + + switch (link_info->link_speed) { + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB: + ifmr->ifm_active |= IFM_100_T; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: + ifmr->ifm_active |= IFM_1000_KX; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: + ifmr->ifm_active |= IFM_1000_T; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY: + ifmr->ifm_active |= IFM_1000_SGMII; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: + ifmr->ifm_active |= IFM_2500_KX; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: + ifmr->ifm_active |= IFM_2500_T; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + ifmr->ifm_active |= IFM_10G_CR1; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + ifmr->ifm_active |= IFM_10G_KR; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: + ifmr->ifm_active |= IFM_10G_LR; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: + ifmr->ifm_active |= IFM_10G_SR; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: + ifmr->ifm_active |= IFM_10G_KX4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: + ifmr->ifm_active |= IFM_10G_T; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: + ifmr->ifm_active |= IFM_20G_KR2; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + ifmr->ifm_active |= IFM_25G_CR; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + ifmr->ifm_active |= IFM_25G_KR; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: + ifmr->ifm_active |= IFM_25G_SR; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + ifmr->ifm_active |= IFM_40G_CR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + ifmr->ifm_active |= IFM_40G_KR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: + ifmr->ifm_active |= IFM_40G_LR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: + ifmr->ifm_active |= IFM_40G_SR4; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + ifmr->ifm_active |= IFM_50G_CR2; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + ifmr->ifm_active |= IFM_50G_KR2; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + ifmr->ifm_active |= IFM_100G_CR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + ifmr->ifm_active |= IFM_100G_KR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: + ifmr->ifm_active |= IFM_100G_LR4; + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: + ifmr->ifm_active |= IFM_100G_SR4; + break; + default: + ifmr->ifm_active |= IFM_UNKNOWN; + break; + } + default: + return; + } + + if (link_info->pause == (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX)) + ifmr->ifm_active |= (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE); + else if (link_info->pause == HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX) + ifmr->ifm_active |= IFM_ETH_TXPAUSE; + else if (link_info->pause == HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX) + ifmr->ifm_active |= IFM_ETH_RXPAUSE; + + bnxt_report_link(softc); + return; +} + +static int +bnxt_media_change(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct ifmedia *ifm = iflib_get_media(ctx); + struct ifmediareq ifmr; + int rc; + + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return EINVAL; + + switch (IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_100_T: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB; + break; + case IFM_1000_KX: + case IFM_1000_T: + case IFM_1000_SGMII: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB; + break; + case IFM_2500_KX: + case IFM_2500_T: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB; + break; + case IFM_10G_CR1: + case IFM_10G_KR: + case IFM_10G_LR: + case IFM_10G_SR: + case IFM_10G_T: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB; + break; + case IFM_20G_KR2: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB; + break; + case IFM_25G_CR: + case IFM_25G_KR: + case IFM_25G_SR: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB; + break; + case IFM_40G_CR4: + case IFM_40G_KR4: + case IFM_40G_LR4: + case IFM_40G_SR4: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB; + break; + case IFM_50G_CR2: + case IFM_50G_KR2: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB; + break; + case IFM_100G_CR4: + case IFM_100G_KR4: + case IFM_100G_LR4: + case IFM_100G_SR4: + softc->link_info.autoneg &= ~BNXT_AUTONEG_SPEED; + softc->link_info.req_link_speed = + HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB; + break; + default: + device_printf(softc->dev, + "Unsupported media type! Using auto\n"); + /* Fall-through */ + case IFM_AUTO: + // Auto + softc->link_info.autoneg |= BNXT_AUTONEG_SPEED; + break; + } + rc = bnxt_hwrm_set_link_setting(softc, true, true); + bnxt_media_status(softc->ctx, &ifmr); + return rc; +} + +static int +bnxt_promisc_set(if_ctx_t ctx, int flags) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + if_t ifp = iflib_get_ifp(ctx); + int rc; + + if (ifp->if_flags & IFF_ALLMULTI || + if_multiaddr_count(ifp, -1) > BNXT_MAX_MC_ADDRS) + softc->vnic_info.rx_mask |= + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; + else + softc->vnic_info.rx_mask &= + ~HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST; + + if (ifp->if_flags & IFF_PROMISC) + softc->vnic_info.rx_mask |= + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS | + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN; + else + softc->vnic_info.rx_mask &= + ~(HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS | + HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN); + + rc = bnxt_hwrm_cfa_l2_set_rx_mask(softc, &softc->vnic_info); + + return rc; +} + +static uint64_t +bnxt_get_counter(if_ctx_t ctx, ift_counter cnt) +{ + if_t ifp = iflib_get_ifp(ctx); + + if (cnt < IFCOUNTERS) + return if_get_counter_default(ifp, cnt); + + return 0; +} + +static void +bnxt_update_admin_status(if_ctx_t ctx) +{ + /* TODO: do we need to do anything here? */ + return; +} + +static void inline +bnxt_do_enable_intr(struct bnxt_cp_ring *cpr) +{ + if (cpr->ring.phys_id != (uint16_t)HWRM_NA_SIGNATURE) { + /* First time enabling, do not set index */ + if (cpr->cons == UINT32_MAX) + BNXT_CP_ENABLE_DB(&cpr->ring); + else + BNXT_CP_IDX_ENABLE_DB(&cpr->ring, cpr->cons); + } +} + +static void inline +bnxt_do_disable_intr(struct bnxt_cp_ring *cpr) +{ + if (cpr->ring.phys_id != (uint16_t)HWRM_NA_SIGNATURE) + BNXT_CP_DISABLE_DB(&cpr->ring); +} + +/* Enable all interrupts */ +static void +bnxt_intr_enable(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + int i; + + bnxt_do_enable_intr(&softc->def_cp_ring); + for (i = 0; i < softc->nrxqsets; i++) + bnxt_do_enable_intr(&softc->rx_cp_rings[i]); + + return; +} + +/* Enable interrupt for a single queue */ +static int +bnxt_queue_intr_enable(if_ctx_t ctx, uint16_t qid) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + + bnxt_do_enable_intr(&softc->rx_cp_rings[qid]); + return 0; +} + +/* Disable all interrupts */ +static void +bnxt_disable_intr(if_ctx_t ctx) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + int i; + + /* + * NOTE: These TX interrupts should never get enabled, so don't + * update the index + */ + for (i = 0; i < softc->ntxqsets; i++) + bnxt_do_disable_intr(&softc->tx_cp_rings[i]); + for (i = 0; i < softc->nrxqsets; i++) + bnxt_do_disable_intr(&softc->rx_cp_rings[i]); + + return; +} + +static int +bnxt_msix_intr_assign(if_ctx_t ctx, int msix) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + int rc; + int i; + + rc = iflib_irq_alloc_generic(ctx, &softc->def_cp_ring.irq, + softc->def_cp_ring.ring.id + 1, IFLIB_INTR_ADMIN, + bnxt_handle_def_cp, softc, 0, "def_cp"); + if (rc) { + device_printf(iflib_get_dev(ctx), + "Failed to register default completion ring handler\n"); + return rc; + } + + for (i=0; iscctx->isc_nrxqsets; i++) { + rc = iflib_irq_alloc_generic(ctx, &softc->rx_cp_rings[i].irq, + softc->rx_cp_rings[i].ring.id + 1, IFLIB_INTR_RX, + bnxt_handle_rx_cp, &softc->rx_cp_rings[i], i, "rx_cp"); + if (rc) { + device_printf(iflib_get_dev(ctx), + "Failed to register RX completion ring handler\n"); + i--; + goto fail; + } + } + + for (i=0; iscctx->isc_ntxqsets; i++) + iflib_softirq_alloc_generic(ctx, i + 1, IFLIB_INTR_TX, NULL, i, + "tx_cp"); + + return rc; + +fail: + for (; i>=0; i--) + iflib_irq_free(ctx, &softc->rx_cp_rings[i].irq); + iflib_irq_free(ctx, &softc->def_cp_ring.irq); + return rc; +} + +/* + * We're explicitly allowing duplicates here. They will need to be + * removed as many times as they are added. + */ +static void +bnxt_vlan_register(if_ctx_t ctx, uint16_t vtag) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct bnxt_vlan_tag *new_tag; + + new_tag = malloc(sizeof(struct bnxt_vlan_tag), M_DEVBUF, M_NOWAIT); + if (new_tag == NULL) + return; + new_tag->tag = vtag; + new_tag->tpid = 8100; + SLIST_INSERT_HEAD(&softc->vnic_info.vlan_tags, new_tag, next); +}; + +static void +bnxt_vlan_unregister(if_ctx_t ctx, uint16_t vtag) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct bnxt_vlan_tag *vlan_tag; + + SLIST_FOREACH(vlan_tag, &softc->vnic_info.vlan_tags, next) { + if (vlan_tag->tag == vtag) { + SLIST_REMOVE(&softc->vnic_info.vlan_tags, vlan_tag, + bnxt_vlan_tag, next); + free(vlan_tag, M_DEVBUF); + break; + } + } +} + +static int +bnxt_priv_ioctl(if_ctx_t ctx, u_long command, caddr_t data) +{ + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct ifreq *ifr = (struct ifreq *)data; + struct ifreq_buffer *ifbuf = &ifr->ifr_ifru.ifru_buffer; + struct bnxt_ioctl_header *ioh = + (struct bnxt_ioctl_header *)(ifbuf->buffer); + int rc = ENOTSUP; + struct bnxt_ioctl_data *iod = NULL; + + switch (command) { + case SIOCGPRIVATE_0: + if ((rc = priv_check(curthread, PRIV_DRIVER)) != 0) + goto exit; + + iod = malloc(ifbuf->length, M_DEVBUF, M_NOWAIT | M_ZERO); + if (!iod) { + rc = ENOMEM; + goto exit; + } + copyin(ioh, iod, ifbuf->length); + + switch (ioh->type) { + case BNXT_HWRM_NVM_FIND_DIR_ENTRY: + { + struct bnxt_ioctl_hwrm_nvm_find_dir_entry *find = + &iod->find; + + rc = bnxt_hwrm_nvm_find_dir_entry(softc, find->type, + &find->ordinal, find->ext, &find->index, + find->use_index, find->search_opt, + &find->data_length, &find->item_length, + &find->fw_ver); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_READ: + { + struct bnxt_ioctl_hwrm_nvm_read *rd = &iod->read; + struct iflib_dma_info dma_data; + size_t offset; + size_t remain; + size_t csize; + + /* + * Some HWRM versions can't read more than 0x8000 bytes + */ + rc = iflib_dma_alloc(softc->ctx, + min(rd->length, 0x8000), &dma_data, BUS_DMA_NOWAIT); + if (rc) + break; + for (remain = rd->length, offset = 0; + remain && offset < rd->length; offset += 0x8000) { + csize = min(remain, 0x8000); + rc = bnxt_hwrm_nvm_read(softc, rd->index, + rd->offset + offset, csize, &dma_data); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + break; + } + else { + copyout(dma_data.idi_vaddr, + rd->data + offset, csize); + iod->hdr.rc = 0; + } + remain -= csize; + } + if (iod->hdr.rc == 0) + copyout(iod, ioh, ifbuf->length); + + iflib_dma_free(&dma_data); + rc = 0; + goto exit; + } + case BNXT_HWRM_FW_RESET: + { + struct bnxt_ioctl_hwrm_fw_reset *rst = + &iod->reset; + + rc = bnxt_hwrm_fw_reset(softc, rst->processor, + &rst->selfreset); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_FW_QSTATUS: + { + struct bnxt_ioctl_hwrm_fw_qstatus *qstat = + &iod->status; + + rc = bnxt_hwrm_fw_qstatus(softc, qstat->processor, + &qstat->selfreset); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_WRITE: + { + struct bnxt_ioctl_hwrm_nvm_write *wr = + &iod->write; + + rc = bnxt_hwrm_nvm_write(softc, wr->data, true, + wr->type, wr->ordinal, wr->ext, wr->attr, + wr->option, wr->data_length, wr->keep, + &wr->item_length, &wr->index); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_ERASE_DIR_ENTRY: + { + struct bnxt_ioctl_hwrm_nvm_erase_dir_entry *erase = + &iod->erase; + + rc = bnxt_hwrm_nvm_erase_dir_entry(softc, erase->index); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_GET_DIR_INFO: + { + struct bnxt_ioctl_hwrm_nvm_get_dir_info *info = + &iod->dir_info; + + rc = bnxt_hwrm_nvm_get_dir_info(softc, &info->entries, + &info->entry_length); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_GET_DIR_ENTRIES: + { + struct bnxt_ioctl_hwrm_nvm_get_dir_entries *get = + &iod->dir_entries; + struct iflib_dma_info dma_data; + + rc = iflib_dma_alloc(softc->ctx, get->max_size, + &dma_data, BUS_DMA_NOWAIT); + if (rc) + break; + rc = bnxt_hwrm_nvm_get_dir_entries(softc, &get->entries, + &get->entry_length, &dma_data); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + copyout(dma_data.idi_vaddr, get->data, + get->entry_length * get->entries); + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + iflib_dma_free(&dma_data); + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_VERIFY_UPDATE: + { + struct bnxt_ioctl_hwrm_nvm_verify_update *vrfy = + &iod->verify; + + rc = bnxt_hwrm_nvm_verify_update(softc, vrfy->type, + vrfy->ordinal, vrfy->ext); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_INSTALL_UPDATE: + { + struct bnxt_ioctl_hwrm_nvm_install_update *inst = + &iod->install; + + rc = bnxt_hwrm_nvm_install_update(softc, + inst->install_type, &inst->installed_items, + &inst->result, &inst->problem_item, + &inst->reset_required); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_NVM_MODIFY: + { + struct bnxt_ioctl_hwrm_nvm_modify *mod = &iod->modify; + + rc = bnxt_hwrm_nvm_modify(softc, mod->index, + mod->offset, mod->data, true, mod->length); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_FW_GET_TIME: + { + struct bnxt_ioctl_hwrm_fw_get_time *gtm = + &iod->get_time; + + rc = bnxt_hwrm_fw_get_time(softc, >m->year, + >m->month, >m->day, >m->hour, >m->minute, + >m->second, >m->millisecond, >m->zone); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + case BNXT_HWRM_FW_SET_TIME: + { + struct bnxt_ioctl_hwrm_fw_set_time *stm = + &iod->set_time; + + rc = bnxt_hwrm_fw_set_time(softc, stm->year, + stm->month, stm->day, stm->hour, stm->minute, + stm->second, stm->millisecond, stm->zone); + if (rc) { + iod->hdr.rc = rc; + copyout(&iod->hdr.rc, &ioh->rc, + sizeof(ioh->rc)); + } + else { + iod->hdr.rc = 0; + copyout(iod, ioh, ifbuf->length); + } + + rc = 0; + goto exit; + } + } + break; + } + +exit: + if (iod) + free(iod, M_DEVBUF); + return rc; +} + +/* + * Support functions + */ +static int +bnxt_probe_phy(struct bnxt_softc *softc) +{ + struct bnxt_link_info *link_info = &softc->link_info; + int rc = 0; + + rc = bnxt_update_link(softc, false); + if (rc) { + device_printf(softc->dev, + "Probe phy can't update link (rc: %x)\n", rc); + return (rc); + } + + /*initialize the ethool setting copy with NVM settings */ + if (link_info->auto_mode != HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) + link_info->autoneg |= BNXT_AUTONEG_SPEED; + + if (link_info->auto_pause & (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX)) { + if (link_info->auto_pause == ( + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX)) + link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; + link_info->req_flow_ctrl = link_info->auto_pause; + } else if (link_info->force_pause & ( + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX)) { + link_info->req_flow_ctrl = link_info->force_pause; + } + link_info->req_duplex = link_info->duplex_setting; + if (link_info->autoneg & BNXT_AUTONEG_SPEED) + link_info->req_link_speed = link_info->auto_link_speed; + else + link_info->req_link_speed = link_info->force_link_speed; + return (rc); +} + +static void +bnxt_add_media_types(struct bnxt_softc *softc) +{ + struct bnxt_link_info *link_info = &softc->link_info; + uint16_t supported; + uint8_t phy_type = get_phy_type(softc); + + supported = link_info->support_speeds; + + /* Auto is always supported */ + ifmedia_add(softc->media, IFM_ETHER | IFM_AUTO, 0, NULL); + + if (softc->flags & BNXT_FLAG_NPAR) + return; + + switch (phy_type) { + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_100G_CR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_50G_CR2, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_40G_CR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_25G_CR, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_CR1, 0, + NULL); + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN: + /* Auto only */ + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_100G_KR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_50G_KR2, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_40G_KR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_25G_KR, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_20G_KR2, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_KR, 0, + NULL); + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_100G_LR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_40G_LR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_LR, 0, + NULL); + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_100G_SR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_40G_SR4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_25G_SR, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_SR, 0, + NULL); + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_KX4, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_2500_KX, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_1000_KX, 0, + NULL); + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET: + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10_T, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB) + ifmedia_add(softc->media, IFM_ETHER | IFM_100_T, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_1000_T, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_2500_T, 0, + NULL); + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_10G_T, 0, + NULL); + break; + case HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY: + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) + ifmedia_add(softc->media, IFM_ETHER | IFM_1000_SGMII, 0, + NULL); + break; + } + + return; +} + +static int +bnxt_map_bar(struct bnxt_softc *softc, struct bnxt_bar_info *bar, int bar_num, bool shareable) +{ + uint32_t flag; + + if (bar->res != NULL) { + device_printf(softc->dev, "Bar %d already mapped\n", bar_num); + return EDOOFUS; + } + + bar->rid = PCIR_BAR(bar_num); + flag = RF_ACTIVE; + if (shareable) + flag |= RF_SHAREABLE; + + if ((bar->res = + bus_alloc_resource_any(softc->dev, + SYS_RES_MEMORY, + &bar->rid, + flag)) == NULL) { + device_printf(softc->dev, + "PCI BAR%d mapping failure\n", bar_num); + return (ENXIO); + } + bar->tag = rman_get_bustag(bar->res); + bar->handle = rman_get_bushandle(bar->res); + bar->size = rman_get_size(bar->res); + + return 0; +} + +static int +bnxt_pci_mapping(struct bnxt_softc *softc) +{ + int rc; + + rc = bnxt_map_bar(softc, &softc->hwrm_bar, 0, true); + if (rc) + return rc; + + rc = bnxt_map_bar(softc, &softc->doorbell_bar, 2, false); + + return rc; +} + +static void +bnxt_pci_mapping_free(struct bnxt_softc *softc) +{ + if (softc->hwrm_bar.res != NULL) + bus_release_resource(softc->dev, SYS_RES_MEMORY, + softc->hwrm_bar.rid, softc->hwrm_bar.res); + softc->hwrm_bar.res = NULL; + + if (softc->doorbell_bar.res != NULL) + bus_release_resource(softc->dev, SYS_RES_MEMORY, + softc->doorbell_bar.rid, softc->doorbell_bar.res); + softc->doorbell_bar.res = NULL; +} + +static int +bnxt_update_link(struct bnxt_softc *softc, bool chng_link_state) +{ + struct bnxt_link_info *link_info = &softc->link_info; + uint8_t link_up = link_info->link_up; + int rc = 0; + + rc = bnxt_hwrm_port_phy_qcfg(softc); + if (rc) + goto exit; + + /* TODO: need to add more logic to report VF link */ + if (chng_link_state) { + if (link_info->phy_link_status == + HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) + link_info->link_up = 1; + else + link_info->link_up = 0; + if (link_up != link_info->link_up) + bnxt_report_link(softc); + } else { + /* always link down if not require to update link state */ + link_info->link_up = 0; + } + +exit: + return rc; +} + +void +bnxt_report_link(struct bnxt_softc *softc) +{ + const char *duplex = NULL, *flow_ctrl = NULL; + + if (softc->link_info.link_up == softc->link_info.last_link_up) { + if (!softc->link_info.link_up) + return; + if (softc->link_info.pause == softc->link_info.last_pause && + softc->link_info.duplex == softc->link_info.last_duplex) + return; + } + + if (softc->link_info.link_up) { + if (softc->link_info.duplex == + HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_FULL) + duplex = "full duplex"; + else + duplex = "half duplex"; + if (softc->link_info.pause == ( + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX)) + flow_ctrl = "FC - receive & transmit"; + else if (softc->link_info.pause == + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX) + flow_ctrl = "FC - transmit"; + else if (softc->link_info.pause == + HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX) + flow_ctrl = "FC - receive"; + else + flow_ctrl = "none"; + iflib_link_state_change(softc->ctx, LINK_STATE_UP, + IF_Gbps(100)); + device_printf(softc->dev, "Link is UP %s, %s\n", duplex, + flow_ctrl); + } else { + iflib_link_state_change(softc->ctx, LINK_STATE_DOWN, + bnxt_get_baudrate(&softc->link_info)); + device_printf(softc->dev, "Link is Down\n"); + } + + softc->link_info.last_link_up = softc->link_info.link_up; + softc->link_info.last_pause = softc->link_info.pause; + softc->link_info.last_duplex = softc->link_info.duplex; +} + +static int +bnxt_handle_rx_cp(void *arg) +{ + struct bnxt_cp_ring *cpr = arg; + + /* Disable further interrupts for this queue */ + BNXT_CP_DISABLE_DB(&cpr->ring); + return FILTER_SCHEDULE_THREAD; +} + +static int +bnxt_handle_def_cp(void *arg) +{ + struct bnxt_softc *softc = arg; + + BNXT_CP_DISABLE_DB(&softc->def_cp_ring.ring); + GROUPTASK_ENQUEUE(&softc->def_cp_task); + return FILTER_HANDLED; +} + +static void +bnxt_clear_ids(struct bnxt_softc *softc) +{ + int i; + + softc->def_cp_ring.stats_ctx_id = HWRM_NA_SIGNATURE; + softc->def_cp_ring.ring.phys_id = (uint16_t)HWRM_NA_SIGNATURE; + for (i = 0; i < softc->ntxqsets; i++) { + softc->tx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; + softc->tx_cp_rings[i].ring.phys_id = + (uint16_t)HWRM_NA_SIGNATURE; + softc->tx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + } + for (i = 0; i < softc->nrxqsets; i++) { + softc->rx_cp_rings[i].stats_ctx_id = HWRM_NA_SIGNATURE; + softc->rx_cp_rings[i].ring.phys_id = + (uint16_t)HWRM_NA_SIGNATURE; + softc->rx_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->ag_rings[i].phys_id = (uint16_t)HWRM_NA_SIGNATURE; + softc->grp_info[i].grp_id = (uint16_t)HWRM_NA_SIGNATURE; + } + softc->vnic_info.filter_id = -1; + softc->vnic_info.id = (uint16_t)HWRM_NA_SIGNATURE; + softc->vnic_info.rss_id = (uint16_t)HWRM_NA_SIGNATURE; + memset(softc->vnic_info.rss_grp_tbl.idi_vaddr, 0xff, + softc->vnic_info.rss_grp_tbl.idi_size); +} + +static void +bnxt_mark_cpr_invalid(struct bnxt_cp_ring *cpr) +{ + struct cmpl_base *cmp = (void *)cpr->ring.vaddr; + int i; + + for (i = 0; i < cpr->ring.ring_size; i++) + cmp[i].info3_v = !cpr->v_bit; +} + +static void +bnxt_handle_async_event(struct bnxt_softc *softc, struct cmpl_base *cmpl) +{ + struct hwrm_async_event_cmpl *ae = (void *)cmpl; + uint16_t async_id = le16toh(ae->event_id); + struct ifmediareq ifmr; + + switch (async_id) { + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: + bnxt_media_status(softc->ctx, &ifmr); + break; + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE: + case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR: + device_printf(softc->dev, + "Unhandled async completion type %u\n", async_id); + break; + default: + device_printf(softc->dev, + "Unknown async completion type %u\n", async_id); + break; + } +} + +static void +bnxt_def_cp_task(void *context) +{ + if_ctx_t ctx = context; + struct bnxt_softc *softc = iflib_get_softc(ctx); + struct bnxt_cp_ring *cpr = &softc->def_cp_ring; + + /* Handle completions on the default completion ring */ + struct cmpl_base *cmpl; + uint32_t cons = cpr->cons; + bool v_bit = cpr->v_bit; + bool last_v_bit; + uint32_t last_cons; + uint16_t type; + + for (;;) { + last_cons = cons; + last_v_bit = v_bit; + NEXT_CP_CONS_V(&cpr->ring, cons, v_bit); + cmpl = &((struct cmpl_base *)cpr->ring.vaddr)[cons]; + + if (!CMP_VALID(cmpl, v_bit)) + break; + + type = le16toh(cmpl->type) & CMPL_BASE_TYPE_MASK; + switch (type) { + case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: + bnxt_handle_async_event(softc, cmpl); + break; + case CMPL_BASE_TYPE_TX_L2: + case CMPL_BASE_TYPE_RX_L2: + case CMPL_BASE_TYPE_RX_AGG: + case CMPL_BASE_TYPE_RX_TPA_START: + case CMPL_BASE_TYPE_RX_TPA_END: + case CMPL_BASE_TYPE_STAT_EJECT: + case CMPL_BASE_TYPE_HWRM_DONE: + case CMPL_BASE_TYPE_HWRM_FWD_REQ: + case CMPL_BASE_TYPE_HWRM_FWD_RESP: + case CMPL_BASE_TYPE_CQ_NOTIFICATION: + case CMPL_BASE_TYPE_SRQ_EVENT: + case CMPL_BASE_TYPE_DBQ_EVENT: + case CMPL_BASE_TYPE_QP_EVENT: + case CMPL_BASE_TYPE_FUNC_EVENT: + device_printf(softc->dev, + "Unhandled completion type %u\n", type); + break; + default: + device_printf(softc->dev, + "Unknown completion type %u\n", type); + break; + } + } + + cpr->cons = last_cons; + cpr->v_bit = last_v_bit; + BNXT_CP_IDX_ENABLE_DB(&cpr->ring, cpr->cons); +} + +static uint8_t +get_phy_type(struct bnxt_softc *softc) +{ + struct bnxt_link_info *link_info = &softc->link_info; + uint8_t phy_type = link_info->phy_type; + uint16_t supported; + + if (phy_type != HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN) + return phy_type; + + /* Deduce the phy type from the media type and supported speeds */ + supported = link_info->support_speeds; + + if (link_info->media_type == + HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) + return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET; + if (link_info->media_type == + HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC) { + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) + return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX; + if (supported & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) + return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR; + return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR; + } + if (link_info->media_type == + HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE) + return HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR; + + return phy_type; +} + +bool +bnxt_check_hwrm_version(struct bnxt_softc *softc) +{ + char buf[16]; + + sprintf(buf, "%hhu.%hhu.%hhu", softc->ver_info->hwrm_min_major, + softc->ver_info->hwrm_min_minor, softc->ver_info->hwrm_min_update); + if (softc->ver_info->hwrm_min_major > softc->ver_info->hwrm_if_major) { + device_printf(softc->dev, + "WARNING: HWRM version %s is too old (older than %s)\n", + softc->ver_info->hwrm_if_ver, buf); + return false; + } + else if(softc->ver_info->hwrm_min_major == + softc->ver_info->hwrm_if_major) { + if (softc->ver_info->hwrm_min_minor > + softc->ver_info->hwrm_if_minor) { + device_printf(softc->dev, + "WARNING: HWRM version %s is too old (older than %s)\n", + softc->ver_info->hwrm_if_ver, buf); + return false; + } + else if (softc->ver_info->hwrm_min_minor == + softc->ver_info->hwrm_if_minor) { + if (softc->ver_info->hwrm_min_update > + softc->ver_info->hwrm_if_update) { + device_printf(softc->dev, + "WARNING: HWRM version %s is too old (older than %s)\n", + softc->ver_info->hwrm_if_ver, buf); + return false; + } + } + } + return true; +} + +static uint64_t +bnxt_get_baudrate(struct bnxt_link_info *link) +{ + switch (link->link_speed) { + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB: + return IF_Mbps(100); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB: + return IF_Gbps(1); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB: + return IF_Gbps(2); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB: + return IF_Mbps(2500); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB: + return IF_Gbps(10); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB: + return IF_Gbps(20); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB: + return IF_Gbps(25); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB: + return IF_Gbps(40); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB: + return IF_Gbps(50); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB: + return IF_Gbps(100); + case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB: + return IF_Mbps(10); + } + return IF_Gbps(100); +} Index: sys/modules/Makefile =================================================================== --- sys/modules/Makefile +++ sys/modules/Makefile @@ -57,6 +57,7 @@ ${_bios} \ ${_bktr} \ ${_bm} \ + bnxt \ bridgestp \ bwi \ bwn \ Index: sys/modules/bnxt/Makefile =================================================================== --- /dev/null +++ sys/modules/bnxt/Makefile @@ -0,0 +1,14 @@ +#$FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/bnxt + +KMOD = if_bnxt +SRCS = device_if.h bus_if.h pci_if.h pci_iov_if.h ifdi_if.h +SRCS += opt_inet.h opt_inet6.h opt_rss.h +SRCS += bnxt_txrx.c if_bnxt.c +SRCS += bnxt_hwrm.c bnxt_hwrm.h +SRCS += bnxt_sysctl.c bnxt_sysctl.h + +CFLAGS+= -DIFLIB + +.include