Index: emulators/Makefile
===================================================================
--- emulators/Makefile
+++ emulators/Makefile
@@ -124,6 +124,8 @@
     SUBDIR += qtemu
     SUBDIR += quasi88
     SUBDIR += raine
+    SUBDIR += riscv-fesvr
+    SUBDIR += riscv-isa-sim
     SUBDIR += rtc
     SUBDIR += rubygem-fission
     SUBDIR += simh
Index: emulators/riscv-fesvr/Makefile
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/Makefile
@@ -0,0 +1,25 @@
+# Created by: sbruno
+# $FreeBSD$
+
+PORTNAME=	riscv-fesvr
+PORTVERSION=	0.0.g2016.08.15
+CATEGORIES=	emulators
+MASTER_SITES=	GH
+
+USE_GITHUB=     yes
+GH_ACCOUNT=     freebsd-riscv
+GH_PROJECT=     ${PORTNAME}
+GH_TAGNAME=	75d2fe3
+
+MAINTAINER=	sbruno@FreeBSD.org
+COMMENT=	Library for riscv stuffs
+
+LICENSE=	BSD3CLAUSE
+LICENSE_FILE=	${WRKSRC}/LICENSE
+
+USES=           pkgconfig gmake libtool shebangfix
+SHEBANG_FILES=	scripts/vcs-version.sh
+GNU_CONFIGURE=  yes
+USE_LDCONFIG=   yes
+
+.include <bsd.port.mk>
Index: emulators/riscv-fesvr/distinfo
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/distinfo
@@ -0,0 +1,2 @@
+SHA256 (freebsd-riscv-riscv-fesvr-0.0.g2016.08.15-75d2fe3_GH0.tar.gz) = 8332fb51fe9d4d45e80a7dbc9f5a247e3efacb4402095dd94a5a017fd2e913e7
+SIZE (freebsd-riscv-riscv-fesvr-0.0.g2016.08.15-75d2fe3_GH0.tar.gz) = 100856
Index: emulators/riscv-fesvr/files/patch-Makefile.in
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/files/patch-Makefile.in
@@ -0,0 +1,11 @@
+--- Makefile.in.orig	2016-08-16 09:21:26 UTC
++++ Makefile.in
+@@ -57,7 +57,7 @@ ifeq ($(enable_stow),yes)
+   stow_pkg_dir := $(prefix)/pkgs
+   INSTALLDIR ?= $(DESTDIR)/$(stow_pkg_dir)/$(project_name)-$(project_ver)
+ else
+-  INSTALLDIR ?= $(DESTDIR)/$(prefix)
++  INSTALLDIR ?= $(DESTDIR)$(prefix)
+ endif
+ 
+ install_hdrs_dir := $(INSTALLDIR)/include/$(project_name)
Index: emulators/riscv-fesvr/pkg-descr
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/pkg-descr
@@ -0,0 +1,5 @@
+RISC-V Frontend Server
+
+This repository contains the front-end server library, which facilitates
+communication between a host machine and a RISC-V target machine. It is usually
+not meant to be used as a standalone package.
Index: emulators/riscv-fesvr/pkg-plist
===================================================================
--- /dev/null
+++ emulators/riscv-fesvr/pkg-plist
@@ -0,0 +1,17 @@
+include/fesvr/device.h
+include/fesvr/option_parser.h
+include/fesvr/dtm.h
+include/fesvr/htif.h
+include/fesvr/elfloader.h
+include/fesvr/context.h
+include/fesvr/rfb.h
+include/fesvr/configstring.h
+include/fesvr/term.h
+include/fesvr/syscall.h
+include/fesvr/memif.h
+include/fesvr/elf.h
+include/fesvr/htif_pthread.h
+include/fesvr/htif_hexwriter.h
+lib/pkgconfig/riscv-fesvr.pc
+lib/libfesvr.so
+bin/elf2hex
Index: emulators/riscv-isa-sim/Makefile
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/Makefile
@@ -0,0 +1,33 @@
+# Created by: sbruno
+# $FreeBSD$
+
+PORTNAME=	riscv-isa-sim
+PORTVERSION=	0.0.g2016.08.15
+CATEGORIES=	emulators
+MASTER_SITES=	GH
+
+USE_GITHUB=     yes
+GH_ACCOUNT=     freebsd-riscv
+GH_PROJECT=     ${PORTNAME}
+GH_TAGNAME=	b81aac8
+
+MAINTAINER=	sbruno@FreeBSD.org
+COMMENT=	Library for riscv stuffs
+
+LICENSE=	BSD3CLAUSE
+LICENSE_FILE=	${WRKSRC}/LICENSE
+
+HAS_CONFIGURE=	yes
+
+USES=		pkgconfig gmake shebangfix compiler:c++11-lang
+SHEBANG_FILES=  scripts/vcs-version.sh
+
+LIB_DEPENDS+= libfesvr.so:emulators/riscv-fesvr
+
+LDFLAGS+=	-L/usr/local/lib
+CFLAGS+=	-I/usr/local/include
+
+post-extract:
+	@${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp	
+
+.include <bsd.port.mk>
Index: emulators/riscv-isa-sim/distinfo
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/distinfo
@@ -0,0 +1,2 @@
+SHA256 (freebsd-riscv-riscv-isa-sim-0.0.g2016.08.15-b81aac8_GH0.tar.gz) = dde5fede4e862ffe4c55e01ba84f8a2e65d8a2b78aabce0f255a7f7186c95f39
+SIZE (freebsd-riscv-riscv-isc-sim-0.0.g2016.08.15-b81aac8_GH0.tar.gz) = 187362
Index: emulators/riscv-isa-sim/files/patch-Makefile.in
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-Makefile.in
@@ -0,0 +1,19 @@
+--- Makefile.in.orig	2016-08-01 15:40:47 UTC
++++ Makefile.in
+@@ -188,13 +188,13 @@ _$(1).cc :
+ 
+ # Build the object files for this subproject
+ 
+-$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs))
++$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs))
+ $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs))
+ $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
+ $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
+ $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs))
+-$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs))
+-$$($(2)_pch) : %.h.gch : %.h
++$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs))
++$$($(2)_pch) : %.h.gch : %.hpp
+ 	$(COMPILE) $$< -o $$@
+ # If using clang, don't depend (and thus don't build) precompiled headers
+ $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))
Index: emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
@@ -0,0 +1,10 @@
+--- riscv/insn_template.cc.orig	2016-08-01 15:40:47 UTC
++++ riscv/insn_template.cc
+@@ -1,6 +1,6 @@
+ // See LICENSE for license details.
+ 
+-#include "insn_template.h"
++#include "insn_template.hpp"
+ 
+ reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
+ {
Index: emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
@@ -0,0 +1,18 @@
+--- riscv/riscv.mk.in.orig	2016-08-01 15:40:47 UTC
++++ riscv/riscv.mk.in
+@@ -21,13 +21,13 @@ riscv_hdrs = \
+ 	tracer.h \
+ 	extension.h \
+ 	rocc.h \
+-	insn_template.h \
++	insn_template.hpp \
+ 	mulhi.h \
+ 	gdbserver.h \
+ 	debug_module.h \
+ 
+ riscv_precompiled_hdrs = \
+-	insn_template.h \
++	insn_template.hpp \
+ 
+ riscv_srcs = \
+ 	processor.cc \
Index: emulators/riscv-isa-sim/pkg-descr
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/pkg-descr
@@ -0,0 +1,5 @@
+RISC-V Frontend Server
+
+This repository contains the front-end server library, which facilitates
+communication between a host machine and a RISC-V target machine. It is usually
+not meant to be used as a standalone package.
Index: emulators/riscv-isa-sim/pkg-plist
===================================================================
--- /dev/null
+++ emulators/riscv-isa-sim/pkg-plist
@@ -0,0 +1,39 @@
+include/spike/extension.h
+include/spike/disasm.h
+include/spike/icache.h
+include/spike/rocc.h
+include/spike/softfloat.h
+include/spike/processor.h
+include/spike/primitiveTypes.h
+include/spike/cachesim.h
+include/spike/decode.h
+include/spike/trap.h
+include/spike/devices.h
+include/spike/encoding.h
+include/spike/mulhi.h
+include/spike/insn_list.h
+include/spike/gdbserver.h
+include/spike/debug_module.h
+include/spike/specialize.h
+include/spike/softfloat_types.h
+include/spike/mmu.h
+include/spike/internals.h
+include/spike/insn_template.hpp
+include/spike/sim.h
+include/spike/memtracer.h
+include/spike/primitives.h
+include/spike/common.h
+include/spike/tracer.h
+include/spike/config.h
+lib/libdummy_rocc.so
+lib/libspike_main.so
+lib/libriscv.so
+lib/libsoftfloat.so
+lib/pkgconfig/riscv-dummy_rocc.pc
+lib/pkgconfig/riscv-riscv.pc
+lib/pkgconfig/riscv-spike_main.pc
+lib/pkgconfig/riscv-softfloat.pc
+bin/xspike
+bin/termios-xspike
+bin/spike-dasm
+bin/spike