Index: sys/boot/fdt/dts/arm/armada-380.dtsi =================================================================== --- sys/boot/fdt/dts/arm/armada-380.dtsi +++ sys/boot/fdt/dts/arm/armada-380.dtsi @@ -74,80 +74,90 @@ }; pcie-controller { - compatible = "marvell,armada-370-pcie"; + compatible = "mrvl,pcie-ctrl", "marvell,armada-370-pcie"; status = "disabled"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - + ranges = <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ + 0x82000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe8) 0xf1300000 0 0x00100000 /* Port 0 IO */ + 0x82000000 0x0 0xf1400000 MBUS_ID(0x08, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ + 0x82000000 0x0 0xf1500000 MBUS_ID(0x08, 0xe8) 0xf1500000 0 0x00100000 /* Port 1 IO */ + 0x82000000 0x0 0xf1600000 MBUS_ID(0x08, 0xe8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ + 0x82000000 0x0 0xf1700000 MBUS_ID(0x08, 0xe8) 0xf1700000 0 0x00100000 /* Port 2 IO */ + >; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; /* x1 port */ pcie@1,0 { + compatible = "mrvl,pcie"; + status = "disabled"; device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; + #interrupt-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; + #address-cells = <3>; + port-id = <0>; + reg = <0x0 0x0 0x80000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1300000 0x0 0xf1300000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH + >; }; /* x1 port */ pcie@2,0 { + compatible = "mrvl,pcie"; + status = "disabled"; device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; + #interrupt-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; + #address-cells = <3>; + port-id = <1>; + reg = <0x0 0x0 0x40000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1400000 0x0 0xf1400000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1500000 0x0 0xf1500000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH + >; }; /* x1 port */ pcie@3,0 { + compatible = "mrvl,pcie"; + status = "disabled"; device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; + #interrupt-cells = <3>; #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; + #address-cells = <3>; + port-id = <2>; + reg = <0x0 0x0 0x44000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1600000 0x0 0xf1600000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1700000 0x0 0xf1700000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + >; }; }; }; Index: sys/boot/fdt/dts/arm/armada-385.dtsi =================================================================== --- sys/boot/fdt/dts/arm/armada-385.dtsi +++ sys/boot/fdt/dts/arm/armada-385.dtsi @@ -77,5 +77,124 @@ compatible = "marvell,mv88f6820-pinctrl"; }; }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x0 0xf1200000 MBUS_ID(0x08, 0xe8) 0xf1200000 0 0x00100000 /* Port 0 MEM */ + 0x82000000 0x0 0xf1300000 MBUS_ID(0x08, 0xe8) 0xf1300000 0 0x00100000 /* Port 0 IO */ + 0x82000000 0x0 0xf1400000 MBUS_ID(0x08, 0xe8) 0xf1400000 0 0x00100000 /* Port 1 MEM */ + 0x82000000 0x0 0xf1500000 MBUS_ID(0x08, 0xe8) 0xf1500000 0 0x00100000 /* Port 1 IO */ + 0x82000000 0x0 0xf1600000 MBUS_ID(0x08, 0xe8) 0xf1600000 0 0x00100000 /* Port 2 MEM */ + 0x82000000 0x0 0xf1700000 MBUS_ID(0x08, 0xe8) 0xf1700000 0 0x00100000 /* Port 2 IO */ + 0x82000000 0x0 0xf1800000 MBUS_ID(0x08, 0xe8) 0xf1800000 0 0x00100000 /* Port 3 MEM */ + 0x82000000 0x0 0xf1900000 MBUS_ID(0x08, 0xe8) 0xf1900000 0 0x00100000 /* Port 3 IO */ + >; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + /* + * This port can be either x4 or x1. When + * configured in x4 by the bootloader, then + * pcie@4,0 is not available. + */ + pcie@1,0 { + compatible = "mrvl,pcie"; + status = "disabled"; + device_type = "pci"; + #interrupt-cells = <3>; + #size-cells = <2>; + #address-cells = <3>; + port-id = <0>; + reg = <0x0 0x0 0x80000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1300000 0x0 0xf1300000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH + >; + }; + + /* x1 port */ + pcie@2,0 { + compatible = "mrvl,pcie"; + status = "disabled"; + device_type = "pci"; + #interrupt-cells = <3>; + #size-cells = <2>; + #address-cells = <3>; + port-id = <1>; + reg = <0x0 0x0 0x40000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1400000 0x0 0xf1400000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1500000 0x0 0xf1500000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH + >; + }; + + /* x1 port */ + pcie@3,0 { + compatible = "mrvl,pcie"; + status = "disabled"; + device_type = "pci"; + #interrupt-cells = <3>; + #size-cells = <2>; + #address-cells = <3>; + port-id = <2>; + reg = <0x0 0x0 0x44000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1600000 0x0 0xf1600000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1700000 0x0 0xf1700000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + >; + }; + + /* + * x1 port only available when pcie@1,0 is + * configured as a x1 port + */ + pcie@4,0 { + compatible = "mrvl,pcie"; + status = "disabled"; + device_type = "pci"; + #interrupt-cells = <3>; + #size-cells = <2>; + #address-cells = <3>; + port-id = <3>; + reg = <0x0 0x0 0x48000 0x0 0x2000>; + bus-range = <0 255>; + ranges = <0x82000000 0x0 0x0 0xf1800000 0x0 0xf1800000 0x0 0x00100000 + 0x81000000 0x0 0x0 0xf1900000 0x0 0xf1900000 0x0 0x00100000>; + interrupt-parent = <&gic>; + interrupts = ; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = < + 0x0000 0x0 0x0 0x1 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH + >; + }; + }; }; + }; Index: sys/boot/fdt/dts/arm/armada-388-gp.dts =================================================================== --- sys/boot/fdt/dts/arm/armada-388-gp.dts +++ sys/boot/fdt/dts/arm/armada-388-gp.dts @@ -239,12 +239,33 @@ gpio-fan,speed-map = < 0 0 3000 1>; }; - }; + pcie-controller { + status = "okay"; + /* + * One PCIe units is accessible through + * standard PCIe slot on the board. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; - pci0: pcie@f1080000 { - status = "okay"; + /* + * The two other PCIe units are accessible + * through mini PCIe slot on the board. + */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; Index: sys/boot/fdt/dts/arm/armada-38x.dtsi =================================================================== --- sys/boot/fdt/dts/arm/armada-38x.dtsi +++ sys/boot/fdt/dts/arm/armada-38x.dtsi @@ -624,25 +624,6 @@ }; }; - pci0: pcie@f1080000 { - compatible = "mrvl,pcie"; - status = "disabled"; - device_type = "pci"; - #interrupt-cells = <3>; - #size-cells = <2>; - #address-cells = <3>; - reg = <0xf1080000 0x2000>; - bus-range = <0 255>; - ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000 - 0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>; - interrupt-parent = <&gic>; - interrupts = ; - interrupt-map-mask = <0xf800 0x0 0x0 0x7>; - interrupt-map = < - 0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH - >; - }; - clocks { /* 2 GHz fixed main PLL */ mainpll: mainpll {