Index: sys/boot/fdt/dts/arm/armada-388-clearfog.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/arm/armada-388-clearfog.dts
@@ -0,0 +1,209 @@
+/*
+* Device Tree file for SolidRun's ClearFog-a1 board
+*
+* Nadav Haklai <nadavh@marvell.com>
+*
+* This file is licensed under the terms of the GNU General Public
+* License version 2.  This program is licensed "as is" without any
+* warranty of any kind, whether express or implied.
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-388.dtsi"
+
+/ {
+	model = "SolidRun ClearFog a1 board";
+	compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1024 MB */
+	};
+
+	soc {
+		ranges = <0 0 0xf1000000 0x100000>;
+
+		internal-regs {
+			ranges;
+
+			crypto@90000 {
+				status = "okay";
+			};
+			crypto@92000 {
+				status = "okay";
+			};
+
+			ethernet@30000 {
+				status = "okay";
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			ethernet@34000 {
+				status = "okay";
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			ethernet@70000 {
+				pinctrl-names = "default";
+				/*
+				 * The Reference Clock 0 is used to provide a
+				 * clock to the PHY
+				 */
+				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+				status = "okay";
+				phy-handle = <&phy0>;
+				phy-mode = "rgmii-id";
+				mdio@72004 {
+					pinctrl-names = "default";
+					pinctrl-0 = <&mdio_pins>;
+
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+
+			};
+
+			i2c0: i2c@11000 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			i2c1: i2c@11100 {
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+
+			sata@a8000 {
+				status = "okay";
+			};
+
+			sata@e0000 {
+				status = "okay";
+			};
+
+			sdhci@d8000 {
+				broken-cd;
+				wp-inverted;
+				bus-width = <4>;
+				status = "okay";
+				no-1-8-v;
+			};
+
+			serial@12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+
+			spi1: spi@10680 {
+				pinctrl-0 = <&spi1_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "w25q32";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <3000000>;
+				};
+			};
+
+			usb3@f8000 {
+				status = "okay";
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+			/*
+				* The two PCIe units are accessible through
+				* standard PCIe slots on the board.
+				*/
+			pcie@2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+			pcie@3,0 {
+				/* Port 2, Lane 0 */
+				status = "okay";
+			};
+		};
+	};
+	dsa@0 {
+		compatible = "marvell,dsa";
+		dsa,ethernet = <&eth1>;
+		dsa,mii-bus = <&mdio>;
+		pinctrl-names = "default";
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		switch@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <4 0>;
+
+			port@0 {
+				reg = <0>;
+				label = "lan1";
+				vlangroup = <0>;
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan2";
+				vlangroup = <0>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan3";
+				vlangroup = <0>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "lan4";
+				vlangroup = <0>;
+			};
+
+			port@4 {
+				reg = <4>;
+				label = "lan5";
+				vlangroup = <0>;
+			};
+
+			port@5 {
+				reg = <5>;
+				label = "cpu";
+				vlangroup = <0>;
+			};
+
+			port@6 {
+				/* 88E1512 external phy */
+				reg = <6>;
+				label = "lan6";
+				vlangroup = <0>;
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+		};
+	};
+};