Index: head/sys/conf/files.powerpc =================================================================== --- head/sys/conf/files.powerpc +++ head/sys/conf/files.powerpc @@ -76,7 +76,7 @@ dev/tsec/if_tsec.c optional tsec dev/tsec/if_tsec_fdt.c optional tsec fdt dev/uart/uart_cpu_powerpc.c optional uart -dev/usb/controller/ehci_fsl.c optional ehci mpc85xx | ehci qoriq_dpaa +dev/usb/controller/ehci_fsl.c optional ehci mpc85xx dev/vt/hw/ofwfb/ofwfb.c optional vt aim kern/kern_clocksource.c standard kern/subr_dummy_vdso_tc.c standard @@ -135,16 +135,16 @@ powerpc/mpc85xx/atpic.c optional mpc85xx isa powerpc/mpc85xx/ds1553_bus_fdt.c optional ds1553 fdt powerpc/mpc85xx/ds1553_core.c optional ds1553 -powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc | qoriq_dpaa sdhc +powerpc/mpc85xx/fsl_sdhc.c optional mpc85xx sdhc powerpc/mpc85xx/i2c.c optional iicbus fdt powerpc/mpc85xx/isa.c optional mpc85xx isa -powerpc/mpc85xx/lbc.c optional mpc85xx | qoriq_dpaa -powerpc/mpc85xx/mpc85xx.c optional mpc85xx | qoriq_dpaa +powerpc/mpc85xx/lbc.c optional mpc85xx +powerpc/mpc85xx/mpc85xx.c optional mpc85xx powerpc/mpc85xx/mpc85xx_gpio.c optional mpc85xx gpio -powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx | qoriq_dpaa -powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx | pci qoriq_dpaa -powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx | pci qoriq_dpaa -powerpc/mpc85xx/qoriq_gpio.c optional mpc85xx gpio | qoriq_dpaa gpio +powerpc/mpc85xx/platform_mpc85xx.c optional mpc85xx +powerpc/mpc85xx/pci_mpc85xx.c optional pci mpc85xx +powerpc/mpc85xx/pci_mpc85xx_pcib.c optional pci mpc85xx +powerpc/mpc85xx/qoriq_gpio.c optional mpc85xx gpio powerpc/ofw/ofw_machdep.c standard powerpc/ofw/ofw_pcibus.c optional pci powerpc/ofw/ofw_pcib_pci.c optional pci Index: head/sys/conf/options.powerpc =================================================================== --- head/sys/conf/options.powerpc +++ head/sys/conf/options.powerpc @@ -21,7 +21,6 @@ MPC85XX opt_platform.h POWERMAC opt_platform.h PS3 opt_platform.h -QORIQ_DPAA opt_platform.h MAMBO PSERIES PSIM Index: head/sys/powerpc/conf/MPC85XX =================================================================== --- head/sys/powerpc/conf/MPC85XX +++ head/sys/powerpc/conf/MPC85XX @@ -10,7 +10,9 @@ machine powerpc powerpc +include "dpaa/config.dpaa" makeoptions DEBUG="-Wa,-me500 -g" +makeoptions WERROR="-Werror -Wno-format -Wno-redundant-decls" makeoptions NO_MODULES=yes options FPU_EMU @@ -21,7 +23,6 @@ options BOOTP options BOOTP_NFSROOT #options BOOTP_NFSV3 -options BOOTP_WIRED_TO=tsec0 options CD9660 options COMPAT_43 options DDB @@ -29,7 +30,6 @@ options DEVICE_POLLING #options DIAGNOSTIC options FDT -makeoptions FDT_DTS_FILE=mpc8572ds.dts #makeoptions FDT_DTS_FILE=mpc8555cds.dts options FFS options GDB @@ -69,6 +69,7 @@ device alc device ether device fxp +device gpio device iic device iicbus #device isa Index: head/sys/powerpc/conf/dpaa/DPAA =================================================================== --- head/sys/powerpc/conf/dpaa/DPAA +++ head/sys/powerpc/conf/dpaa/DPAA @@ -16,7 +16,7 @@ makeoptions NO_MODULES=yes # Platform support -options QORIQ_DPAA #Freescale SoC family +options MPC85XX #Freescale SoC family options SMP #Symmetric Multi Processing Index: head/sys/powerpc/mpc85xx/mpc85xx.h =================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx.h +++ head/sys/powerpc/mpc85xx/mpc85xx.h @@ -67,36 +67,44 @@ /* * Local access registers */ -#if defined(QORIQ_DPAA) /* Write order: OCP_LAWBARH -> OCP_LAWBARL -> OCP_LAWSR */ #define OCP85XX_LAWBARH(n) (CCSRBAR_VA + 0xc00 + 0x10 * (n)) #define OCP85XX_LAWBARL(n) (CCSRBAR_VA + 0xc04 + 0x10 * (n)) -#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) -#else +#define OCP85XX_LAWSR_QORIQ(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) #define OCP85XX_LAWBAR(n) (CCSRBAR_VA + 0xc08 + 0x10 * (n)) -#define OCP85XX_LAWSR(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) -#endif +#define OCP85XX_LAWSR_85XX(n) (CCSRBAR_VA + 0xc10 + 0x10 * (n)) +#define OCP85XX_LAWSR(n) (mpc85xx_is_qoriq() ? OCP85XX_LAWSR_QORIQ(n) : \ + OCP85XX_LAWSR_85XX(n)) /* Attribute register */ #define OCP85XX_ENA_MASK 0x80000000 #define OCP85XX_DIS_MASK 0x7fffffff -#if defined(QORIQ_DPAA) -#define OCP85XX_TGTIF_LBC 0x1f -#define OCP85XX_TGTIF_RAM_INTL 0x14 -#define OCP85XX_TGTIF_RAM1 0x10 -#define OCP85XX_TGTIF_RAM2 0x11 -#define OCP85XX_TGTIF_BMAN 0x18 -#define OCP85XX_TGTIF_DCSR 0x1D -#define OCP85XX_TGTIF_QMAN 0x3C -#define OCP85XX_TRGT_SHIFT 20 -#else -#define OCP85XX_TGTIF_LBC 0x04 -#define OCP85XX_TGTIF_RAM_INTL 0x0b -#define OCP85XX_TGTIF_RIO 0x0c -#define OCP85XX_TGTIF_RAM1 0x0f -#define OCP85XX_TGTIF_RAM2 0x16 -#endif +#define OCP85XX_TGTIF_LBC_QORIQ 0x1f +#define OCP85XX_TGTIF_RAM_INTL_QORIQ 0x14 +#define OCP85XX_TGTIF_RAM1_QORIQ 0x10 +#define OCP85XX_TGTIF_RAM2_QORIQ 0x11 +#define OCP85XX_TGTIF_BMAN 0x18 +#define OCP85XX_TGTIF_DCSR 0x1D +#define OCP85XX_TGTIF_QMAN 0x3C +#define OCP85XX_TRGT_SHIFT_QORIQ 20 + +#define OCP85XX_TGTIF_LBC_85XX 0x04 +#define OCP85XX_TGTIF_RAM_INTL_85XX 0x0b +#define OCP85XX_TGTIF_RIO_85XX 0x0c +#define OCP85XX_TGTIF_RAM1_85XX 0x0f +#define OCP85XX_TGTIF_RAM2_85XX 0x16 + +#define OCP85XX_TGTIF_LBC \ + (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_LBC_QORIQ : OCP85XX_TGTIF_LBC_85XX) +#define OCP85XX_TGTIF_RAM_INTL \ + (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM_INTL_QORIQ : OCP85XX_TGTIF_RAM_INTL_85XX) +#define OCP85XX_TGTIF_RIO \ + (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RIO_QORIQ : OCP85XX_TGTIF_RIO_85XX) +#define OCP85XX_TGTIF_RAM1 \ + (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM1_QORIQ : OCP85XX_TGTIF_RAM1_85XX) +#define OCP85XX_TGTIF_RAM2 \ + (mpc85xx_is_qoriq() ? OCP85XX_TGTIF_RAM2_QORIQ : OCP85XX_TGTIF_RAM2_85XX) /* * L2 cache registers @@ -153,5 +161,6 @@ void mpc85xx_enable_l3_cache(void); void mpc85xx_fix_errata(vm_offset_t); void dataloss_erratum_access(vm_offset_t, uint32_t); +int mpc85xx_is_qoriq(void); #endif /* _MPC85XX_H_ */ Index: head/sys/powerpc/mpc85xx/mpc85xx.c =================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx.c +++ head/sys/powerpc/mpc85xx/mpc85xx.c @@ -108,13 +108,17 @@ static inline void law_write(uint32_t n, uint64_t bar, uint32_t sr) { -#if defined(QORIQ_DPAA) - ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32); - ccsr_write4(OCP85XX_LAWBARL(n), bar); -#else - ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12); -#endif - ccsr_write4(OCP85XX_LAWSR(n), sr); + + if (mpc85xx_is_qoriq()) { + ccsr_write4(OCP85XX_LAWBARH(n), bar >> 32); + ccsr_write4(OCP85XX_LAWBARL(n), bar); + ccsr_write4(OCP85XX_LAWSR_QORIQ(n), sr); + ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); + } else { + ccsr_write4(OCP85XX_LAWBAR(n), bar >> 12); + ccsr_write4(OCP85XX_LAWSR_85XX(n), sr); + ccsr_read4(OCP85XX_LAWSR_85XX(n)); + } /* * The last write to LAWAR should be followed by a read @@ -123,20 +127,21 @@ * instruction. */ - ccsr_read4(OCP85XX_LAWSR(n)); isync(); } static inline void law_read(uint32_t n, uint64_t *bar, uint32_t *sr) { -#if defined(QORIQ_DPAA) - *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 | - ccsr_read4(OCP85XX_LAWBARL(n)); -#else - *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12; -#endif - *sr = ccsr_read4(OCP85XX_LAWSR(n)); + + if (mpc85xx_is_qoriq()) { + *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBARH(n)) << 32 | + ccsr_read4(OCP85XX_LAWBARL(n)); + *sr = ccsr_read4(OCP85XX_LAWSR_QORIQ(n)); + } else { + *bar = (uint64_t)ccsr_read4(OCP85XX_LAWBAR(n)) << 12; + *sr = ccsr_read4(OCP85XX_LAWSR_85XX(n)); + } } static int @@ -306,6 +311,18 @@ } } +int +mpc85xx_is_qoriq(void) +{ + uint16_t pvr = mfpvr() >> 16; + + /* QorIQ register set is only in e500mc and derivative core based SoCs. */ + if (pvr == FSL_E500mc || pvr == FSL_E5500 || pvr == FSL_E6500) + return (1); + + return (0); +} + static void mpc85xx_dataloss_erratum_spr976(void) { @@ -352,9 +369,7 @@ if (err != 0) return (err); -#ifdef QORIQ_DPAA law_enable(OCP85XX_TGTIF_DCSR, b, 0x400000); -#endif return pmap_early_io_map(b, 0x400000); } Index: head/sys/powerpc/mpc85xx/pci_mpc85xx.c =================================================================== --- head/sys/powerpc/mpc85xx/pci_mpc85xx.c +++ head/sys/powerpc/mpc85xx/pci_mpc85xx.c @@ -655,7 +655,8 @@ switch (tgt) { /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ - case OCP85XX_TGTIF_RAM1: + case OCP85XX_TGTIF_RAM1_85XX: + case OCP85XX_TGTIF_RAM1_QORIQ: attr = 0xa0f55000 | (ffsl(size) - 2); break; default: Index: head/sys/powerpc/mpc85xx/platform_mpc85xx.c =================================================================== --- head/sys/powerpc/mpc85xx/platform_mpc85xx.c +++ head/sys/powerpc/mpc85xx/platform_mpc85xx.c @@ -258,16 +258,17 @@ sizeof(freq)) <= 0) goto out; + if (freq == 0) + goto out; + /* * Time Base and Decrementer are updated every 8 CCB bus clocks. * HID0[SEL_TBCLK] = 0 */ - if (freq != 0) -#ifdef QORIQ_DPAA + if (mpc85xx_is_qoriq()) ticks = freq / 32; -#else + else ticks = freq / 8; -#endif out: if (ticks <= 0) @@ -324,24 +325,24 @@ int timeout; uintptr_t brr; int cpuid; - -#ifdef QORIQ_DPAA uint32_t tgt; - reg = ccsr_read4(OCP85XX_COREDISR); - cpuid = pc->pc_cpuid; + if (mpc85xx_is_qoriq()) { + reg = ccsr_read4(OCP85XX_COREDISR); + cpuid = pc->pc_cpuid; + + if ((reg & (1 << cpuid)) != 0) { + printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid); + return (-1); + } - if ((reg & cpuid) != 0) { - printf("%s: CPU %d is disabled!\n", __func__, pc->pc_cpuid); - return (-1); + brr = OCP85XX_BRR; + } else { + brr = OCP85XX_EEBPCR; + cpuid = pc->pc_cpuid + 24; } - - brr = OCP85XX_BRR; -#else /* QORIQ_DPAA */ - brr = OCP85XX_EEBPCR; - cpuid = pc->pc_cpuid + 24; -#endif bp_kernload = kernload; + reg = ccsr_read4(brr); if ((reg & (1 << cpuid)) != 0) { printf("SMP: CPU %d already out of hold-off state!\n", @@ -358,55 +359,52 @@ bptr = ((vm_paddr_t)(uintptr_t)__boot_page - KERNBASE) + kernload; KASSERT((bptr & 0xfff) == 0, ("%s: boot page is not aligned (%#jx)", __func__, (uintmax_t)bptr)); -#ifdef QORIQ_DPAA - - /* - * Read DDR controller configuration to select proper BPTR target ID. - * - * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers - * interleaving. If this bit is set, we have to use - * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs, - * this bit is reserved and always 0. - */ - - reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG); - if (reg & (1 << 29)) - tgt = OCP85XX_TGTIF_RAM_INTL; - else - tgt = OCP85XX_TGTIF_RAM1; - - /* - * Set BSTR to the physical address of the boot page - */ - ccsr_write4(OCP85XX_BSTRH, bptr >> 32); - ccsr_write4(OCP85XX_BSTRL, bptr); - ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK | - (tgt << OCP85XX_TRGT_SHIFT) | (ffsl(PAGE_SIZE) - 2)); - - /* Read back OCP85XX_BSTAR to synchronize write */ - ccsr_read4(OCP85XX_BSTAR); - - /* - * Enable and configure time base on new CPU. - */ - - /* Set TB clock source to platform clock / 32 */ - reg = ccsr_read4(CCSR_CTBCKSELR); - ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid)); - - /* Enable TB */ - reg = ccsr_read4(CCSR_CTBENR); - ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid)); -#else - - /* - * Set BPTR to the physical address of the boot page - */ - bptr = (bptr >> 12) | 0x80000000u; - ccsr_write4(OCP85XX_BPTR, bptr); - __asm __volatile("isync; msync"); - -#endif /* QORIQ_DPAA */ + if (mpc85xx_is_qoriq()) { + /* + * Read DDR controller configuration to select proper BPTR target ID. + * + * On P5020 bit 29 of DDR1_CS0_CONFIG enables DDR controllers + * interleaving. If this bit is set, we have to use + * OCP85XX_TGTIF_RAM_INTL as BPTR target ID. On other QorIQ DPAA SoCs, + * this bit is reserved and always 0. + */ + + reg = ccsr_read4(OCP85XX_DDR1_CS0_CONFIG); + if (reg & (1 << 29)) + tgt = OCP85XX_TGTIF_RAM_INTL; + else + tgt = OCP85XX_TGTIF_RAM1; + + /* + * Set BSTR to the physical address of the boot page + */ + ccsr_write4(OCP85XX_BSTRH, bptr >> 32); + ccsr_write4(OCP85XX_BSTRL, bptr); + ccsr_write4(OCP85XX_BSTAR, OCP85XX_ENA_MASK | + (tgt << OCP85XX_TRGT_SHIFT_QORIQ) | (ffsl(PAGE_SIZE) - 2)); + + /* Read back OCP85XX_BSTAR to synchronize write */ + ccsr_read4(OCP85XX_BSTAR); + + /* + * Enable and configure time base on new CPU. + */ + + /* Set TB clock source to platform clock / 32 */ + reg = ccsr_read4(CCSR_CTBCKSELR); + ccsr_write4(CCSR_CTBCKSELR, reg & ~(1 << pc->pc_cpuid)); + + /* Enable TB */ + reg = ccsr_read4(CCSR_CTBENR); + ccsr_write4(CCSR_CTBENR, reg | (1 << pc->pc_cpuid)); + } else { + /* + * Set BPTR to the physical address of the boot page + */ + bptr = (bptr >> 12) | 0x80000000u; + ccsr_write4(OCP85XX_BPTR, bptr); + __asm __volatile("isync; msync"); + } /* * Release AP from hold-off state @@ -424,15 +422,14 @@ * address (= 0xfffff000) isn't permanently remapped and thus not * usable otherwise. */ -#ifdef QORIQ_DPAA - ccsr_write4(OCP85XX_BSTAR, 0); -#else - ccsr_write4(OCP85XX_BPTR, 0); -#endif + if (mpc85xx_is_qoriq()) + ccsr_write4(OCP85XX_BSTAR, 0); + else + ccsr_write4(OCP85XX_BPTR, 0); __asm __volatile("isync; msync"); if (!pc->pc_awake) - printf("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); + panic("SMP: CPU %d didn't wake up.\n", pc->pc_cpuid); return ((pc->pc_awake) ? 0 : EBUSY); #else /* No SMP support */ @@ -469,33 +466,32 @@ static void mpc85xx_idle(platform_t plat, int cpu) { -#ifdef QORIQ_DPAA uint32_t reg; - reg = ccsr_read4(OCP85XX_RCPM_CDOZCR); - ccsr_write4(OCP85XX_RCPM_CDOZCR, reg | (1 << cpu)); - ccsr_read4(OCP85XX_RCPM_CDOZCR); -#else - register_t msr; - - msr = mfmsr(); - /* Freescale E500 core RM section 6.4.1. */ - __asm __volatile("msync; mtmsr %0; isync" :: - "r" (msr | PSL_WE)); -#endif + if (mpc85xx_is_qoriq()) { + reg = ccsr_read4(OCP85XX_RCPM_CDOZCR); + ccsr_write4(OCP85XX_RCPM_CDOZCR, reg | (1 << cpu)); + ccsr_read4(OCP85XX_RCPM_CDOZCR); + } else { + reg = mfmsr(); + /* Freescale E500 core RM section 6.4.1. */ + __asm __volatile("msync; mtmsr %0; isync" :: + "r" (reg | PSL_WE)); + } } static int mpc85xx_idle_wakeup(platform_t plat, int cpu) { -#ifdef QORIQ_DPAA uint32_t reg; - reg = ccsr_read4(OCP85XX_RCPM_CDOZCR); - ccsr_write4(OCP85XX_RCPM_CDOZCR, reg & ~(1 << cpu)); - ccsr_read4(OCP85XX_RCPM_CDOZCR); + if (mpc85xx_is_qoriq()) { + reg = ccsr_read4(OCP85XX_RCPM_CDOZCR); + ccsr_write4(OCP85XX_RCPM_CDOZCR, reg & ~(1 << cpu)); + ccsr_read4(OCP85XX_RCPM_CDOZCR); + + return (1); + } - return (1); -#endif return (0); }