Index: sys/dev/bhnd/bcma/bcma.c =================================================================== --- sys/dev/bhnd/bcma/bcma.c +++ sys/dev/bhnd/bcma/bcma.c @@ -181,14 +181,6 @@ } } -static void -bcma_child_deleted(device_t dev, device_t child) -{ - struct bcma_devinfo *dinfo = device_get_ivars(child); - if (dinfo != NULL) - bcma_free_dinfo(dev, dinfo); -} - static struct resource_list * bcma_get_resource_list(device_t dev, device_t child) { @@ -415,6 +407,19 @@ return (ENOENT); } +static struct bhnd_devinfo * +bcma_alloc_bhnd_dinfo(device_t dev) +{ + struct bcma_devinfo *dinfo = bcma_alloc_dinfo(dev); + return ((struct bhnd_devinfo *)dinfo); +} + +static void +bcma_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) +{ + bcma_free_dinfo(dev, (struct bcma_devinfo *)dinfo); +} + /** * Scan a device enumeration ROM table, adding all valid discovered cores to * the bus. @@ -431,8 +436,7 @@ struct bcma_devinfo *dinfo; device_t child; int error; - - dinfo = NULL; + corecfg = NULL; /* Initialize our reader */ @@ -450,26 +454,20 @@ goto failed; } - /* Allocate per-device bus info */ - dinfo = bcma_alloc_dinfo(bus, corecfg); - if (dinfo == NULL) { - error = ENXIO; - goto failed; - } - - /* The dinfo instance now owns the corecfg value */ - corecfg = NULL; - /* Add the child device */ - child = device_add_child(bus, NULL, -1); + child = BUS_ADD_CHILD(bus, 0, NULL, -1); if (child == NULL) { error = ENXIO; goto failed; } - /* The child device now owns the dinfo pointer */ - device_set_ivars(child, dinfo); - dinfo = NULL; + /* Initialize device ivars */ + dinfo = device_get_ivars(child); + if ((error = bcma_init_dinfo(bus, dinfo, corecfg))) + goto failed; + + /* The dinfo instance now owns the corecfg value */ + corecfg = NULL; /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ @@ -482,9 +480,6 @@ return (0); failed: - if (dinfo != NULL) - bcma_free_dinfo(bus, dinfo); - if (corecfg != NULL) bcma_free_corecfg(corecfg); @@ -499,13 +494,14 @@ DEVMETHOD(device_detach, bcma_detach), /* Bus interface */ - DEVMETHOD(bus_child_deleted, bcma_child_deleted), DEVMETHOD(bus_read_ivar, bcma_read_ivar), DEVMETHOD(bus_write_ivar, bcma_write_ivar), DEVMETHOD(bus_get_resource_list, bcma_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_find_hostb_device, bcma_find_hostb_device), + DEVMETHOD(bhnd_bus_alloc_devinfo, bcma_alloc_bhnd_dinfo), + DEVMETHOD(bhnd_bus_free_devinfo, bcma_free_bhnd_dinfo), DEVMETHOD(bhnd_bus_reset_core, bcma_reset_core), DEVMETHOD(bhnd_bus_suspend_core, bcma_suspend_core), DEVMETHOD(bhnd_bus_get_port_count, bcma_get_port_count), Index: sys/dev/bhnd/bcma/bcma_subr.c =================================================================== --- sys/dev/bhnd/bcma/bcma_subr.c +++ sys/dev/bhnd/bcma/bcma_subr.c @@ -186,28 +186,54 @@ } } + /** - * Allocate and initialize new device info structure, assuming ownership - * of the provided core configuration. + * Allocate and return a new empty device info structure. * * @param bus The requesting bus device. - * @param corecfg Device core configuration. + * + * @retval NULL if allocation failed. */ struct bcma_devinfo * -bcma_alloc_dinfo(device_t bus, struct bcma_corecfg *corecfg) +bcma_alloc_dinfo(device_t bus) { struct bcma_devinfo *dinfo; - dinfo = malloc(sizeof(struct bcma_devinfo), M_BHND, M_NOWAIT); + dinfo = malloc(sizeof(struct bcma_devinfo), M_BHND, M_NOWAIT|M_ZERO); if (dinfo == NULL) - return NULL; + return (NULL); - dinfo->corecfg = corecfg; + dinfo->corecfg = NULL; dinfo->res_agent = NULL; dinfo->rid_agent = -1; resource_list_init(&dinfo->resources); + return (dinfo); +} + +/** + * Initialize a device info structure previously allocated via + * bcma_alloc_dinfo, assuming ownership of the provided core + * configuration. + * + * @param bus The requesting bus device. + * @param dinfo The device info instance. + * @param corecfg Device core configuration; ownership of this value + * will be assumed by @p dinfo. + * + * @retval 0 success + * @retval non-zero initialization failed. + */ +int +bcma_init_dinfo(device_t bus, struct bcma_devinfo *dinfo, + struct bcma_corecfg *corecfg) +{ + KASSERT(dinfo->corecfg == NULL, ("dinfo previously initialized")); + + /* Save core configuration value */ + dinfo->corecfg = corecfg; + /* The device ports must always be initialized first to ensure that * rid 0 maps to the first device port */ bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->dev_ports); @@ -215,7 +241,7 @@ bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->bridge_ports); bcma_dinfo_init_resource_info(bus, dinfo, &corecfg->wrapper_ports); - return dinfo; + return (0); } /** @@ -227,9 +253,11 @@ void bcma_free_dinfo(device_t bus, struct bcma_devinfo *dinfo) { - bcma_free_corecfg(dinfo->corecfg); resource_list_free(&dinfo->resources); + if (dinfo->corecfg != NULL) + bcma_free_corecfg(dinfo->corecfg); + /* Release agent resource, if any */ if (dinfo->res_agent != NULL) { bhnd_release_resource(bus, SYS_RES_MEMORY, dinfo->rid_agent, Index: sys/dev/bhnd/bcma/bcmavar.h =================================================================== --- sys/dev/bhnd/bcma/bcmavar.h +++ sys/dev/bhnd/bcma/bcmavar.h @@ -69,7 +69,9 @@ struct bcma_sport_list *bcma_corecfg_get_port_list(struct bcma_corecfg *cfg, bhnd_port_type type); -struct bcma_devinfo *bcma_alloc_dinfo(device_t bus, +struct bcma_devinfo *bcma_alloc_dinfo(device_t bus); +int bcma_init_dinfo(device_t bus, + struct bcma_devinfo *dinfo, struct bcma_corecfg *corecfg); void bcma_free_dinfo(device_t bus, struct bcma_devinfo *dinfo); @@ -132,7 +134,9 @@ * BCMA per-device info */ struct bcma_devinfo { - struct resource_list resources; /**< Slave port memory regions. */ + struct bhnd_devinfo bhnd_dinfo; /**< superclass device info. */ + + struct resource_list resources; /**< Slave port memory regions. */ struct bcma_corecfg *corecfg; /**< IP core/block config */ struct bhnd_resource *res_agent; /**< Agent (wrapper) resource, or NULL. Not @@ -147,4 +151,4 @@ device_t hostb_dev; /**< host bridge core, or NULL */ }; -#endif /* _BCMA_BCMAVAR_H_ */ \ No newline at end of file +#endif /* _BCMA_BCMAVAR_H_ */ Index: sys/dev/bhnd/bhnd.c =================================================================== --- sys/dev/bhnd/bhnd.c +++ sys/dev/bhnd/bhnd.c @@ -493,6 +493,54 @@ } /** + * Default bhnd(4) bus driver implementation of BUS_ADD_CHILD(). + * + * This implementation manages internal bhnd(4) state, and must be called + * by subclassing drivers. + */ +device_t +bhnd_generic_add_child(device_t dev, u_int order, const char *name, int unit) +{ + struct bhnd_devinfo *dinfo; + device_t child; + + child = device_add_child_ordered(dev, order, name, unit); + if (child == NULL) + return (NULL); + + if ((dinfo = BHND_BUS_ALLOC_DEVINFO(dev)) == NULL) { + device_delete_child(dev, child); + return (NULL); + } + + device_set_ivars(child, dinfo); + + /* Inform concrete bus driver. */ + BHND_BUS_CHILD_ADDED(dev, child); + + return (child); +} + +/** + * Default bhnd(4) bus driver implementation of BUS_CHILD_DELETED(). + * + * This implementation manages internal bhnd(4) state, and must be called + * by subclassing drivers. + */ +void +bhnd_generic_child_deleted(device_t dev, device_t child) +{ + struct bhnd_softc *sc; + struct bhnd_devinfo *dinfo; + + sc = device_get_softc(dev); + + /* Free device info */ + if ((dinfo = device_get_ivars(child)) != NULL) + BHND_BUS_FREE_DEVINFO(dev, dinfo); +} + +/** * Helper function for implementing BUS_SUSPEND_CHILD(). * * TODO: Power management @@ -611,6 +659,8 @@ DEVMETHOD(device_resume, bhnd_generic_resume), /* Bus interface */ + DEVMETHOD(bus_add_child, bhnd_generic_add_child), + DEVMETHOD(bus_child_deleted, bhnd_generic_child_deleted), DEVMETHOD(bus_probe_nomatch, bhnd_generic_probe_nomatch), DEVMETHOD(bus_print_child, bhnd_generic_print_child), DEVMETHOD(bus_child_pnpinfo_str, bhnd_child_pnpinfo_str), Index: sys/dev/bhnd/bhnd_bus_if.m =================================================================== --- sys/dev/bhnd/bhnd_bus_if.m +++ sys/dev/bhnd/bhnd_bus_if.m @@ -41,6 +41,7 @@ struct bhnd_board_info; struct bhnd_core_info; struct bhnd_chipid; + struct bhnd_devinfo; struct bhnd_resource; } @@ -55,12 +56,23 @@ panic("bhnd_bus_get_chipid unimplemented"); } + static bhnd_attach_type + bhnd_bus_null_get_attach_type(device_t dev, device_t child) + { + panic("bhnd_bus_get_attach_type unimplemented"); + } + static int bhnd_bus_null_read_board_info(device_t dev, device_t child, struct bhnd_board_info *info) { panic("bhnd_bus_read_boardinfo unimplemented"); } + + static void + bhnd_bus_null_child_added(device_t dev, device_t child) + { + } static device_t bhnd_bus_null_find_hostb_device(device_t dev) @@ -197,7 +209,7 @@ METHOD bhnd_attach_type get_attach_type { device_t dev; device_t child; -} DEFAULT bhnd_bus_generic_get_attach_type; +} DEFAULT bhnd_bus_null_get_attach_type; /** * Attempt to read the BHND board identification from the parent bus. @@ -222,6 +234,46 @@ } DEFAULT bhnd_bus_null_read_board_info; /** + * Allocate and zero-initialize a buffer suitably sized and aligned for a + * bhnd_devinfo structure. + * + * @param dev The bhnd bus device. + * + * @retval non-NULL success + * @retval NULL allocation failed + */ +METHOD struct bhnd_devinfo * alloc_devinfo { + device_t dev; +}; + +/** + * Release memory previously allocated for @p devinfo. + * + * @param dev The bhnd bus device. + * @param dinfo A devinfo buffer previously allocated via + * BHND_BUS_ALLOC_DEVINFO(). + */ +METHOD void free_devinfo { + device_t dev; + struct bhnd_devinfo *dinfo; +}; + +/** + * Notify a bhnd bus that a child was added. + * + * Called at the end of BUS_ADD_CHILD() to allow the concrete bhnd(4) + * driver instance to initialize any additional driver-specific state for the + * child. + * + * @param dev The bhnd bus whose child is being added. + * @param child The child added to @p dev. + */ +METHOD void child_added { + device_t dev; + device_t child; +} DEFAULT bhnd_bus_null_child_added; + +/** * Reset the device's hardware core. * * @param dev The parent of @p child. Index: sys/dev/bhnd/bhnd_subr.c =================================================================== --- sys/dev/bhnd/bhnd_subr.c +++ sys/dev/bhnd/bhnd_subr.c @@ -1159,21 +1159,3 @@ return (EINVAL); }; -/** - * Helper function for implementing BHND_BUS_GET_ATTACH_TYPE(). - * - * This implementation of BHND_BUS_GET_ATTACH_TYPE() simply calls the - * BHND_BUS_GET_ATTACH_TYPE() method of the parent of @p dev. - */ -bhnd_attach_type -bhnd_bus_generic_get_attach_type(device_t dev, device_t child) -{ - /* iterate from cores via bhnd to bridge or SoC */ - if (device_get_parent(dev) != NULL) - return (BHND_BUS_GET_ATTACH_TYPE(device_get_parent(dev), - child)); - - panic("bhnd_bus_get_attach_type unimplemented"); - /* Unreachable */ - return (BHND_ATTACH_ADAPTER); -} Index: sys/dev/bhnd/bhndvar.h =================================================================== --- sys/dev/bhnd/bhndvar.h +++ sys/dev/bhnd/bhndvar.h @@ -46,6 +46,13 @@ DECLARE_CLASS(bhnd_driver); /** + * bhnd per-device info. Must be first member of all subclass + * devinfo structures. + */ +struct bhnd_devinfo { +}; + +/** * bhnd driver instance state. Must be first member of all subclass * softc structures. */ @@ -66,6 +73,10 @@ void bhnd_generic_probe_nomatch(device_t dev, device_t child); +device_t bhnd_generic_add_child(device_t dev, u_int order, + const char *name, int unit); +void bhnd_generic_child_deleted(device_t dev, + device_t child); int bhnd_generic_suspend_child(device_t dev, device_t child); int bhnd_generic_resume_child(device_t dev, Index: sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m =================================================================== --- sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m +++ sys/dev/bhnd/cores/chipc/bhnd_chipc_if.m @@ -36,32 +36,16 @@ # HEADER { - #include /* forward declarations */ struct chipc_caps; - struct chipc_caps *bhnd_chipc_generic_get_caps(device_t dev); } CODE { - - /** - * Helper function for implementing BHND_CHIPC_GET_CAPS(). - * - * This implementation of BHND_CHIPC_GET_CAPS() simply calls the - * BHND_CHIPC_GET_CAPS() method of the parent of @p dev. - */ - struct chipc_caps* - bhnd_chipc_generic_get_caps(device_t dev) + static struct chipc_caps * + bhnd_chipc_null_get_caps(device_t dev) { - - if (device_get_parent(dev) != NULL) - return (BHND_CHIPC_GET_CAPS(device_get_parent(dev))); - panic("bhnd_chipc_generic_get_caps unimplemented"); - /* Unreachable */ - return (NULL); } - } /** @@ -91,7 +75,7 @@ */ METHOD struct chipc_caps * get_caps { device_t dev; -} DEFAULT bhnd_chipc_generic_get_caps; +} DEFAULT bhnd_chipc_null_get_caps; /** * Enable hardware access to the SPROM/OTP source. @@ -114,12 +98,3 @@ METHOD void disable_sprom { device_t dev; } - -/** - * Return the flash configuration register value - * - * @param dev A bhnd(4) ChipCommon device - */ -METHOD uint32_t get_flash_cfg { - device_t dev; -} Index: sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c =================================================================== --- sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c +++ sys/dev/bhnd/cores/chipc/bhnd_sprom_chipc.c @@ -54,22 +54,6 @@ #define CHIPC_VALID_SPROM_SRC(_src) \ ((_src) == BHND_NVRAM_SRC_SPROM || (_src) == BHND_NVRAM_SRC_OTP) -static void -chipc_sprom_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (!CHIPC_VALID_SPROM_SRC(caps->nvram_src)) - return; - - if (device_find_child(parent, "bhnd_nvram", 0) != NULL) - return; - - if (BUS_ADD_CHILD(parent, 0, "bhnd_nvram", 0) == NULL) - device_printf(parent, "add bhnd_nvram failed\n"); -} - static int chipc_sprom_probe(device_t dev) { @@ -113,7 +97,6 @@ static device_method_t chipc_sprom_methods[] = { /* Device interface */ - DEVMETHOD(device_identify, chipc_sprom_identify), DEVMETHOD(device_probe, chipc_sprom_probe), DEVMETHOD(device_attach, chipc_sprom_attach), DEVMETHOD_END Index: sys/dev/bhnd/cores/chipc/chipc.c =================================================================== --- sys/dev/bhnd/cores/chipc/chipc.c +++ sys/dev/bhnd/cores/chipc/chipc.c @@ -37,25 +37,8 @@ * With the exception of some very early chipsets, the ChipCommon core * has been included in all HND SoCs and chipsets based on the siba(4) * and bcma(4) interconnects, providing a common interface to chipset - * identification, bus enumeration, UARTs, clocks, watchdog interrupts, GPIO, - * flash, etc. - * - * The purpose of this driver is memory resource management for ChipCommon drivers - * like UART, PMU, flash. ChipCommon core has several memory regions. - * - * ChipCommon driver has memory resource manager. Driver - * gets information about BHND core ports/regions and map them - * into drivers' resources. - * - * Here is overview of mapping: - * - * ------------------------------------------------------ - * | Port.Region| Purpose | - * ------------------------------------------------------ - * | 0.0 | PMU, SPI(0x40), UART(0x300) | - * | 1.0 | ? | - * | 1.1 | MMIO flash (SPI & CFI) | - * ------------------------------------------------------ + * identification, bus enumeration, UARTs, clocks, watchdog interrupts, + * GPIO, flash, etc. */ #include @@ -76,6 +59,7 @@ #include "chipcreg.h" #include "chipcvar.h" + #include "chipc_private.h" devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ @@ -123,49 +107,10 @@ BHND_DEVICE_QUIRK_END }; +// FIXME: IRQ shouldn't be hard-coded +#define CHIPC_MIPS_IRQ 2 -/* - * Here is resource configuration hints for child devices - * - * [Flash] There are 2 flash resources: - * - resource ID (rid) = 0: memory-mapped flash memory - * - resource ID (rid) = 1: memory-mapped flash registers (i.e for SPI) - * - * [UART] Uses IRQ and memory resources: - * - resource ID (rid) = 0: memory-mapped registers - * - IRQ resource ID (rid) = 0: shared IRQ line for Tx/Rx. - */ - -static const struct chipc_hint { - const char *name; - int unit; - int type; - int rid; - rman_res_t base; /* relative to parent resource */ - rman_res_t size; - u_int port; /* ignored if SYS_RES_IRQ */ - u_int region; -} chipc_hints[] = { - // FIXME: cfg/spi port1.1 mapping on siba(4) SoCs - // FIXME: IRQ shouldn't be hardcoded - /* device unit type rid base size port,region */ - { "bhnd_nvram", 0, SYS_RES_MEMORY, 0, CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0,0 }, - { "uart", 0, SYS_RES_MEMORY, 0, CHIPC_UART0_BASE, CHIPC_UART_SIZE, 0,0 }, - { "uart", 0, SYS_RES_IRQ, 0, 2, 1 }, - { "uart", 1, SYS_RES_MEMORY, 0, CHIPC_UART1_BASE, CHIPC_UART_SIZE, 0,0 }, - { "uart", 1, SYS_RES_IRQ, 0, 2, 1 }, - { "spi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1 }, - { "spi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, - { "cfi", 0, SYS_RES_MEMORY, 0, 0, RM_MAX_END, 1,1}, - { "cfi", 0, SYS_RES_MEMORY, 1, CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0,0 }, - { NULL } -}; - - -static int chipc_try_activate_resource( - struct chipc_softc *sc, device_t child, - int type, int rid, struct resource *r, - bool req_direct); +static int chipc_add_children(struct chipc_softc *sc); static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps); @@ -175,6 +120,11 @@ static bool chipc_should_enable_sprom( struct chipc_softc *sc); +static int chipc_try_activate_resource( + struct chipc_softc *sc, device_t child, + int type, int rid, struct resource *r, + bool req_direct); + static int chipc_init_rman(struct chipc_softc *sc); static void chipc_free_rman(struct chipc_softc *sc); static struct rman *chipc_get_rman(struct chipc_softc *sc, @@ -210,9 +160,6 @@ chipc_attach(device_t dev) { struct chipc_softc *sc; - bhnd_addr_t enum_addr; - uint32_t ccid_reg; - uint8_t chip_type; int error; sc = device_get_softc(dev); @@ -231,7 +178,7 @@ goto failed; } - /* Allocate the region containing our core registers */ + /* Allocate the region containing the chipc register block */ if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { error = ENXIO; goto failed; @@ -242,30 +189,10 @@ if (error) { sc->core_region = NULL; goto failed; - } else { - sc->core = sc->core_region->cr_res; } - /* Fetch our chipset identification data */ - ccid_reg = bhnd_bus_read_4(sc->core, CHIPC_ID); - chip_type = CHIPC_GET_BITS(ccid_reg, CHIPC_ID_BUS); - - switch (chip_type) { - case BHND_CHIPTYPE_SIBA: - /* enumeration space starts at the ChipCommon register base. */ - enum_addr = rman_get_start(sc->core->res); - break; - case BHND_CHIPTYPE_BCMA: - case BHND_CHIPTYPE_BCMA_ALT: - enum_addr = bhnd_bus_read_4(sc->core, CHIPC_EROMPTR); - break; - default: - device_printf(dev, "unsupported chip type %hhu\n", chip_type); - error = ENODEV; - goto failed; - } - - sc->ccid = bhnd_parse_chipid(ccid_reg, enum_addr); + /* Save a direct reference to our chipc registers */ + sc->core = sc->core_region->cr_res; /* Fetch and parse capability register(s) */ if ((error = chipc_read_caps(sc, &sc->caps))) @@ -274,8 +201,10 @@ if (bootverbose) chipc_print_caps(sc->dev, &sc->caps); - /* Probe and attach children */ - bus_generic_probe(dev); + /* Attach all supported child devices */ + if ((error = chipc_add_children(sc))) + goto failed; + if ((error = bus_generic_attach(dev))) goto failed; @@ -313,6 +242,119 @@ return (0); } +static int +chipc_add_children(struct chipc_softc *sc) +{ + device_t child; + const char *flash_bus; + int error; + + /* SPROM/OTP */ + if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || + sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) + { + child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add nvram device\n"); + return (ENXIO); + } + + /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0); + if (error) + return (error); + } + +#ifdef notyet + /* + * PMU/SLOWCLK/INSTACLK + * + * On AOB ("Always on Bus") devices, a PMU core (if it exists) is + * enumerated directly by the bhnd(4) bus -- not chipc. + * + * Otherwise, we always add a PMU child device, and let the + * chipc bhnd_pmu drivers probe for it. If the core supports an + * earlier non-PMU clock/power register interface, one of the instaclk, + * powerctl, or null bhnd_pmu drivers will claim the device. + */ + if (!sc->caps.aob || (sc->caps.aob && !sc->caps.pmu)) { + child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add pmu\n"); + return (ENXIO); + } + + /* Associate the applicable register block */ + error = 0; + if (sc->caps.pmu) { + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_PMU, CHIPC_PMU_SIZE, 0, 0); + } else if (sc->caps.power_control) { + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_PWRCTL, CHIPC_PWRCTL_SIZE, 0, 0); + } + + if (error) + return (error); + + } +#endif /* notyet */ + + /* All remaining devices are SoC-only */ + if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) + return (0); + + /* UARTs */ + for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { + child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add uart%u\n", i); + return (ENXIO); + } + + /* Shared IRQ */ + error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ, + 1); + if (error) { + device_printf(sc->dev, "failed to set uart%u irq %u\n", + i, CHIPC_MIPS_IRQ); + return (error); + } + + /* UART registers are mapped sequentially */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); + if (error) + return (error); + } + + /* Flash */ + flash_bus = chipc_flash_bus_name(sc->caps.flash_type); + if (flash_bus != NULL) { + child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); + if (child == NULL) { + device_printf(sc->dev, "failed to add %s device\n", + flash_bus); + return (ENXIO); + } + + /* flash memory mapping */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0, + 0, RM_MAX_END, 1, 1); + if (error) + return (error); + + /* flashctrl registers */ + error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1, + CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); + if (error) + return (error); + } + + return (0); +} + /** * Determine the NVRAM data source for this device. * @@ -411,7 +453,6 @@ /* Determine flash type and parameters */ caps->cfi_width = 0; - switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { case CHIPC_CAP_SFLASH_ST: caps->flash_type = CHIPC_SFLASH_ST; @@ -420,6 +461,7 @@ caps->flash_type = CHIPC_SFLASH_AT; break; case CHIPC_CAP_NFLASH: + /* unimplemented */ caps->flash_type = CHIPC_NFLASH; break; case CHIPC_CAP_PFLASH: @@ -548,33 +590,16 @@ static device_t chipc_add_child(device_t dev, u_int order, const char *name, int unit) { + struct chipc_softc *sc; struct chipc_devinfo *dinfo; - const struct chipc_hint *hint; device_t child; - devclass_t child_dc; - int error; - int busrel_unit; + + sc = device_get_softc(dev); child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (NULL); - /* system-wide device unit */ - unit = device_get_unit(child); - child_dc = device_get_devclass(child); - - busrel_unit = 0; - for (int i = 0; i < unit; i++) { - device_t tmp; - - tmp = devclass_get_device(child_dc, i); - if (tmp != NULL && (device_get_parent(tmp) == dev)) - busrel_unit++; - } - - /* bus-wide device unit (override unit for further hint matching) */ - unit = busrel_unit; - dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); if (dinfo == NULL) { device_delete_child(dev, child); @@ -584,93 +609,7 @@ resource_list_init(&dinfo->resources); device_set_ivars(child, dinfo); - /* Hint matching requires a device name */ - if (name == NULL) - return (child); - - /* Use hint table to set child resources */ - for (hint = chipc_hints; hint->name != NULL; hint++) { - bhnd_addr_t region_addr; - bhnd_size_t region_size; - - /* Check device name */ - if (strcmp(hint->name, name) != 0) - continue; - - /* Check device unit */ - if (hint->unit >= 0 && unit != hint->unit) - continue; - - switch (hint->type) { - case SYS_RES_IRQ: - /* Add child resource */ - error = bus_set_resource(child, hint->type, hint->rid, - hint->base, hint->size); - if (error) { - device_printf(dev, - "bus_set_resource() failed for %s: %d\n", - device_get_nameunit(child), error); - goto failed; - } - break; - - case SYS_RES_MEMORY: - /* Fetch region address and size */ - error = bhnd_get_region_addr(dev, BHND_PORT_DEVICE, - hint->port, hint->region, ®ion_addr, - ®ion_size); - if (error) { - device_printf(dev, - "lookup of %s%u.%u failed: %d\n", - bhnd_port_type_name(BHND_PORT_DEVICE), - hint->port, hint->region, error); - goto failed; - } - - /* Verify requested range is mappable */ - if (hint->base > region_size || - (hint->size != RM_MAX_END && - (hint->size > region_size || - region_size - hint->base < hint->size ))) - { - device_printf(dev, - "%s%u.%u region cannot map requested range " - "%#jx+%#jx\n", - bhnd_port_type_name(BHND_PORT_DEVICE), - hint->port, hint->region, hint->base, - hint->size); - } - - /* - * Add child resource. If hint doesn't define the end - * of resource window (RX_MAX_END), use end of region. - */ - - error = bus_set_resource(child, - hint->type, - hint->rid, region_addr + hint->base, - (hint->size == RM_MAX_END) ? - region_size - hint->base : - hint->size); - if (error) { - device_printf(dev, - "bus_set_resource() failed for %s: %d\n", - device_get_nameunit(child), error); - goto failed; - } - break; - default: - device_printf(child, "unknown hint resource type: %d\n", - hint->type); - break; - } - } - return (child); - -failed: - device_delete_child(dev, child); - return (NULL); } static void @@ -705,7 +644,7 @@ u_int num_regions; int error; - num_regions = bhnd_get_region_count(sc->dev, port, port); + num_regions = bhnd_get_region_count(sc->dev, type, port); for (u_int region = 0; region < num_regions; region++) { /* Allocate new region record */ cr = chipc_alloc_region(sc, type, port, region); @@ -1349,15 +1288,6 @@ return (&sc->caps); } -static uint32_t -chipc_get_flash_cfg(device_t dev) -{ - struct chipc_softc *sc; - - sc = device_get_softc(dev); - return (bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG)); -} - static device_method_t chipc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, chipc_probe), @@ -1399,7 +1329,6 @@ DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom_pins), DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom_pins), DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), - DEVMETHOD(bhnd_chipc_get_flash_cfg, chipc_get_flash_cfg), DEVMETHOD_END }; Index: sys/dev/bhnd/cores/chipc/chipc_cfi.c =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_cfi.c +++ sys/dev/bhnd/cores/chipc/chipc_cfi.c @@ -40,90 +40,39 @@ #include -#include #include #include "bhnd_chipc_if.h" -#include "chipc_slicer.h" + #include "chipcreg.h" #include "chipcvar.h" - -/* - * **************************** PROTOTYPES **************************** - */ - -static void chipc_cfi_identify(driver_t *driver, device_t parent); -static int chipc_cfi_probe(device_t dev); -static int chipc_cfi_attach(device_t dev); - -/* - * **************************** IMPLEMENTATION ************************ - */ - -static void -chipc_cfi_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - if (device_find_child(parent, cfi_driver_name, -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (caps == NULL) - return; - - if (caps->flash_type != CHIPC_PFLASH_CFI) - return; - - BUS_ADD_CHILD(parent, 0, cfi_driver_name, -1); - return; -} +#include "chipc_slicer.h" static int chipc_cfi_probe(device_t dev) { - int error; - int enabled; - int byteswap; - uint32_t flash_config; struct cfi_softc *sc; + int error; sc = device_get_softc(dev); - flash_config = BHND_CHIPC_GET_FLASH_CFG(device_get_parent(dev)); - - enabled = (flash_config & CHIPC_CF_EN); - byteswap = (flash_config & CHIPC_CF_BS); - - if (enabled == 0) - device_disable(dev); - - BHND_DEBUG_DEV(dev, "trying attach flash enabled=%d swapbytes=%d", - enabled, byteswap); - sc->sc_width = 0; - error = cfi_probe(dev); - if (error == 0) - device_set_desc(dev, "ChipCommon CFI"); + if ((error = cfi_probe(dev)) > 0) + return (error); + + device_set_desc(dev, "Broadcom ChipCommon CFI"); return (error); } static int chipc_cfi_attach(device_t dev) { - int error; - - error = cfi_attach(dev); - if (error) - return (error); - - flash_register_slicer(chipc_slicer_cfi); - return (0); + chipc_register_slicer(CHIPC_PFLASH_CFI); + return (cfi_attach(dev)); } static device_method_t chipc_cfi_methods[] = { /* device interface */ - DEVMETHOD(device_identify, chipc_cfi_identify), DEVMETHOD(device_probe, chipc_cfi_probe), DEVMETHOD(device_attach, chipc_cfi_attach), DEVMETHOD(device_detach, cfi_detach), @@ -138,4 +87,3 @@ }; DRIVER_MODULE(cfi, bhnd_chipc, chipc_cfi_driver, cfi_devclass, 0, 0); - Index: sys/dev/bhnd/cores/chipc/chipc_private.h =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_private.h +++ sys/dev/bhnd/cores/chipc/chipc_private.h @@ -55,6 +55,11 @@ struct resource *parent, bhnd_size_t offset, bhnd_size_t size); +int chipc_set_resource(struct chipc_softc *sc, + device_t child, int type, int rid, + rman_res_t start, rman_res_t count, u_int port, + u_int region); + struct chipc_region *chipc_alloc_region(struct chipc_softc *sc, bhnd_port_type type, u_int port, u_int region); Index: sys/dev/bhnd/cores/chipc/chipc_slicer.h =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_slicer.h +++ sys/dev/bhnd/cores/chipc/chipc_slicer.h @@ -34,10 +34,13 @@ #include +#include "chipcvar.h" + #define TRX_MAGIC 0x30524448 #define CFE_MAGIC 0x43464531 #define NVRAM_MAGIC 0x48534C46 +void chipc_register_slicer(chipc_flash flash_type); int chipc_slicer_spi(device_t dev, struct flash_slice *slices, int *nslices); int chipc_slicer_cfi(device_t dev, struct flash_slice *slices, Index: sys/dev/bhnd/cores/chipc/chipc_slicer.c =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_slicer.c +++ sys/dev/bhnd/cores/chipc/chipc_slicer.c @@ -54,58 +54,88 @@ #include #include "chipc_spi.h" -static int chipc_slicer_walk(device_t dev, struct resource* res, +static int chipc_slicer_walk(device_t dev, struct resource *res, struct flash_slice *slices, int *nslices); +void +chipc_register_slicer(chipc_flash flash_type) +{ + switch (flash_type) { + case CHIPC_SFLASH_AT: + case CHIPC_SFLASH_ST: + flash_register_slicer(chipc_slicer_spi); + break; + case CHIPC_PFLASH_CFI: + flash_register_slicer(chipc_slicer_cfi); + break; + default: + /* Unsupported */ + break; + } +} + int chipc_slicer_cfi(device_t dev, struct flash_slice *slices, int *nslices) { struct cfi_softc *sc; + device_t parent; - if (strcmp("cfi", device_get_name(dev)) != 0) - return (0); + /* must be CFI flash */ + if (device_get_devclass(dev) != devclass_find("cfi")) + return (ENXIO); - sc = device_get_softc(dev); + /* must be attached to chipc */ + if ((parent = device_get_parent(dev)) == NULL) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } + if (device_get_devclass(parent) != devclass_find("bhnd_chipc")) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } + + sc = device_get_softc(dev); return (chipc_slicer_walk(dev, sc->sc_res, slices, nslices)); } int chipc_slicer_spi(device_t dev, struct flash_slice *slices, int *nslices) { - /* flash(mx25l) <- spibus <- chipc_spi */ - device_t spibus; - device_t chipc_spi; struct chipc_spi_softc *sc; + device_t chipc, spi, spibus; BHND_DEBUG_DEV(dev, "initting SPI slicer: %s", device_get_name(dev)); - if (strcmp("mx25l", device_get_name(dev)) != 0) - return (EINVAL); - + /* must be SPI-attached flash */ spibus = device_get_parent(dev); if (spibus == NULL) { BHND_ERROR_DEV(dev, "no found ChipCommon SPI BUS device"); - return (EINVAL); + return (ENXIO); } - chipc_spi = device_get_parent(spibus); - if (chipc_spi == NULL) { - BHND_ERROR_DEV(spibus, "no found ChipCommon SPI device"); - return (EINVAL); + spi = device_get_parent(spibus); + if (spi == NULL) { + BHND_ERROR_DEV(dev, "no found ChipCommon SPI device"); + return (ENXIO); } - sc = device_get_softc(chipc_spi); + chipc = device_get_parent(spi); + if (device_get_devclass(chipc) != devclass_find("bhnd_chipc")) { + BHND_ERROR_DEV(dev, "no found ChipCommon device"); + return (ENXIO); + } - return (chipc_slicer_walk(dev, sc->sc_res, slices, nslices)); + sc = device_get_softc(spi); + return (chipc_slicer_walk(dev, sc->sc_flash_res, slices, nslices)); } /* * Main processing part */ static int -chipc_slicer_walk(device_t dev, struct resource* res, - struct flash_slice *slices, int *nslices) +chipc_slicer_walk(device_t dev, struct resource *res, + struct flash_slice *slices, int *nslices) { uint32_t fw_len; uint32_t fs_ofs; Index: sys/dev/bhnd/cores/chipc/chipc_spi.h =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_spi.h +++ sys/dev/bhnd/cores/chipc/chipc_spi.h @@ -62,28 +62,26 @@ #define CHIPC_SPI_FLASHDATA 0x08 struct chipc_spi_softc { - device_t dev; + device_t sc_dev; + struct resource *sc_res; /**< SPI registers */ + int sc_rid; - /* SPI registers */ - struct resource *sc_mem_res; - - /* MMIO flash */ - struct resource *sc_res; + struct resource *sc_flash_res; /**< flash shadow */ + int sc_flash_rid; }; /* register space access macros */ -#define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ +#define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_res, 0, 0, \ BUS_SPACE_BARRIER_WRITE) -#define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ +#define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_res, 0, 0, \ BUS_SPACE_BARRIER_READ) -#define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ - BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) +#define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_res, 0, 0, \ + BUS_SPACE_BARRIER_READ | \ + BUS_SPACE_BARRIER_WRITE) -#define SPI_WRITE(sc, reg, val) do { \ - bus_write_4(sc->sc_mem_res, (reg), (val)); \ - } while (0) +#define SPI_WRITE(sc, reg, val) bus_write_4(sc->sc_res, (reg), (val)); -#define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) +#define SPI_READ(sc, reg) bus_read_4(sc->sc_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) Index: sys/dev/bhnd/cores/chipc/chipc_spi.c =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_spi.c +++ sys/dev/bhnd/cores/chipc/chipc_spi.c @@ -1,5 +1,6 @@ /*- * Copyright (c) 2016 Michael Zhilin + * Copyright (c) 2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -41,135 +42,134 @@ #include #include -/* - * SPI BUS interface - */ + #include +#include "bhnd_chipc_if.h" + #include "spibus_if.h" #include "chipcreg.h" #include "chipcvar.h" -#include "chipc_spi.h" -#include "bhnd_chipc_if.h" - -/* - * Flash slicer - */ #include "chipc_slicer.h" -/* - * **************************** PROTOTYPES **************************** - */ +#include "chipc_spi.h" -static void chipc_spi_identify(driver_t *driver, device_t parent); static int chipc_spi_probe(device_t dev); static int chipc_spi_attach(device_t dev); +static int chipc_spi_detach(device_t dev); static int chipc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd); static int chipc_spi_txrx(struct chipc_spi_softc *sc, uint8_t in, uint8_t* out); static int chipc_spi_wait(struct chipc_spi_softc *sc); -/* - * **************************** IMPLEMENTATION ************************ - */ +static int +chipc_spi_probe(device_t dev) +{ + device_set_desc(dev, "Broadcom ChipCommon SPI"); + return (BUS_PROBE_NOWILDCARD); +} -static void -chipc_spi_identify(driver_t *driver, device_t parent) +static int +chipc_spi_attach(device_t dev) { - struct chipc_caps *caps; - device_t spidev; - device_t spibus; - device_t flash; - char* flash_name; - int err; - - flash_name = NULL; - - if (device_find_child(parent, "spi", -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - if (caps == NULL) { - BHND_ERROR_DEV(parent, "can't retrieve ChipCommon capabilities"); - return; - } + struct chipc_spi_softc *sc; + struct chipc_caps *ccaps; + device_t flash_dev; + device_t spibus; + const char *flash_name; + int error; - switch (caps->flash_type) { - case CHIPC_SFLASH_AT: - flash_name = "at45d"; - break; - case CHIPC_SFLASH_ST: - flash_name = "mx25l"; - break; - default: - return; - } + sc = device_get_softc(dev); - spidev = BUS_ADD_CHILD(parent, 0, "spi", -1); - if (spidev == NULL) { - BHND_ERROR_DEV(parent, "can't add chipc_spi to ChipCommon"); - return; + /* Allocate SPI controller registers */ + sc->sc_rid = 1; + sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, + RF_ACTIVE); + if (sc->sc_res == NULL) { + device_printf(dev, "failed to allocate device registers\n"); + return (ENXIO); } - err = device_probe_and_attach(spidev); - if (err) { - BHND_ERROR_DEV(spidev, "failed attach chipc_spi: %d", err); - return; + /* Allocate flash shadow region */ + sc->sc_flash_rid = 0; + sc->sc_flash_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->sc_flash_rid, RF_ACTIVE); + if (sc->sc_flash_res == NULL) { + device_printf(dev, "failed to allocate flash region\n"); + error = ENXIO; + goto failed; } - spibus = device_find_child(spidev, "spibus", -1); - if (spibus == NULL) { - BHND_ERROR_DEV(spidev, "can't find spibus under chipc_spi"); - return; + /* + * Add flash device + * + * XXX: This should be replaced with a DEVICE_IDENTIFY implementation + * in chipc-specific subclasses of the mx25l and at45d drivers. + */ + if ((spibus = device_add_child(dev, "spibus", -1)) == NULL) { + device_printf(dev, "failed to add spibus\n"); + error = ENXIO; + goto failed; } - flash = BUS_ADD_CHILD(spibus, 0, flash_name, -1); - if (flash == NULL) { - BHND_ERROR_DEV(spibus, "can't add %s to spibus", flash_name); - return; + /* Let spibus perform full attach before we try to call + * BUS_ADD_CHILD() */ + if ((error = bus_generic_attach(dev))) + goto failed; + + /* Determine flash type and add the flash child */ + ccaps = BHND_CHIPC_GET_CAPS(device_get_parent(dev)); + flash_name = chipc_sflash_device_name(ccaps->flash_type); + if (flash_name != NULL) { + flash_dev = BUS_ADD_CHILD(spibus, 0, flash_name, -1); + if (flash_dev == NULL) { + device_printf(dev, "failed to add %s\n", flash_name); + error = ENXIO; + goto failed; + } + + chipc_register_slicer(ccaps->flash_type); + + if ((error = device_probe_and_attach(flash_dev))) { + device_printf(dev, "failed to attach %s: %d\n", + flash_name, error); + goto failed; + } } - err = device_probe_and_attach(flash); - if (err) - BHND_ERROR_DEV(flash, "failed attach flash %s: %d", flash_name, - err); + return (0); - return; -} +failed: + device_delete_children(dev); -static int -chipc_spi_probe(device_t dev) -{ - device_set_desc(dev, "ChipCommon SPI"); - return (BUS_PROBE_DEFAULT); -} + if (sc->sc_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, + sc->sc_res); -struct resource_spec spec_mem[] = { - {SYS_RES_MEMORY, 0, RF_ACTIVE}, - {SYS_RES_MEMORY, 1, RF_ACTIVE}, - { -1, -1, 0 } - }; + if (sc->sc_flash_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_flash_rid, + sc->sc_flash_res); + + return (error); +} static int -chipc_spi_attach(device_t dev) +chipc_spi_detach(device_t dev) { - int err; struct chipc_spi_softc *sc; - struct resource *mem[2]; + int error; sc = device_get_softc(dev); - err = bus_alloc_resources(dev, spec_mem, mem); - if (err != 0) - return (ENXIO); - sc->sc_res = mem[0]; - sc->sc_mem_res = mem[1]; + if ((error = bus_generic_detach(dev))) + return (error); - flash_register_slicer(chipc_slicer_spi); - device_add_child(dev, "spibus", 0); - return (bus_generic_attach(dev)); + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res); + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_flash_rid, + sc->sc_flash_res); + return (0); } static int @@ -184,7 +184,7 @@ if (i > 0) return (0); - BHND_DEBUG_DEV(sc->dev, "busy"); + BHND_DEBUG_DEV(sc->sc_dev, "busy"); return (-1); } @@ -256,13 +256,11 @@ return (0); } -/* - * **************************** METADATA ************************ - */ static device_method_t chipc_spi_methods[] = { - DEVMETHOD(device_identify, chipc_spi_identify), DEVMETHOD(device_probe, chipc_spi_probe), DEVMETHOD(device_attach, chipc_spi_attach), + DEVMETHOD(device_detach, chipc_spi_detach), + /* SPI */ DEVMETHOD(spibus_transfer, chipc_spi_transfer), DEVMETHOD_END @@ -277,4 +275,4 @@ static devclass_t chipc_spi_devclass; DRIVER_MODULE(chipc_spi, bhnd_chipc, chipc_spi_driver, chipc_spi_devclass, - 0, 0); + 0, 0); Index: sys/dev/bhnd/cores/chipc/chipc_subr.c =================================================================== --- sys/dev/bhnd/cores/chipc/chipc_subr.c +++ sys/dev/bhnd/cores/chipc/chipc_subr.c @@ -38,6 +38,93 @@ #include "chipcvar.h" /** + * Return a human-readable name for the given flash @p type. + */ +const char * +chipc_flash_name(chipc_flash type) +{ + switch (type) { + case CHIPC_PFLASH_CFI: + return ("CFI Flash"); + + case CHIPC_SFLASH_ST: + case CHIPC_SFLASH_AT: + return ("SPI Flash"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + return ("QSPI Flash"); + + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + return ("NAND"); + + case CHIPC_FLASH_NONE: + default: + return ("unknown"); + } +} + +/** + * Return the name of the bus device class used by flash @p type, + * or NULL if @p type is unsupported. + */ +const char * +chipc_flash_bus_name(chipc_flash type) +{ + switch (type) { + case CHIPC_PFLASH_CFI: + return ("cfi"); + + case CHIPC_SFLASH_ST: + case CHIPC_SFLASH_AT: + return ("spi"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + /* unimplemented; spi? */ + return (NULL); + + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + /* unimplemented; nandbus? */ + return (NULL); + + case CHIPC_FLASH_NONE: + default: + return (NULL); + } +} + +/** + * Return the name of the flash device class for SPI flash @p type, + * or NULL if @p type does not use SPI, or is unsupported. + */ +const char * +chipc_sflash_device_name(chipc_flash type) +{ + switch (type) { + case CHIPC_SFLASH_ST: + return ("mx25l"); + + case CHIPC_SFLASH_AT: + return ("at45d"); + + case CHIPC_QSFLASH_ST: + case CHIPC_QSFLASH_AT: + /* unimplemented */ + return (NULL); + + case CHIPC_PFLASH_CFI: + case CHIPC_NFLASH: + case CHIPC_NFLASH_4706: + case CHIPC_FLASH_NONE: + default: + return (NULL); + } +} + +/** * Initialize child resource @p r with a virtual address, tag, and handle * copied from @p parent, adjusted to contain only the range defined by * @p offsize and @p size. @@ -74,6 +161,72 @@ return (0); } +/** + * Associate a resource with a given resource ID, relative to the given + * port and region. + * + * This function behaves identically to bus_set_resource() for all resource + * types other than SYS_RES_MEMORY. + * + * For SYS_RES_MEMORY resources, the specified @p region's address and size + * will be fetched from the bhnd(4) bus, and bus_set_resource() will be called + * with @p start added the region's actual base address. + * + * To use the default region values for @p start and @p count, specify + * a @p start value of 0ul, and an end value of RMAN_MAX_END + * + * @param sc chipc driver state. + * @param child The device to set the resource on. + * @param type The resource type. + * @param rid The resource ID. + * @param start The resource start address (if SYS_RES_MEMORY, this is + * relative to @p region's base address). + * @param count The length of the resource. + * @param port The mapping port number (ignored if not SYS_RES_MEMORY). + * @param region The mapping region number (ignored if not SYS_RES_MEMORY). + */ +int +chipc_set_resource(struct chipc_softc *sc, device_t child, int type, int rid, + rman_res_t start, rman_res_t count, u_int port, u_int region) +{ + bhnd_addr_t region_addr; + bhnd_size_t region_size; + bool isdefault; + int error; + + if (type != SYS_RES_MEMORY) + return (bus_set_resource(child, type, rid, start, count)); + + isdefault = RMAN_IS_DEFAULT_RANGE(start, count); + + /* Fetch region address and size */ + error = bhnd_get_region_addr(sc->dev, BHND_PORT_DEVICE, port, + region, ®ion_addr, ®ion_size); + if (error) { + device_printf(sc->dev, + "lookup of %s%u.%u failed: %d\n", + bhnd_port_type_name(BHND_PORT_DEVICE), port, region, error); + return (error); + } + + /* Populate defaults */ + if (isdefault) { + start = 0; + count = region_size; + } + + /* Verify requested range is mappable */ + if (start > region_size || region_size - start < count) { + device_printf(sc->dev, + "%s%u.%u region cannot map requested range %#jx+%#jx\n", + bhnd_port_type_name(BHND_PORT_DEVICE), port, region, start, + count); + return (ERANGE); + } + + return (bus_set_resource(child, type, rid, region_addr + start, count)); +} + /* * Print a capability structure. Index: sys/dev/bhnd/cores/chipc/chipcreg.h =================================================================== --- sys/dev/bhnd/cores/chipc/chipcreg.h +++ sys/dev/bhnd/cores/chipc/chipcreg.h @@ -175,8 +175,8 @@ #define CHIPC_UART_BASE 0x300 #define CHIPC_UART_SIZE 0x100 -#define CHIPC_UART0_BASE CHIPC_UART_BASE -#define CHIPC_UART1_BASE (CHIPC_UART_BASE + CHIPC_UART_SIZE) +#define CHIPC_UART_MAX 3 /**< max UART blocks */ +#define CHIPC_UART(_n) (CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n)) /* PMU registers (rev >= 20) */ #define CHIPC_PMU_BASE 0x600 Index: sys/dev/bhnd/cores/chipc/chipcvar.h =================================================================== --- sys/dev/bhnd/cores/chipc/chipcvar.h +++ sys/dev/bhnd/cores/chipc/chipcvar.h @@ -59,6 +59,10 @@ CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ } chipc_flash; +const char *chipc_flash_name(chipc_flash type); +const char *chipc_flash_bus_name(chipc_flash type); +const char *chipc_sflash_device_name(chipc_flash type); + /** * ChipCommon capability flags; */ @@ -69,15 +73,16 @@ uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ - chipc_flash flash_type; /**< Flash type */ - bhnd_nvram_src nvram_src; /**< identified NVRAM source */ + chipc_flash flash_type; /**< flash type */ + uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI + not present */ + + bhnd_nvram_src nvram_src; /**< identified NVRAM source */ bus_size_t sprom_offset; /**< Offset to SPROM data within SPROM/OTP, 0 if unknown or not present */ uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ - uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI - not present */ uint8_t pll_type; /**< PLL type */ bool power_control; /**< Power control available */ @@ -200,7 +205,6 @@ struct bhnd_resource *core; /**< core registers. */ struct chipc_region *core_region; /**< region containing core registers */ - struct bhnd_chipid ccid; /**< chip identification */ uint32_t quirks; /**< chipc quirk flags */ struct chipc_caps caps; /**< chipc capabilities */ Index: sys/dev/bhnd/siba/siba.c =================================================================== --- sys/dev/bhnd/siba/siba.c +++ sys/dev/bhnd/siba/siba.c @@ -206,14 +206,6 @@ } } -static void -siba_child_deleted(device_t dev, device_t child) -{ - struct siba_devinfo *dinfo = device_get_ivars(child); - if (dinfo != NULL) - siba_free_dinfo(dev, dinfo); -} - static struct resource_list * siba_get_resource_list(device_t dev, device_t child) { @@ -436,6 +428,19 @@ return (0); } +static struct bhnd_devinfo * +siba_alloc_bhnd_dinfo(device_t dev) +{ + struct siba_devinfo *dinfo = siba_alloc_dinfo(dev); + return ((struct bhnd_devinfo *)dinfo); +} + +static void +siba_free_bhnd_dinfo(device_t dev, struct bhnd_devinfo *dinfo) +{ + siba_free_dinfo(dev, (struct siba_devinfo *)dinfo); +} + /** * Scan the core table and add all valid discovered cores to * the bus. @@ -556,6 +561,13 @@ goto cleanup; } + /* Add the child device */ + child = BUS_ADD_CHILD(dev, 0, NULL, -1); + if (child == NULL) { + error = ENXIO; + goto cleanup; + } + /* Read the core info */ idhigh = bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDHIGH)); idlow = bus_read_4(r, SB0_REG_ABS(SIBA_CFG0_IDLOW)); @@ -570,27 +582,18 @@ cores[i].unit++; } - /* Allocate per-device bus info */ - dinfo = siba_alloc_dinfo(dev, &cid); - if (dinfo == NULL) { + /* Initialize per-device bus info */ + if ((dinfo = device_get_ivars(child)) == NULL) { error = ENXIO; goto cleanup; } - /* Register the core's address space(s). */ - if ((error = siba_register_addrspaces(dev, dinfo, r))) + if ((error = siba_init_dinfo(dev, dinfo, &cid))) goto cleanup; - /* Add the child device */ - child = device_add_child(dev, NULL, -1); - if (child == NULL) { - error = ENXIO; + /* Register the core's address space(s). */ + if ((error = siba_register_addrspaces(dev, dinfo, r))) goto cleanup; - } - - /* The child device now owns the dinfo pointer */ - device_set_ivars(child, dinfo); - dinfo = NULL; /* If pins are floating or the hardware is otherwise * unpopulated, the device shouldn't be used. */ @@ -606,9 +609,6 @@ if (cores != NULL) free(cores, M_BHND); - if (dinfo != NULL) - siba_free_dinfo(dev, dinfo); - if (r != NULL) bus_release_resource(dev, SYS_RES_MEMORY, rid, r); @@ -624,13 +624,14 @@ DEVMETHOD(device_suspend, siba_suspend), /* Bus interface */ - DEVMETHOD(bus_child_deleted, siba_child_deleted), DEVMETHOD(bus_read_ivar, siba_read_ivar), DEVMETHOD(bus_write_ivar, siba_write_ivar), DEVMETHOD(bus_get_resource_list, siba_get_resource_list), /* BHND interface */ DEVMETHOD(bhnd_bus_find_hostb_device, siba_find_hostb_device), + DEVMETHOD(bhnd_bus_alloc_devinfo, siba_alloc_bhnd_dinfo), + DEVMETHOD(bhnd_bus_free_devinfo, siba_free_bhnd_dinfo), DEVMETHOD(bhnd_bus_reset_core, siba_reset_core), DEVMETHOD(bhnd_bus_suspend_core, siba_suspend_core), DEVMETHOD(bhnd_bus_get_port_count, siba_get_port_count), Index: sys/dev/bhnd/siba/siba_subr.c =================================================================== --- sys/dev/bhnd/siba/siba_subr.c +++ sys/dev/bhnd/siba/siba_subr.c @@ -106,23 +106,21 @@ } /** - * Allocate and initialize new device info structure, copying the - * provided core id. + * Allocate and return a new empty device info structure. * - * @param dev The requesting bus device. - * @param core Device core info. + * @param bus The requesting bus device. + * + * @retval NULL if allocation failed. */ struct siba_devinfo * -siba_alloc_dinfo(device_t bus, const struct siba_core_id *core_id) +siba_alloc_dinfo(device_t bus) { struct siba_devinfo *dinfo; - dinfo = malloc(sizeof(struct siba_devinfo), M_BHND, M_NOWAIT); + dinfo = malloc(sizeof(struct siba_devinfo), M_BHND, M_NOWAIT|M_ZERO); if (dinfo == NULL) return NULL; - dinfo->core_id = *core_id; - for (u_int i = 0; i < nitems(dinfo->cfg); i++) { dinfo->cfg[i] = NULL; dinfo->cfg_rid[i] = -1; @@ -134,6 +132,25 @@ } /** + * Initialize a device info structure previously allocated via + * siba_alloc_dinfo, copying the provided core id. + * + * @param dev The requesting bus device. + * @param dinfo The device info instance. + * @param core Device core info. + * + * @retval 0 success + * @retval non-zero initialization failed. + */ +int +siba_init_dinfo(device_t dev, struct siba_devinfo *dinfo, + const struct siba_core_id *core_id) +{ + dinfo->core_id = *core_id; + return (0); +} + +/** * Map an addrspace index to its corresponding bhnd(4) port number. * * @param addrspace Address space index. Index: sys/dev/bhnd/siba/sibavar.h =================================================================== --- sys/dev/bhnd/siba/sibavar.h +++ sys/dev/bhnd/siba/sibavar.h @@ -63,7 +63,9 @@ int siba_add_children(device_t bus, const struct bhnd_chipid *chipid); -struct siba_devinfo *siba_alloc_dinfo(device_t dev, +struct siba_devinfo *siba_alloc_dinfo(device_t dev); +int siba_init_dinfo(device_t dev, + struct siba_devinfo *dinfo, const struct siba_core_id *core_id); void siba_free_dinfo(device_t dev, struct siba_devinfo *dinfo); @@ -136,6 +138,8 @@ * siba(4) per-device info */ struct siba_devinfo { + struct bhnd_devinfo bhnd_dinfo; /**< superclass device info. */ + struct resource_list resources; /**< per-core memory regions. */ struct siba_core_id core_id; /**< core identification info */ struct siba_addrspace addrspace[SIBA_MAX_ADDRSPACE]; /**< memory map descriptors */ Index: sys/mips/atheros/ar71xx_chip.c =================================================================== --- sys/mips/atheros/ar71xx_chip.c +++ sys/mips/atheros/ar71xx_chip.c @@ -55,8 +55,6 @@ #include #include -#include - /* XXX these should replace the current definitions in ar71xxreg.h */ /* XXX perhaps an ar71xx_chip.h header file? */ #define AR71XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 Index: sys/mips/atheros/ar71xx_machdep.c =================================================================== --- sys/mips/atheros/ar71xx_machdep.c +++ sys/mips/atheros/ar71xx_machdep.c @@ -58,8 +58,6 @@ #include #include -#include - extern char edata[], end[]; /* 4KB static data aread to keep a copy of the bootload env until Index: sys/mips/atheros/ar724x_chip.c =================================================================== --- sys/mips/atheros/ar724x_chip.c +++ sys/mips/atheros/ar724x_chip.c @@ -59,8 +59,6 @@ #include #include -#include - static void ar724x_chip_detect_mem_size(void) { Index: sys/mips/atheros/ar91xx_chip.c =================================================================== --- sys/mips/atheros/ar91xx_chip.c +++ sys/mips/atheros/ar91xx_chip.c @@ -57,8 +57,6 @@ #include #include -#include - static void ar91xx_chip_detect_mem_size(void) { Index: sys/mips/broadcom/bcm_machdep.c =================================================================== --- sys/mips/broadcom/bcm_machdep.c +++ sys/mips/broadcom/bcm_machdep.c @@ -71,7 +71,6 @@ #include #include -#include #include "bcm_socinfo.h" #ifdef CFE @@ -79,7 +78,9 @@ #endif #if 0 -#define BROADCOM_TRACE 0 +#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__) +#else +#define BCM_TRACE(_fmt, ...) #endif extern int *edata; @@ -109,16 +110,12 @@ result = cfe_enummem(i / 2, 0, &addr, &len, &type); if (result < 0) { -#ifdef BROADCOM_TRACE - printf("There is no phys memory for: %d\n", i); -#endif + BCM_TRACE("There is no phys memory for: %d\n", i); phys_avail[i] = phys_avail[i + 1] = 0; break; } - if (type != CFE_MI_AVAILABLE){ -#ifdef BROADCOM_TRACE - printf("phys memory is not available: %d\n", i); -#endif + if (type != CFE_MI_AVAILABLE) { + BCM_TRACE("phys memory is not available: %d\n", i); continue; } @@ -131,19 +128,16 @@ */ phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); } -#ifdef BROADCOM_TRACE - printf("phys memory is available for: %d\n", i); - printf(" => addr = %jx\n", addr); - printf(" => len = %jd\n", len); -#endif + + BCM_TRACE("phys memory is available for: %d\n", i); + BCM_TRACE(" => addr = %jx\n", addr); + BCM_TRACE(" => len = %jd\n", len); + phys_avail[i + 1] = addr + len; physmem += len; } -#ifdef BROADCOM_TRACE - printf("Total phys memory is : %ld\n", physmem); -#endif - + BCM_TRACE("Total phys memory is : %ld\n", physmem); realmem = btoc(physmem); #endif @@ -165,15 +159,25 @@ #endif } -#define BCM_REG_CHIPC 0x18000000 - - void platform_reset(void) { printf("bcm::platform_reset()\n"); intr_disable(); + +#if defined(CFE) + cfe_exit(0, 0); +#else + /* PMU watchdog reset */ BCM_WRITE_REG32(BCM_REG_CHIPC_PMUWD_OFFS, 2); /* PMU watchdog */ +#endif + +#if 0 + /* Non-PMU reset + * XXX: Need chipc capability flags */ + *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; +#endif + for (;;); } @@ -194,6 +198,37 @@ /* Initialize pcpu stuff */ mips_pcpu0_init(); +#if 0 + /* + * Probe the Broadcom on-chip PLL clock registers + * and discover the CPU pipeline clock and bus clock + * multipliers from this. + * XXX: Wrong place. You have to ask the ChipCommon + * or External Interface cores on the SiBa. + */ + uint32_t busmult, cpumult, refclock, clkcfg1; +#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F +#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 +#define S5_CLKCFG1_BUSMULT_SHIFT 5 +#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 +#define S5_CLKCFG1_CPUMULT_SHIFT 10 + + counter_freq = 100000000; /* XXX */ + + clkcfg1 = s5_rd_clkcfg1(); + printf("clkcfg1 = 0x%08x\n", clkcfg1); + + refclock = clkcfg1 & 0x1F; + busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; + cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; + + printf("refclock = %u\n", refclock); + printf("busmult = %u\n", busmult); + printf("cpumult = %u\n", cpumult); + + counter_freq = cpumult * refclock; +#endif + socinfo = bcm_get_socinfo(); platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */ @@ -212,10 +247,10 @@ if (a3 == CFE_EPTSEAL) cfe_init(a0, a2); #endif + cninit(); mips_init(); - /* BCM471x timer is 1/2 of Clk */ - mips_timer_init_params(platform_counter_freq, 1); + mips_timer_init_params(platform_counter_freq, socinfo->double_count); } Index: sys/mips/broadcom/bcm_socinfo.h =================================================================== --- sys/mips/broadcom/bcm_socinfo.h +++ sys/mips/broadcom/bcm_socinfo.h @@ -35,9 +35,10 @@ #include struct bcm_socinfo { - uint32_t id; - uint32_t cpurate; /* in MHz */ - uint32_t uartrate; /* in Hz */ + uint32_t id; + uint32_t cpurate; /* in MHz */ + uint32_t uartrate; /* in Hz */ + int double_count; }; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key); Index: sys/mips/broadcom/bcm_socinfo.c =================================================================== --- sys/mips/broadcom/bcm_socinfo.c +++ sys/mips/broadcom/bcm_socinfo.c @@ -33,22 +33,23 @@ /* found on https://wireless.wiki.kernel.org/en/users/drivers/b43/soc */ struct bcm_socinfo bcm_socinfos[] = { - {0x00005300, 600, 25000000}, /* BCM4706 to check */ - {0x0022B83A, 300, 20000000}, /* BCM4716B0 ASUS RT-N12 */ - {0x00914716, 354, 20000000}, /* BCM4717A1 to check */ - {0x00A14716, 480, 20000000}, /* BCM4718A1 ASUS RT-N16 */ - {0x00435356, 300, 25000000}, /* BCM5356A1 (RT-N10, WNR1000v3) */ - {0x00825357, 500, 20000000}, /* BCM5358UB0 ASUS RT-N53A1 */ - {0x00845357, 300, 20000000}, /* BCM5357B0 to check */ - {0x00945357, 500, 20000000}, /* BCM5358 */ - {0x00A45357, 500, 20000000}, /* BCM47186B0 Tenda N60 */ - {0x0085D144, 300, 20000000}, /* BCM5356C0 */ - {0x00B5D144, 300, 20000000}, /* BCM5357C0 */ + {0x00005300, 600, 25000000, 1}, /* BCM4706 to check */ + {0x0022B83A, 300, 20000000, 1}, /* BCM4716B0 ASUS RT-N12 */ + {0x00914716, 354, 20000000, 1}, /* BCM4717A1 to check */ + {0x00A14716, 480, 20000000, 1}, /* BCM4718A1 ASUS RT-N16 */ + {0x00435356, 300, 25000000, 1}, /* BCM5356A1 (RT-N10, WNR1000v3) */ + {0x00825357, 500, 20000000, 1}, /* BCM5358UB0 ASUS RT-N53A1 */ + {0x00845357, 300, 20000000, 1}, /* BCM5357B0 to check */ + {0x00945357, 500, 20000000, 1}, /* BCM5358 */ + {0x00A45357, 500, 20000000, 1}, /* BCM47186B0 Tenda N60 */ + {0x0085D144, 300, 20000000, 1}, /* BCM5356C0 */ + {0x00B5D144, 300, 20000000, 1}, /* BCM5357C0 */ + {0x00015365, 200, 0, 1}, /* BCM5365 */ {0,0,0} }; /* Most popular BCM SoC info */ -struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000}; +struct bcm_socinfo BCM_DEFAULT_SOCINFO = {0x0, 300, 20000000, 0}; struct bcm_socinfo* bcm_get_socinfo_by_socid(uint32_t key) Index: sys/mips/broadcom/std.broadcom =================================================================== --- sys/mips/broadcom/std.broadcom +++ sys/mips/broadcom/std.broadcom @@ -3,5 +3,7 @@ machine mips mipsel -cpu CPU_MIPS74K +makeoptions INTRNG +options INTRNG + files "../broadcom/files.broadcom" Index: sys/mips/broadcom/uart_bus_chipc.c =================================================================== --- sys/mips/broadcom/uart_bus_chipc.c +++ sys/mips/broadcom/uart_bus_chipc.c @@ -45,84 +45,29 @@ #include #include -#include - #include "uart_if.h" #include "bhnd_chipc_if.h" +#include "bcm_socinfo.h" -static int uart_chipc_probe(device_t dev); - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; - -static void -uart_chipc_identify(driver_t *driver, device_t parent) -{ - struct chipc_caps *caps; - - if (device_find_child(parent, "uart", -1) != NULL) - return; - - caps = BHND_CHIPC_GET_CAPS(parent); - - if (caps == NULL) { - device_printf(parent, "error: can't retrieve ChipCommon " - "capabilities\n"); - return; - } - - if (caps->num_uarts == 0) - return; - - /* - * TODO: add more than one UART - */ - BUS_ADD_CHILD(parent, 0, "uart", -1); -} static int uart_chipc_probe(device_t dev) { struct uart_softc *sc; - struct resource *res; - int rid; - int err; - - rid = 0; - res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (res == NULL) { - device_printf(dev, "can't allocate main resource\n"); - return (ENXIO); - } + struct bcm_socinfo *socinfo; sc = device_get_softc(dev); sc->sc_class = &uart_ns8250_class; - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - if (sc->sc_sysdev == NULL) { - device_printf(dev, "missing sysdev\n"); - return (EINVAL); - } - - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - - sc->sc_sysdev->bas.bst = rman_get_bustag(res); - sc->sc_sysdev->bas.bsh = rman_get_bushandle(res); - sc->sc_bas.bst = sc->sc_sysdev->bas.bst; - sc->sc_bas.bsh = sc->sc_sysdev->bas.bsh; - - err = bus_release_resource(dev, SYS_RES_MEMORY, rid, res); - if (err) { - device_printf(dev, "can't release resource [%d]\n", rid); - return (ENXIO); - } - /* We use internal SoC clock generator with non-standart freq MHz */ - return (uart_bus_probe(dev, 0, sc->sc_sysdev->bas.rclk, 0, 0)); + /* TODO: UART rate should be calculated from CPU clock speed + * as fetched from bhnd bus */ + socinfo = bcm_get_socinfo(); + return (uart_bus_probe(dev, 0, socinfo->uartrate, 0, 0)); } static device_method_t uart_chipc_methods[] = { /* Device interface */ - DEVMETHOD(device_identify, uart_chipc_identify), DEVMETHOD(device_probe, uart_chipc_probe), DEVMETHOD(device_attach, uart_bus_attach), DEVMETHOD(device_detach, uart_bus_detach), Index: sys/mips/broadcom/uart_cpu_chipc.c =================================================================== --- sys/mips/broadcom/uart_cpu_chipc.c +++ sys/mips/broadcom/uart_cpu_chipc.c @@ -39,6 +39,8 @@ #include +#include + #include #include #include @@ -48,31 +50,74 @@ bus_space_tag_t uart_bus_space_io; bus_space_tag_t uart_bus_space_mem; +static struct uart_class *chipc_uart_class = &uart_ns8250_class; + +#define CHIPC_UART_BAUDRATE 115200 + int uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) { return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); } -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) +static int +uart_cpu_init(struct uart_devinfo *di, int uart, int baudrate) { - struct uart_class *class; struct bcm_socinfo *socinfo; + if (uart >= CHIPC_UART_MAX) + return (EINVAL); + socinfo = bcm_get_socinfo(); - class = &uart_ns8250_class; - di->ops = uart_getops(class); + di->ops = uart_getops(chipc_uart_class); di->bas.chan = 0; - di->bas.bst = mips_bus_space_generic; - di->bas.bsh = (bus_space_handle_t)BCM_SOCREG(BCM_REG_CHIPC_UART); + di->bas.bst = uart_bus_space_mem; + di->bas.bsh = (bus_space_handle_t) BCM_SOCREG(CHIPC_UART(uart)); di->bas.regshft = 0; di->bas.rclk = socinfo->uartrate; /* in Hz */ - di->baudrate = 115200; + di->baudrate = baudrate; di->databits = 8; di->stopbits = 1; di->parity = UART_PARITY_NONE; + + return (0); +} + +int +uart_cpu_getdev(int devtype, struct uart_devinfo *di) +{ + int ivar; + uart_bus_space_io = NULL; uart_bus_space_mem = mips_bus_space_generic; - return (0); + + /* Check the environment. */ + if (uart_getenv(devtype, di, chipc_uart_class) == 0) + return (0); + + /* Scan the device hints for the first matching device */ + for (int i = 0; i < CHIPC_UART_MAX; i++) { + if (resource_int_value("uart", i, "flags", &ivar)) + continue; + + /* Check usability */ + if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar)) + continue; + + if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar)) + continue; + + if (resource_int_value("uart", i, "disabled", &ivar) == 0 && + ivar == 0) + continue; + + /* Found */ + if (resource_int_value("uart", i, "baud", &ivar) != 0) + ivar = CHIPC_UART_BAUDRATE; + + return (uart_cpu_init(di, i, ivar)); + } + + /* Default to uart0/115200 */ + return (uart_cpu_init(di, 0, CHIPC_UART_BAUDRATE)); } Index: sys/mips/conf/BCM =================================================================== --- sys/mips/conf/BCM +++ sys/mips/conf/BCM @@ -6,6 +6,7 @@ # ident BCM +cpu CPU_MIPS74K hints "BCM.hints" include "../broadcom/std.broadcom" @@ -16,9 +17,6 @@ options BREAK_TO_DEBUGGER options BOOTVERBOSE=0 -makeoptions INTRNG -options INTRNG - makeoptions TRAMPLOADADDR=0x80800000 makeoptions DEBUG="-g3" #Build kernel with gdb(1) debug symbols makeoptions MODULES_OVERRIDE="" Index: sys/mips/conf/BCM.hints =================================================================== --- sys/mips/conf/BCM.hints +++ sys/mips/conf/BCM.hints @@ -2,4 +2,3 @@ hint.bhnd.0.at="nexus0" hint.bhnd.0.maddr="0x18000000" hint.bhnd.0.msize="0x00100000" - Index: sys/mips/conf/SENTRY5 =================================================================== --- sys/mips/conf/SENTRY5 +++ sys/mips/conf/SENTRY5 @@ -25,11 +25,11 @@ # ident SENTRY5 +cpu CPU_MIPS4KC +makeoptions TRAMPLOADADDR=0x807963c0 -# XXX only siba should be hardwired for now; we will use -# bus enumeration there hints "SENTRY5.hints" -include "../sentry5/std.sentry5" +include "../broadcom/std.broadcom" # sentry5 normally ships with cfe firmware; use the console for now options CFE @@ -78,11 +78,10 @@ device uhci # UHCI PCI->USB interface device ehci # EHCI PCI->USB interface (USB 2.0) -# need to teach the code to ignore the bridge.... +device cfi # parallel flash +device cfid - -# XXX notyet; need to be auto probed children of siba_cc. -#device uart +device uart device loop device ether Index: sys/mips/conf/SENTRY5.hints =================================================================== --- sys/mips/conf/SENTRY5.hints +++ sys/mips/conf/SENTRY5.hints @@ -1,5 +1,7 @@ # $FreeBSD$ hint.bhnd.0.at="nexus0" -hint.bhnd.0.maddr="0x18000000" -hint.bhnd.0.msize="0x1000" -# XXX irq? +hint.bhnd.0.maddr="0x18000000" +hint.bhnd.0.msize="0x00100000" + +# console on uart1 +hint.uart.1.flags="0x10" Index: sys/mips/sentry5/files.sentry5 =================================================================== --- sys/mips/sentry5/files.sentry5 +++ /dev/null @@ -1,9 +0,0 @@ -# $FreeBSD$ - -# TODO: Add attachment elsehwere in the tree -# for USB 1.1 OHCI, Ethernet and IPSEC cores -# which are believed to be devices we have drivers for -# which just need to be tweaked for attachment to an SSB system bus. -mips/sentry5/s5_machdep.c standard -mips/mips/intr_machdep.c standard -mips/mips/tick.c standard Index: sys/mips/sentry5/obio.c =================================================================== --- sys/mips/sentry5/obio.c +++ /dev/null @@ -1,183 +0,0 @@ -/* $NetBSD: obio.c,v 1.11 2003/07/15 00:25:05 lukem Exp $ */ - -/*- - * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * On-board device autoconfiguration support for Broadcom Sentry5 - * based boards. - * XXX This is totally bogus and is just enough to get the console hopefully - * running on the sentry5. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -int obio_probe(device_t); -int obio_attach(device_t); - -/* - * A bit tricky and hackish. Since we need OBIO to rely - * on PCI we make it pseudo-pci device. But there should - * be only one such device, so we use this static flag - * to prevent false positives on every realPCI device probe. - */ -static int have_one = 0; - -int -obio_probe(device_t dev) -{ - if (!have_one) { - have_one = 1; - return 0; - } - return (ENXIO); -} - -int -obio_attach(device_t dev) -{ - struct obio_softc *sc = device_get_softc(dev); - - sc->oba_st = MIPS_BUS_SPACE_IO; - sc->oba_addr = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - sc->oba_size = 0x03FFFFFF; /* XXX sb pci bus 0 aperture size? */ - sc->oba_rman.rm_type = RMAN_ARRAY; - sc->oba_rman.rm_descr = "OBIO I/O"; - if (rman_init(&sc->oba_rman) != 0 || - rman_manage_region(&sc->oba_rman, - sc->oba_addr, sc->oba_addr + sc->oba_size) != 0) - panic("obio_attach: failed to set up I/O rman"); - sc->oba_irq_rman.rm_type = RMAN_ARRAY; - sc->oba_irq_rman.rm_descr = "OBIO IRQ"; - - /* - * This module is intended for UART purposes only and - * it's IRQ is 4 - */ - if (rman_init(&sc->oba_irq_rman) != 0 || - rman_manage_region(&sc->oba_irq_rman, 4, 4) != 0) - panic("obio_attach: failed to set up IRQ rman"); - - device_add_child(dev, "uart", 0); - bus_generic_probe(dev); - bus_generic_attach(dev); - - return (0); -} - -static struct resource * -obio_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct resource *rv; - struct rman *rm; - bus_space_handle_t bh = 0; - struct obio_softc *sc = device_get_softc(bus); - - switch (type) { - case SYS_RES_IRQ: - rm = &sc->oba_irq_rman; - break; - case SYS_RES_MEMORY: - return (NULL); - case SYS_RES_IOPORT: - rm = &sc->oba_rman; - bh = sc->oba_addr; - start = bh; - break; - default: - return (NULL); - } - - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) - return (NULL); - if (type == SYS_RES_IRQ) - return (rv); - rman_set_rid(rv, *rid); - rman_set_bustag(rv, mips_bus_space_generic); - rman_set_bushandle(rv, bh); - - if (0) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - return (rv); - -} - -static int -obio_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - return (0); -} -static device_method_t obio_methods[] = { - DEVMETHOD(device_probe, obio_probe), - DEVMETHOD(device_attach, obio_attach), - - DEVMETHOD(bus_alloc_resource, obio_alloc_resource), - DEVMETHOD(bus_activate_resource, obio_activate_resource), - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), - - {0, 0}, -}; - -static driver_t obio_driver = { - "obio", - obio_methods, - sizeof(struct obio_softc), -}; -static devclass_t obio_devclass; - -DRIVER_MODULE(obio, pci, obio_driver, obio_devclass, 0, 0); Index: sys/mips/sentry5/obiovar.h =================================================================== --- sys/mips/sentry5/obiovar.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */ - -/*- - * Copyright (c) 2002, 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _SENTRY5_OBIOVAR_H_ -#define _SENTRY5_OBIOVAR_H_ - -#include - -struct obio_softc { - bus_space_tag_t oba_st; /* bus space tag */ - bus_addr_t oba_addr; /* address of device */ - bus_size_t oba_size; /* size of device */ - int oba_width; /* bus width */ - int oba_irq; /* XINT interrupt bit # */ - struct rman oba_rman; - struct rman oba_irq_rman; - -}; -extern struct bus_space obio_bs_tag; - -#endif /* _SENTRY5_OBIOVAR_H_ */ Index: sys/mips/sentry5/s5_machdep.c =================================================================== --- sys/mips/sentry5/s5_machdep.c +++ /dev/null @@ -1,223 +0,0 @@ -/*- - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_ddb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#ifdef CFE -#include -#endif - -extern int *edata; -extern int *end; - -void -platform_cpu_init() -{ - /* Nothing special */ -} - -static void -mips_init(void) -{ - int i, j; - - printf("entry: mips_init()\n"); - -#ifdef CFE - /* - * Query DRAM memory map from CFE. - */ - physmem = 0; - for (i = 0; i < 10; i += 2) { - int result; - uint64_t addr, len, type; - - result = cfe_enummem(i, 0, &addr, &len, &type); - if (result < 0) { - phys_avail[i] = phys_avail[i + 1] = 0; - break; - } - if (type != CFE_MI_AVAILABLE) - continue; - - phys_avail[i] = addr; - if (i == 0 && addr == 0) { - /* - * If this is the first physical memory segment probed - * from CFE, omit the region at the start of physical - * memory where the kernel has been loaded. - */ - phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end); - } - phys_avail[i + 1] = addr + len; - physmem += len; - } - - realmem = btoc(physmem); -#endif - - for (j = 0; j < i; j++) - dump_avail[j] = phys_avail[j]; - - physmem = realmem; - - init_param1(); - init_param2(physmem); - mips_cpu_init(); - pmap_bootstrap(); - mips_proc0_init(); - mutex_init(); - kdb_init(); -#ifdef KDB - if (boothowto & RB_KDB) - kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); -#endif -} - -void -platform_reset(void) -{ - -#if defined(CFE) - cfe_exit(0, 0); -#else - *((volatile uint8_t *)MIPS_PHYS_TO_KSEG1(SENTRY5_EXTIFADR)) = 0x80; -#endif -} - -void -platform_start(__register_t a0, __register_t a1, __register_t a2, - __register_t a3) -{ - vm_offset_t kernend; - uint64_t platform_counter_freq; - - /* clear the BSS and SBSS segments */ - kernend = (vm_offset_t)&end; - memset(&edata, 0, kernend - (vm_offset_t)(&edata)); - - mips_postboot_fixup(); - - /* Initialize pcpu stuff */ - mips_pcpu0_init(); - -#ifdef CFE - /* - * Initialize CFE firmware trampolines before - * we initialize the low-level console. - * - * CFE passes the following values in registers: - * a0: firmware handle - * a2: firmware entry point - * a3: entry point seal - */ - if (a3 == CFE_EPTSEAL) - cfe_init(a0, a2); -#endif - cninit(); - - mips_init(); - -# if 0 - /* - * Probe the Broadcom Sentry5's on-chip PLL clock registers - * and discover the CPU pipeline clock and bus clock - * multipliers from this. - * XXX: Wrong place. You have to ask the ChipCommon - * or External Interface cores on the SiBa. - */ - uint32_t busmult, cpumult, refclock, clkcfg1; -#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F -#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 -#define S5_CLKCFG1_BUSMULT_SHIFT 5 -#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 -#define S5_CLKCFG1_CPUMULT_SHIFT 10 - - counter_freq = 100000000; /* XXX */ - - clkcfg1 = s5_rd_clkcfg1(); - printf("clkcfg1 = 0x%08x\n", clkcfg1); - - refclock = clkcfg1 & 0x1F; - busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; - cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; - - printf("refclock = %u\n", refclock); - printf("busmult = %u\n", busmult); - printf("cpumult = %u\n", cpumult); - - counter_freq = cpumult * refclock; -# else - platform_counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */ -# endif - - mips_timer_init_params(platform_counter_freq, 0); -} Index: sys/mips/sentry5/s5reg.h =================================================================== --- sys/mips/sentry5/s5reg.h +++ /dev/null @@ -1,58 +0,0 @@ -/* $FreeBSD$ */ - -#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_ -#define _MIPS32_SENTRY5_SENTRY5REG_H_ - -#define SENTRY5_UART0ADR 0x18000300 -#define SENTRY5_UART1ADR 0x18000400 - -/* Reset register implemented here in a PLD device. */ -#define SENTRY5_EXTIFADR 0x1F000000 -#define SENTRY5_DORESET 0x80 - -/* - * Custom CP0 register macros. - * XXX: This really needs the mips cpuregs.h file for the barrier. - */ -#define S5_RDRW32_C0P0_CUST22(n,r) \ -static __inline u_int32_t \ -s5_rd_ ## n (void) \ -{ \ - int v0; \ - __asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \ - : [v0] "=&r"(v0)); \ - /*mips_barrier();*/ \ - return (v0); \ -} \ -static __inline void \ -s5_wr_ ## n (u_int32_t a0) \ -{ \ - __asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \ - __XSTRING(COP0_SYNC)";" \ - "nop;" \ - "nop;" \ - : \ - : [a0] "r"(a0)); \ - /*mips_barrier();*/ \ -} struct __hack - -/* - * All 5 of these sub-registers are used by Linux. - * There is a further custom register at 25 which is not used. - */ -#define S5_CP0_DIAG 0 -#define S5_CP0_CLKCFG1 1 -#define S5_CP0_CLKCFG2 2 -#define S5_CP0_SYNC 3 -#define S5_CP0_CLKCFG3 4 -#define S5_CP0_RESET 5 - -/* s5_[rd|wr]_xxx() */ -S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG); -S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1); -S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2); -S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC); -S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3); -S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET); - -#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */ Index: sys/mips/sentry5/std.sentry5 =================================================================== --- sys/mips/sentry5/std.sentry5 +++ /dev/null @@ -1,10 +0,0 @@ -# $FreeBSD$ -# - -machine mips mipsel - -cpu CPU_MIPS4KC -options CPU_SENTRY5 # XXX should this be a - # sub-cpu option? -files "../sentry5/files.sentry5" - Index: sys/mips/sentry5/uart_bus_sbusart.c =================================================================== --- sys/mips/sentry5/uart_bus_sbusart.c +++ /dev/null @@ -1,95 +0,0 @@ -/*- - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ - -/* - * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is - * experimental and was written for MIPS32 port. - */ -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - -#include - -#include "uart_if.h" - -static int uart_malta_probe(device_t dev); - -extern struct uart_class malta_uart_class; - -static device_method_t uart_malta_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_malta_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_malta_driver = { - uart_driver_name, - uart_malta_methods, - sizeof(struct uart_softc), -}; - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; -static int -uart_malta_probe(device_t dev) -{ - struct uart_softc *sc; - - sc = device_get_softc(dev); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - sc->sc_class = &uart_ns8250_class; - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - sc->sc_sysdev->bas.bst = mips_bus_space_generic; - sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - sc->sc_bas.bst = mips_bus_space_generic; - sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - return(uart_bus_probe(dev, 0, 0, 0, 0)); -} - -DRIVER_MODULE(uart, obio, uart_malta_driver, uart_devclass, 0, 0); Index: sys/mips/sentry5/uart_cpu_sbusart.c =================================================================== --- sys/mips/sentry5/uart_cpu_sbusart.c +++ /dev/null @@ -1,82 +0,0 @@ -/*- - * Copyright (c) 2006 Wojciech A. Koszek - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id$ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ -/* - * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is - * experimental and was written for MIPS32 port. - */ -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include - -#include -#include - -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -extern struct uart_ops malta_usart_ops; -extern struct bus_space malta_bs_tag; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = 0; - di->bas.regshft = 0; - di->bas.rclk = 0; - di->baudrate = 115200; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - - uart_bus_space_io = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - uart_bus_space_mem = mips_bus_space_generic; - di->bas.bsh = MIPS_PHYS_TO_KSEG1(SENTRY5_UART1ADR); - return (0); -}