Index: sys/dev/bhnd/bcma/bcma.c
===================================================================
--- sys/dev/bhnd/bcma/bcma.c
+++ sys/dev/bhnd/bcma/bcma.c
@@ -43,6 +43,7 @@
 
 #include "bcma_eromreg.h"
 #include "bcma_eromvar.h"
+#include <dev/bhnd/bhnd_core.h>
 
 int
 bcma_probe(device_t dev)
@@ -217,9 +218,33 @@
 	if (dinfo->res_agent == NULL)
 		return (ENODEV);
 
-	// TODO - perform reset
+	/* Start reset */
+	bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, BHND_RESET_CF_ENABLE);
+	bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF);
+	DELAY(10);
 
-	return (ENXIO);
+	/* Disable clock */
+	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, flags);
+	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
+	DELAY(10);
+
+	/* Enable clocks & force clock gating */
+	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN |
+	    BHND_CF_FGC | flags);
+	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
+	DELAY(10);
+
+	/* Complete reset */
+	bhnd_bus_write_4(dinfo->res_agent, BHND_RESET_CF, 0);
+	bhnd_bus_read_4(dinfo->res_agent, BHND_RESET_CF);
+	DELAY(10);
+
+	/* Release force clock gating */
+	bhnd_bus_write_4(dinfo->res_agent, BHND_CF, BHND_CF_CLOCK_EN | flags);
+	bhnd_bus_read_4(dinfo->res_agent, BHND_CF);
+	DELAY(10);
+
+	return (0);
 }
 
 static int
Index: sys/dev/bhnd/bhnd_core.h
===================================================================
--- sys/dev/bhnd/bhnd_core.h
+++ sys/dev/bhnd/bhnd_core.h
@@ -25,19 +25,27 @@
 #define _BHND_BHND_CORE_H_
 
 /* Common core control flags */
-#define	BHND_CF_BIST_EN		0x8000		/**< ??? */
+#define	BHND_CF 		0x0408
+#define	BHND_CF_BIST_EN		0x8000		/**< built-in self test */
 #define	BHND_CF_PME_EN		0x4000		/**< ??? */
 #define	BHND_CF_CORE_BITS	0x3ffc		/**< core specific flag mask */
 #define	BHND_CF_FGC		0x0002		/**< force clock gating */
 #define	BHND_CF_CLOCK_EN	0x0001		/**< enable clock */
 
 /* Common core status flags */
+#define	BHND_SF			0x0500
 #define	BHND_SF_BIST_DONE	0x8000		/**< ??? */
 #define	BHND_SF_BIST_ERROR	0x4000		/**< ??? */
 #define	BHND_SF_GATED_CLK	0x2000		/**< clock gated */
 #define	BHND_SF_DMA64		0x1000		/**< supports 64-bit DMA */
 #define	BHND_SF_CORE_BITS	0x0fff		/**< core-specific status mask */
 
+/*Reset core control flags */
+#define	BHND_RESET_CF		0x0800
+#define	BHND_RESET_CF_ENABLE	0x0001
+
+#define	BHND_RESET_SF		0x0804
+
 /* 
  * A register that is common to all cores to
  * communicate w/PMU regarding clock control.