Index: sys/dev/etherswitch/rtl8366/rtl8366rb.c
===================================================================
--- sys/dev/etherswitch/rtl8366/rtl8366rb.c
+++ sys/dev/etherswitch/rtl8366/rtl8366rb.c
@@ -74,6 +74,7 @@
 	struct ifnet	*ifp[RTL8366_NUM_PHYS];
 	struct callout	callout_tick;
 	etherswitch_info_t	info;
+	int		chip_type;	/* 0 = RTL8366RB, 1 = RTL8366SR */
 };
 
 #define RTL_LOCK(_sc)	mtx_lock(&(_sc)->sc_mtx)
@@ -121,7 +122,6 @@
 static int rtl8366rb_ifmedia_upd(struct ifnet *);
 static void rtl8366rb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 
-static int chip_type = 0;	/* 0 = RTL8366RB, 1 = RTL8366SR */
 
 static void
 rtl8366rb_identify(driver_t *driver, device_t parent)
@@ -139,9 +139,13 @@
 static int
 rtl8366rb_probe(device_t dev)
 {
+	struct rtl8366rb_softc *sc;
+
+	sc = device_get_softc(dev);
+	bzero(sc, sizeof(*sc));
 	if (smi_probe(dev) != 0)
 		return (ENXIO);
-	if(chip_type == 0)
+	if(sc->chip_type == 0)
 		device_set_desc(dev, "RTL8366RB Ethernet Switch Controller");
 	else
 		device_set_desc(dev, "RTL8366SR Ethernet Switch Controller");
@@ -200,7 +204,6 @@
 	int i;
 
 	sc = device_get_softc(dev);
-	bzero(sc, sizeof(*sc));
 	sc->dev = dev;
 	mtx_init(&sc->sc_mtx, "rtl8366rb", NULL, MTX_DEF);
 	sc->smi_acquired = 0;
@@ -213,7 +216,7 @@
 	sc->info.es_nports = RTL8366_NUM_PORTS;
 	sc->info.es_nvlangroups = RTL8366_NUM_VLANS;
 	sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q;
-	if(chip_type == 0)
+	if(sc->chip_type == 0)
 		sprintf(sc->info.es_name, "Realtek RTL8366RB");
 	else
 		sprintf(sc->info.es_name, "Realtek RTL8366SR");
@@ -344,12 +347,14 @@
 static int
 smi_probe(device_t dev)
 {
+	struct rtl8366rb_softc *sc;
 	device_t iicbus, iicha;
 	int err, i, j;
 	uint16_t chipid;
 	char bytes[2];
 	int xferd;
 
+	sc = device_get_softc(dev);
 	iicbus = device_get_parent(dev);
 	iicha = device_get_parent(iicbus);
 
@@ -384,13 +389,13 @@
 		chipid = ((bytes[1] & 0xff) << 8) | (bytes[0] & 0xff);
 		if (i == 0 && chipid == RTL8366RB_CIR_ID8366RB) {
 			DPRINTF(dev, "chip id 0x%04x\n", chipid);
-			chip_type = 0;
+			sc->chip_type = 0;
 			err = 0;
 			break;
 		}
 		if (i == 1 && chipid == RTL8366SR_CIR_ID8366SR) {
 			DPRINTF(dev, "chip id 0x%04x\n", chipid);
-			chip_type = 1;
+			sc->chip_type = 1;
 			err = 0;
 			break;
 		}
@@ -450,10 +455,12 @@
 	device_t iicbus = device_get_parent(dev);
 	struct iicbus_ivar *devi = IICBUS_IVAR(dev);
 	int slave = devi->addr;
+	struct rtl8366rb_softc *sc;
 
 	RTL_SMI_ACQUIRED_ASSERT((struct rtl8366rb_softc *)device_get_softc(dev));
 
-	if(chip_type == 1) {   // RTL8366SR work around
+	sc = device_get_softc(dev);
+	if(sc->chip_type == 1) {   // RTL8366SR work around
 		// this is same work around at probe
 		for (int i=3; i--; )
 			IICBUS_STOP(device_get_parent(device_get_parent(dev)));
@@ -709,7 +716,7 @@
 	sc->vid[g] |= ETHERSWITCH_VID_VALID;
 	rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_DOT1Q_REG, g),
 		(vg->es_vid << RTL8366_VMCR_DOT1Q_VID_SHIFT) & RTL8366_VMCR_DOT1Q_VID_MASK);
-	if(chip_type == 0) {
+	if(sc->chip_type == 0) {
 		rtl_writereg(dev, RTL8366_VMCR(RTL8366_VMCR_MU_REG, g),
 	 	    ((vg->es_member_ports << RTL8366_VMCR_MU_MEMBER_SHIFT) & RTL8366_VMCR_MU_MEMBER_MASK) |
 		    ((vg->es_untagged_ports << RTL8366_VMCR_MU_UNTAG_SHIFT) & RTL8366_VMCR_MU_UNTAG_MASK));
Index: sys/dev/etherswitch/rtl8366/rtl8366rbvar.h
===================================================================
--- sys/dev/etherswitch/rtl8366/rtl8366rbvar.h
+++ sys/dev/etherswitch/rtl8366/rtl8366rbvar.h
@@ -66,7 +66,7 @@
 #define RTL8366_SSCR2_DROP_UNKNOWN_DA		0x0001
 
 /* Port Link Status: two ports per register */
-#define RTL8366_PLSR_BASE			(chip_type == 0 ? 0x0014 : 0x0060)
+#define RTL8366_PLSR_BASE			(sc->chip_type == 0 ? 0x0014 : 0x0060)
 #define RTL8366_PLSR_SPEED_MASK	0x03
 #define RTL8366_PLSR_SPEED_10		0x00
 #define RTL8366_PLSR_SPEED_100	0x01
@@ -78,8 +78,8 @@
 #define RTL8366_PLSR_NO_AUTO		0x80
 
 /* VLAN Member Configuration, 3 or 2 registers per VLAN */
-#define RTL8366_VMCR_BASE			(chip_type == 0 ? 0x0020 : 0x0016)
-#define RTL8366_VMCR_MULT		(chip_type == 0 ? 3 : 2)
+#define RTL8366_VMCR_BASE			(sc->chip_type == 0 ? 0x0020 : 0x0016)
+#define RTL8366_VMCR_MULT		(sc->chip_type == 0 ? 3 : 2)
 #define RTL8366_VMCR_DOT1Q_REG	0
 #define RTL8366_VMCR_DOT1Q_VID_SHIFT	0
 #define RTL8366_VMCR_DOT1Q_VID_MASK	0x0fff
@@ -87,12 +87,12 @@
 #define RTL8366_VMCR_DOT1Q_PCP_MASK	0x7000
 #define RTL8366_VMCR_MU_REG		1
 #define RTL8366_VMCR_MU_MEMBER_SHIFT	0
-#define RTL8366_VMCR_MU_MEMBER_MASK	(chip_type == 0 ? 0x00ff : 0x003f)
-#define RTL8366_VMCR_MU_UNTAG_SHIFT	(chip_type == 0 ? 8 : 6)
-#define RTL8366_VMCR_MU_UNTAG_MASK	(chip_type == 0 ? 0xff00 : 0x0fc0)
-#define RTL8366_VMCR_FID_REG		(chip_type == 0 ? 2 : 1)
-#define RTL8366_VMCR_FID_FID_SHIFT	(chip_type == 0 ? 0 : 12)
-#define RTL8366_VMCR_FID_FID_MASK	(chip_type == 0 ? 0x0007 : 0x7000)
+#define RTL8366_VMCR_MU_MEMBER_MASK	(sc->chip_type == 0 ? 0x00ff : 0x003f)
+#define RTL8366_VMCR_MU_UNTAG_SHIFT	(sc->chip_type == 0 ? 8 : 6)
+#define RTL8366_VMCR_MU_UNTAG_MASK	(sc->chip_type == 0 ? 0xff00 : 0x0fc0)
+#define RTL8366_VMCR_FID_REG		(sc->chip_type == 0 ? 2 : 1)
+#define RTL8366_VMCR_FID_FID_SHIFT	(sc->chip_type == 0 ? 0 : 12)
+#define RTL8366_VMCR_FID_FID_MASK	(sc->chip_type == 0 ? 0x0007 : 0x7000)
 #define RTL8366_VMCR(_reg, _vlan) \
 	(RTL8366_VMCR_BASE + _reg + _vlan * RTL8366_VMCR_MULT)
 /* VLAN Identifier */
@@ -111,7 +111,7 @@
 	>> RTL8366_VMCR_MU_UNTAG_SHIFT)
 /* Forwarding ID */
 #define RTL8366_VMCR_FID(_r) \
-	(chip_type == 0 ? (_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) : \
+	(sc->chip_type == 0 ? (_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) : \
 		((_r[RTL8366_VMCR_FID_REG] & RTL8366_VMCR_FID_FID_MASK) \
 		>> RTL8366_VMCR_FID_FID_SHIFT))
 
@@ -120,7 +120,7 @@
  * Determines the VID for untagged ingress frames through
  * index into VMC.
  */
-#define RTL8366_PVCR_BASE			(chip_type == 0 ? 0x0063 : 0x0058)
+#define RTL8366_PVCR_BASE			(sc->chip_type == 0 ? 0x0063 : 0x0058)
 #define RTL8366_PVCR_PORT_SHIFT	4
 #define RTL8366_PVCR_PORT_PERREG	(16 / RTL8366_PVCR_PORT_SHIFT)
 #define RTL8366_PVCR_PORT_MASK	0x000f
@@ -138,7 +138,7 @@
 #define RTL8366_RCR_SOFT_RESET	0x0002
 
 /* Chip Version Control: CHIP_VER[3:0] */
-#define RTL8366_CVCR				(chip_type == 0 ? 0x050A : 0x0104)
+#define RTL8366_CVCR				(sc->chip_type == 0 ? 0x050A : 0x0104)
 /* Chip Identifier */
 #define RTL8366RB_CIR				0x0509
 #define RTL8366RB_CIR_ID8366RB		0x5937
@@ -150,7 +150,7 @@
 
 /* MIB registers */
 #define RTL8366_MCNT_BASE			0x1000
-#define RTL8366_MCTLR				(chip_type == 0 ? 0x13f0 : 0x11F0)
+#define RTL8366_MCTLR				(sc->chip_type == 0 ? 0x13f0 : 0x11F0)
 #define RTL8366_MCTLR_BUSY		0x0001
 #define RTL8366_MCTLR_RESET		0x0002
 #define RTL8366_MCTLR_RESET_PORT_MASK	0x00fc
@@ -162,15 +162,15 @@
 	(1 << ((_p) + 2))
 
 /* PHY Access Control */
-#define RTL8366_PACR				(chip_type == 0 ? 0x8000 : 0x8028)
+#define RTL8366_PACR				(sc->chip_type == 0 ? 0x8000 : 0x8028)
 #define RTL8366_PACR_WRITE		0x0000
 #define RTL8366_PACR_READ			0x0001
 
 /* PHY Access Data */
-#define	RTL8366_PADR				(chip_type == 0 ? 0x8002 : 0x8029)
+#define	RTL8366_PADR				(sc->chip_type == 0 ? 0x8002 : 0x8029)
 
 #define RTL8366_PHYREG(phy, page, reg) \
-	(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
+	(0x8000 | (1 << (((phy) & 0x1f) + 9)) | (((page) & (sc->chip_type == 0 ? 0xf : 0x7)) << 5) | ((reg) & 0x1f))
 
 /* general characteristics of the chip */
 #define	RTL8366_CPU_PORT			5