Index: sys/dev/aic7xxx/aic79xx.h =================================================================== --- sys/dev/aic7xxx/aic79xx.h +++ sys/dev/aic7xxx/aic79xx.h @@ -478,7 +478,7 @@ * each S/G element is expired, its datacnt field is checked to see * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the * residual sg ptr and the transfer is considered complete. If the - * sequencer determines that there is a residual in the tranfer, or + * sequencer determines that there is a residual in the transfer, or * there is non-zero status, it will set the SG_STATUS_VALID flag in * sgptr and dma the scb back into host memory. To sumarize: * @@ -486,7 +486,7 @@ * o A residual has occurred if SG_FULL_RESID is set in sgptr, * or residual_sgptr does not have SG_LIST_NULL set. * - * o We are transfering the last segment if residual_datacnt has + * o We are transferring the last segment if residual_datacnt has * the SG_LAST_SEG flag set. * * Host: @@ -529,7 +529,7 @@ */ /* - * Definition of a scatter/gather element as transfered to the controller. + * Definition of a scatter/gather element as transferred to the controller. * The aic7xxx chips only support a 24bit length. We use the top byte of * the length to store additional address bits and a flag to indicate * that a given segment terminates the transfer. This gives us an Index: sys/dev/aic7xxx/aic79xx.c =================================================================== --- sys/dev/aic7xxx/aic79xx.c +++ sys/dev/aic7xxx/aic79xx.c @@ -1206,7 +1206,7 @@ * that requires host assistance for completion. * While handling the message phase(s), we will be * notified by the sequencer after each byte is - * transfered so we can track bus phase changes. + * transferred so we can track bus phase changes. * * If this is the first time we've seen a HOST_MSG_LOOP * interrupt, initialize the state of the host message @@ -1620,7 +1620,7 @@ /* * Although the driver does not care about the * 'Selection in Progress' status bit, the busy - * LED does. SELINGO is only cleared by a sucessfull + * LED does. SELINGO is only cleared by a successful * selection, so we must manually clear it to insure * the LED turns off just incase no future successful * selections occur (e.g. no devices on the bus). @@ -2695,7 +2695,7 @@ ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); ahd_outb(ahd, SIMODE1, simode1); /* - * SCSIINT seems to glitch occassionally when + * SCSIINT seems to glitch occasionally when * the interrupt masks are restored. Clear SCSIINT * one more time so that only persistent errors * are seen as a real interrupt. @@ -3023,7 +3023,7 @@ /* * Update the bitmask of targets for which the controller should - * negotiate with at the next convenient oportunity. This currently + * negotiate with at the next convenient opportunity. This currently * means the next time we send the initial identify messages for * a new transaction. */ @@ -3374,7 +3374,7 @@ /* * During packetized transfers, the target will - * give us the oportunity to send command packets + * give us the opportunity to send command packets * without us asserting attention. */ if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) @@ -4838,7 +4838,7 @@ /* * Requeue all tagged commands for this target - * currently in our posession so they can be + * currently in our possession so they can be * converted to untagged commands. */ ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), @@ -5489,7 +5489,7 @@ /* * Reset the controller and record some information about it * that is only available just after a reset. If "reinit" is - * non-zero, this reset occured after initial configuration + * non-zero, this reset occurred after initial configuration * and the caller requests that the chip be fully reinitialized * to a runable state. Chip interrupts are *not* enabled after * a reinitialization. The caller must enable interrupts via @@ -5742,7 +5742,7 @@ } /* - * Note that we were successfull + * Note that we were successful */ return (0); @@ -8785,7 +8785,7 @@ cur_patch += cur_patch->skip_patch; } else { /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to + * one and wait for our instruction pointer to * hit this point. */ cur_patch++; @@ -9664,7 +9664,7 @@ return (error); /* - * Write the data. If we don't get throught the loop at + * Write the data. If we don't get thought the loop at * least once, the arguments were invalid. */ retval = EINVAL; Index: sys/dev/aic7xxx/aic79xx.reg =================================================================== --- sys/dev/aic7xxx/aic79xx.reg +++ sys/dev/aic7xxx/aic79xx.reg @@ -283,7 +283,7 @@ } /* - * Sequencer Interupt Status + * Sequencer Interrupt Status */ register SEQINTSTAT { address 0x00C @@ -643,7 +643,7 @@ } /* - * CMC Recieve Message 0 + * CMC Receive Message 0 */ register CMCRXMSG0 { address 0x090 @@ -654,7 +654,7 @@ } /* - * Overlay Recieve Message 0 + * Overlay Receive Message 0 */ register OVLYRXMSG0 { address 0x090 @@ -690,7 +690,7 @@ } /* - * CMC Recieve Message 1 + * CMC Receive Message 1 */ register CMCRXMSG1 { address 0x091 @@ -700,7 +700,7 @@ } /* - * Overlay Recieve Message 1 + * Overlay Receive Message 1 */ register OVLYRXMSG1 { address 0x091 @@ -735,7 +735,7 @@ } /* - * CMC Recieve Message 2 + * CMC Receive Message 2 */ register CMCRXMSG2 { address 0x092 @@ -745,7 +745,7 @@ } /* - * Overlay Recieve Message 2 + * Overlay Receive Message 2 */ register OVLYRXMSG2 { address 0x092 @@ -774,7 +774,7 @@ } /* - * CMC Recieve Message 3 + * CMC Receive Message 3 */ register CMCRXMSG3 { address 0x093 @@ -784,7 +784,7 @@ } /* - * Overlay Recieve Message 3 + * Overlay Receive Message 3 */ register OVLYRXMSG3 { address 0x093 @@ -1192,7 +1192,7 @@ /* * LQ Packet In - * The last LQ Packet recieved + * The last LQ Packet received */ register LQIN { address 0x020 @@ -2424,7 +2424,7 @@ } /* - * Shaddow Host Address. + * Shadow Host Address. */ register SHADDR { address 0x060 @@ -3726,7 +3726,7 @@ /* * The maximum amount of time to wait, when interrupt coalescing - * is enabled, before issueing a CMDCMPLT interrupt for a completed + * is enabled, before issuing a CMDCMPLT interrupt for a completed * command. */ INT_COALESCING_TIMER { Index: sys/dev/aic7xxx/aic79xx.seq =================================================================== --- sys/dev/aic7xxx/aic79xx.seq +++ sys/dev/aic7xxx/aic79xx.seq @@ -217,7 +217,7 @@ scbdma_tohost_done: test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone; /* - * An SCB has been succesfully uploaded to the host. + * An SCB has been successfully uploaded to the host. * If the SCB was uploaded for some reason other than * bad SCSI status (currently only for underruns), we * queue the SCB for normal completion. Otherwise, we @@ -960,7 +960,7 @@ * This is done to allow the host to send messages outside of an identify * sequence while protecting the seqencer from testing the MK_MESSAGE bit * on an SCB that might not be for the current nexus. (For example, a - * BDR message in responce to a bad reselection would leave us pointed to + * BDR message in response to a bad reselection would leave us pointed to * an SCB that doesn't have anything to do with the current target). * * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, @@ -1507,7 +1507,7 @@ * If the other FIFO needs loading, then it * must not have claimed the S/G cache yet * (SG_CACHE_AVAIL would have been cleared in - * the orginal FIFO mode and we test this above). + * the original FIFO mode and we test this above). * Return to the idle loop so we can process the * FIFO not currently on the bus first. */ @@ -1551,7 +1551,7 @@ test DFSTATUS, PRELOAD_AVAIL jz return; /* * On the A, preloading a segment before HDMAENACK - * comes true can clobber the shaddow address of the + * comes true can clobber the shadow address of the * first segment in the S/G FIFO. Wait until it is * safe to proceed. */ @@ -2004,10 +2004,10 @@ * Defer handling of this NONPACKREQ until we * can be sure it pertains to this FIFO. SAVEPTRS * will not be asserted if the NONPACKREQ is for us, - * so we must simulate it if shaddow is valid. If - * shaddow is not valid, keep running this FIFO until we + * so we must simulate it if shadow is valid. If + * shadow is not valid, keep running this FIFO until we * have satisfied the transfer by loading segments and - * waiting for either shaddow valid or last_seg_done. + * waiting for either shadow valid or last_seg_done. */ test MDFFSTAT, SHVALID jnz pkt_saveptrs; pkt_service_fifo: @@ -2171,7 +2171,7 @@ /* * The unexpected nonpkt phase handler assumes that any * data channel use will have a FIFO reference count. It - * turns out that the status handler doesn't need a refernce + * turns out that the status handler doesn't need a references * count since the status received flag, and thus completion * processing, cannot be set until the handler is finished. * We increment the count here to make the nonpkt handler Index: sys/dev/aic7xxx/aic79xx_inline.h =================================================================== --- sys/dev/aic7xxx/aic79xx_inline.h +++ sys/dev/aic7xxx/aic79xx_inline.h @@ -417,7 +417,7 @@ - (uint8_t *)ahd->qoutfifo); } -/*********************** Miscelaneous Support Functions ***********************/ +/*********************** Miscellaneous Support Functions ***********************/ static __inline void ahd_complete_scb(struct ahd_softc *ahd, struct scb *scb); static __inline void ahd_update_residual(struct ahd_softc *ahd, @@ -534,7 +534,7 @@ ahd_outw(struct ahd_softc *ahd, u_int port, u_int value) { /* - * Write low byte first to accomodate registers + * Write low byte first to accommodate registers * such as PRGMCNT where the order maters. */ ahd_outb(ahd, port, value & 0xFF); Index: sys/dev/aic7xxx/aic79xx_pci.c =================================================================== --- sys/dev/aic7xxx/aic79xx_pci.c +++ sys/dev/aic7xxx/aic79xx_pci.c @@ -489,7 +489,7 @@ * Next create a situation where write combining * or read prefetching could be initiated by the * CPU or host bridge. Our device does not support - * either, so look for data corruption and/or flaged + * either, so look for data corruption and/or flagged * PCI errors. First pause without causing another * chip reset. */ @@ -1011,7 +1011,7 @@ | AHD_FAINT_LED_BUG; /* - * IO Cell paramter setup. + * IO Cell parameter setup. */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); @@ -1032,7 +1032,7 @@ | AHD_BUSFREEREV_BUG; /* - * IO Cell paramter setup. + * IO Cell parameter setup. */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); Index: sys/dev/aic7xxx/aic7xxx.h =================================================================== --- sys/dev/aic7xxx/aic7xxx.h +++ sys/dev/aic7xxx/aic7xxx.h @@ -448,7 +448,7 @@ * each S/G element is expired, its datacnt field is checked to see * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the * residual sg ptr and the transfer is considered complete. If the - * sequencer determines that there is a residual in the tranfer, it + * sequencer determines that there is a residual in the transfer, it * will set the SG_RESID_VALID flag in sgptr and dma the scb back into * host memory. To sumarize: * @@ -456,7 +456,7 @@ * o A residual has occurred if SG_FULL_RESID is set in sgptr, * or residual_sgptr does not have SG_LIST_NULL set. * - * o We are transfering the last segment if residual_datacnt has + * o We are transferring the last segment if residual_datacnt has * the SG_LAST_SEG flag set. * * Host: @@ -510,7 +510,7 @@ */ /* - * Definition of a scatter/gather element as transfered to the controller. + * Definition of a scatter/gather element as transferred to the controller. * The aic7xxx chips only support a 24bit length. We use the top byte of * the length to store additional address bits and a flag to indicate * that a given segment terminates the transfer. This gives us an Index: sys/dev/aic7xxx/aic7xxx.c =================================================================== --- sys/dev/aic7xxx/aic7xxx.c +++ sys/dev/aic7xxx/aic7xxx.c @@ -116,7 +116,7 @@ /* * Valid SCSIRATE values. (p. 3-17) - * Provides a mapping of tranfer periods in ns to the proper value to + * Provides a mapping of transfer periods in ns to the proper value to * stick in the scsixfer reg. */ static struct ahc_syncrate ahc_syncrates[] = @@ -682,7 +682,7 @@ * that requires host assistance for completion. * While handling the message phase(s), we will be * notified by the sequencer after each byte is - * transfered so we can track bus phase changes. + * transferred so we can track bus phase changes. * * If this is the first time we've seen a HOST_MSG_LOOP * interrupt, initialize the state of the host message @@ -925,7 +925,7 @@ scbptr, ahc_inb(ahc, ARG_1), ahc->scb_data->hscbs[scbptr].tag); ahc_dump_card_state(ahc); - panic("for saftey"); + panic("for safety"); break; } case OUT_OF_RANGE: @@ -1171,7 +1171,7 @@ /* * Although the driver does not care about the * 'Selection in Progress' status bit, the busy - * LED does. SELINGO is only cleared by a sucessfull + * LED does. SELINGO is only cleared by a successful * selection, so we must manually clear it to insure * the LED turns off just incase no future successful * selections occur (e.g. no devices on the bus). @@ -1381,7 +1381,7 @@ if (lastphase != P_BUSFREE) { /* * Renegotiate with this device at the - * next oportunity just in case this busfree + * next opportunity just in case this busfree * is due to a negotiation mismatch with the * device. */ @@ -1857,7 +1857,7 @@ /* * Update the bitmask of targets for which the controller should - * negotiate with at the next convenient oportunity. This currently + * negotiate with at the next convenient opportunity. This currently * means the next time we send the initial identify messages for * a new transaction. */ @@ -3627,7 +3627,7 @@ /* * Requeue all tagged commands for this target - * currently in our posession so they can be + * currently in our possession so they can be * converted to untagged commands. */ ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), @@ -4136,7 +4136,7 @@ /* * Reset the controller and record some information about it * that is only available just after a reset. If "reinit" is - * non-zero, this reset occured after initial configuration + * non-zero, this reset occurred after initial configuration * and the caller requests that the chip be fully reinitialized * to a runable state. Chip interrupts are *not* enabled after * a reinitialization. The caller must enable interrupts via @@ -4458,7 +4458,7 @@ ahc->next_queued_scb = ahc_get_scb(ahc); /* - * Note that we were successfull + * Note that we were successful */ return (0); @@ -6543,7 +6543,7 @@ cur_patch += cur_patch->skip_patch; } else { /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to + * one and wait for our instruction pointer to * hit this point. */ cur_patch++; @@ -7247,7 +7247,7 @@ ahc_outb(ahc, SCBPTR, saved_scbptr); aic_scb_timer_reset(scb, 2 * 1000); } else { - /* Go "immediatly" to the bus reset */ + /* Go "immediately" to the bus reset */ /* This shouldn't happen */ ahc_set_recoveryscb(ahc, scb); ahc_print_path(ahc, scb); Index: sys/dev/aic7xxx/aic7xxx.reg =================================================================== --- sys/dev/aic7xxx/aic7xxx.reg +++ sys/dev/aic7xxx/aic7xxx.reg @@ -329,7 +329,7 @@ address 0x00d access_mode RO field OVERRUN 0x80 - field SHVALID 0x40 /* Shaddow Layer non-zero */ + field SHVALID 0x40 /* Shadow Layer non-zero */ field EXP_ACTIVE 0x10 /* SCSI Expander Active */ field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */ field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */ Index: sys/dev/aic7xxx/aic7xxx.seq =================================================================== --- sys/dev/aic7xxx/aic7xxx.seq +++ sys/dev/aic7xxx/aic7xxx.seq @@ -60,7 +60,7 @@ * use byte 27 of the SCB as a psuedo-next pointer and to thread a list * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to - * this list everytime a request sense occurs or after completing a non-tagged + * this list every time a request sense occurs or after completing a non-tagged * command for which a second SCB has been queued. The sequencer will * automatically consume the entries. */ @@ -1489,7 +1489,7 @@ * This is done to allow the host to send messages outside of an identify * sequence while protecting the seqencer from testing the MK_MESSAGE bit * on an SCB that might not be for the current nexus. (For example, a - * BDR message in responce to a bad reselection would leave us pointed to + * BDR message in response to a bad reselection would leave us pointed to * an SCB that doesn't have anything to do with the current target). * * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag, Index: sys/dev/aic7xxx/aic7xxx_inline.h =================================================================== --- sys/dev/aic7xxx/aic7xxx_inline.h +++ sys/dev/aic7xxx/aic7xxx_inline.h @@ -229,7 +229,7 @@ return (ahc->name); } -/*********************** Miscelaneous Support Functions ***********************/ +/********************** Miscellaneous Support Functions ***********************/ static __inline void ahc_update_residual(struct ahc_softc *ahc, struct scb *scb); Index: sys/dev/aic7xxx/aic7xxx_pci.c =================================================================== --- sys/dev/aic7xxx/aic7xxx_pci.c +++ sys/dev/aic7xxx/aic7xxx_pci.c @@ -865,7 +865,7 @@ ahc->bus_suspend = ahc_pci_suspend; ahc->bus_resume = ahc_pci_resume; - /* Remeber how the card was setup in case there is no SEEPROM */ + /* Remember how the card was setup in case there is no SEEPROM */ if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { ahc_pause(ahc); if ((ahc->features & AHC_ULTRA2) != 0) @@ -936,7 +936,7 @@ } /* - * We cannot perform ULTRA speeds without the presense + * We cannot perform ULTRA speeds without the presence * of the external precision resistor. */ if ((ahc->features & AHC_ULTRA) != 0) { @@ -1054,7 +1054,7 @@ } /* - * Test for the presense of external sram in an + * Test for the presence of external sram in an * "unshared" configuration. */ static int Index: sys/dev/aic7xxx/aicasm/aicasm.c =================================================================== --- sys/dev/aic7xxx/aicasm/aicasm.c +++ sys/dev/aic7xxx/aicasm/aicasm.c @@ -668,7 +668,7 @@ cur_patch = STAILQ_NEXT(cur_patch, links); } else { /* Accepted this patch. Advance to the next - * one and wait for our intruction pointer to + * one and wait for our instruction pointer to * hit this point. */ cur_patch = STAILQ_NEXT(cur_patch, links); Index: sys/dev/aic7xxx/aicasm/aicasm_gram.y =================================================================== --- sys/dev/aic7xxx/aicasm/aicasm_gram.y +++ sys/dev/aic7xxx/aicasm/aicasm_gram.y @@ -1286,8 +1286,8 @@ ; /* - * This grammer differs from the one in the aic7xxx - * reference manual since the grammer listed there is + * This grammar differs from the one in the aic7xxx + * reference manual since the grammar listed there is * ambiguous and causes a shift/reduce conflict. * It also seems more logical as the "immediate" * argument is listed as the second arg like the @@ -1753,7 +1753,7 @@ instr = seq_alloc(); f3_instr = &instr->format.format3; if (address->symbol == NULL) { - /* 'dot' referrence. Use the current instruction pointer */ + /* 'dot' reference. Use the current instruction pointer */ addr = instruction_ptr + address->offset; } else if (address->symbol->type == UNINITIALIZED) { /* forward reference */