Index: head/sys/mips/mediatek/mtk_soc.c
===================================================================
--- head/sys/mips/mediatek/mtk_soc.c
+++ head/sys/mips/mediatek/mtk_soc.c
@@ -76,13 +76,17 @@
 static uint32_t
 mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh)
 {
-	uint32_t clk;
+	uint32_t val;
+
+	val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
+	if (val == RT3350_CHIPID0_3)
+		return (MTK_CPU_CLK_320MHZ);
 
-	clk = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
-	clk >>= RT305X_CPU_CLKSEL_OFF;
-	clk &= RT305X_CPU_CLKSEL_MSK;
+	val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
+	val >>= RT305X_CPU_CLKSEL_OFF;
+	val &= RT305X_CPU_CLKSEL_MSK;
 
-	return ((clk == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ);
+	return ((val == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ);
 }
 
 static uint32_t
@@ -265,10 +269,8 @@
 	switch (mtk_soc_socid) {
 	case MTK_SOC_RT3050:  /* fallthrough */
 	case MTK_SOC_RT3052:
-		mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh);
-		break;
 	case MTK_SOC_RT3350:
-		mtk_soc_cpuclk = MTK_CPU_CLK_320MHZ;
+		mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh);
 		break;
 	case MTK_SOC_RT3352:
 		mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh);
Index: head/sys/mips/mediatek/mtk_sysctl.h
===================================================================
--- head/sys/mips/mediatek/mtk_sysctl.h
+++ head/sys/mips/mediatek/mtk_sysctl.h
@@ -52,6 +52,8 @@
 
 #define SYSCFG1_USB_HOST_MODE	(1<<10)
 
+#define RT3350_CHIPID0_3	0x33335452
+
 extern uint32_t	mtk_sysctl_get(uint32_t);
 extern void	mtk_sysctl_set(uint32_t, uint32_t);
 extern void	mtk_sysctl_clr_set(uint32_t, uint32_t, uint32_t);