Index: head/sys/dev/rt/if_rt.c
===================================================================
--- head/sys/dev/rt/if_rt.c
+++ head/sys/dev/rt/if_rt.c
@@ -99,13 +99,14 @@
 #ifdef FDT
 /* more specific and new models should go first */
 static const struct ofw_compat_data rt_compat_data[] = {
-	{ "ralink,rt3050-eth",	RT_CHIPID_RT3050 },
-	{ "ralink,rt3352-eth",	RT_CHIPID_RT3050 },
-	{ "ralink,rt3883-eth",	RT_CHIPID_RT3050 },
-	{ "ralink,rt5350-eth",	RT_CHIPID_RT5350 },
-	{ "ralink,mt7620a-eth",	RT_CHIPID_MT7620 },
-	{ "ralink,mt7621-eth",	RT_CHIPID_MT7621 },
-	{ NULL,			0 }
+	{ "ralink,rt3050-eth",		RT_CHIPID_RT3050 },
+	{ "ralink,rt3352-eth",		RT_CHIPID_RT3050 },
+	{ "ralink,rt3883-eth",		RT_CHIPID_RT3050 },
+	{ "ralink,rt5350-eth",		RT_CHIPID_RT5350 },
+	{ "ralink,mt7620a-eth",		RT_CHIPID_MT7620 },
+	{ "ralink,mt7621-eth",		RT_CHIPID_MT7621 },
+	{ "mediatek,mt7621-eth",	RT_CHIPID_MT7621 },
+	{ NULL,				0 }
 };
 #endif
 
Index: head/sys/mips/mediatek/mtk_ehci.c
===================================================================
--- head/sys/mips/mediatek/mtk_ehci.c
+++ head/sys/mips/mediatek/mtk_ehci.c
@@ -78,7 +78,7 @@
 	if (!ofw_bus_status_okay(self))
 		return (ENXIO);
 
-	if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ehci"))
+	if (!ofw_bus_is_compatible(self, "generic-ehci"))
 		return (ENXIO);
 
 	device_set_desc(self, EHCI_HC_DEVSTR);
Index: head/sys/mips/mediatek/mtk_gpio_v1.c
===================================================================
--- head/sys/mips/mediatek/mtk_gpio_v1.c
+++ head/sys/mips/mediatek/mtk_gpio_v1.c
@@ -281,8 +281,8 @@
 		sc->do_remap = 0;
 	}
 
-	if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node,
-	    "mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0))
+	if (OF_hasprop(node, "ralink,num-gpios") && (OF_getencprop(node,
+	    "ralink,num-gpios", &num_pins, sizeof(num_pins)) >= 0))
 		sc->num_pins = num_pins;
 	else
 		sc->num_pins = MTK_GPIO_PINS;
Index: head/sys/mips/mediatek/mtk_gpio_v2.c
===================================================================
--- head/sys/mips/mediatek/mtk_gpio_v2.c
+++ head/sys/mips/mediatek/mtk_gpio_v2.c
@@ -121,8 +121,8 @@
 #define GPIO_PIORESET(_sc)		GPIO_REG((_sc), 0x0040)
 
 static struct ofw_compat_data compat_data[] = {
-	{ "mtk,mt7621-gpio",	1 },
-	{ "mtk,mt7628-gpio",	1 },
+	{ "mtk,mt7621-gpio-bank",	1 },
+	{ "mtk,mt7628-gpio-bank",	1 },
 	{ NULL,			0 }
 };
 
@@ -281,7 +281,7 @@
 	else
 		sc->num_pins = MTK_GPIO_PINS;
 
-	for (i = 0; i < num_pins; i++) {
+	for (i = 0; i < sc->num_pins; i++) {
 		sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
 		    GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
 		sc->pins[i].intr_polarity = INTR_POLARITY_HIGH;
Index: head/sys/mips/mediatek/mtk_intr_gic.c
===================================================================
--- head/sys/mips/mediatek/mtk_intr_gic.c
+++ head/sys/mips/mediatek/mtk_intr_gic.c
@@ -281,10 +281,10 @@
 	sc = device_get_softc(dev);
 
 	if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
-	    data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
+	    data->fdt.ncells != 3 || data->fdt.cells[1] >= sc->nirqs)
 		return (EINVAL);
 
-	*isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[0]);
+	*isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[1]);
 	return (0);
 #else
 	return (EINVAL);
Index: head/sys/mips/mediatek/mtk_ohci.c
===================================================================
--- head/sys/mips/mediatek/mtk_ohci.c
+++ head/sys/mips/mediatek/mtk_ohci.c
@@ -78,7 +78,7 @@
 	if (!ofw_bus_status_okay(self))
 		return (ENXIO);
 
-	if (!ofw_bus_is_compatible(self, "ralink,rt3xxx-ohci"))
+	if (!ofw_bus_is_compatible(self, "generic-ohci"))
 		return (ENXIO);
 
 	device_set_desc(self, OHCI_HC_DEVSTR);
Index: head/sys/mips/mediatek/mtk_pcie.c
===================================================================
--- head/sys/mips/mediatek/mtk_pcie.c
+++ head/sys/mips/mediatek/mtk_pcie.c
@@ -99,7 +99,7 @@
 	u_long	len;
 };
 
-#define FDT_RANGES_CELLS	(3 * 2)
+#define FDT_RANGES_CELLS	((1 + 2 + 3) * 2)
 
 static void
 mtk_pci_range_dump(struct mtk_pci_range *range)
@@ -117,30 +117,33 @@
 {
 	struct mtk_pci_range *pci_space;
 	pcell_t ranges[FDT_RANGES_CELLS];
+	pcell_t addr_cells, size_cells, par_addr_cells;
 	pcell_t *rangesptr;
 	pcell_t cell0, cell1, cell2;
-	int tuples, i, rv, len;
+	int tuple_size, tuples, i, rv, len;
 
 	/*
 	 * Retrieve 'ranges' property.
 	 */
-	if (!OF_hasprop(node, "ranges")) {
-		printf("%s: %d\n", __FUNCTION__, 1);
+	if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
 		return (EINVAL);
-	}
+	if (addr_cells != 3 || size_cells != 2)
+		return (ERANGE);
+
+	par_addr_cells = fdt_parent_addr_cells(node);
+	if (par_addr_cells != 1)
+		return (ERANGE);
 
 	len = OF_getproplen(node, "ranges");
-	if (len > sizeof(ranges)) {
-		printf("%s: %d\n", __FUNCTION__, 2);
+	if (len > sizeof(ranges))
 		return (ENOMEM);
-	}
 
-	if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) {
-		printf("%s: %d\n", __FUNCTION__, 3);
+	if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
 		return (EINVAL);
-	}
 
-	tuples = len / (sizeof(pcell_t) * 3);
+	tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
+	    size_cells);
+	tuples = len / tuple_size;
 
 	/*
 	 * Initialize the ranges so that we don't have to worry about
@@ -159,18 +162,21 @@
 		cell2 = fdt_data_get((void *)rangesptr, 1);
 		rangesptr++;
 
-		if (cell0 == 2) {
+		if (cell0 & 0x02000000) {
 			pci_space = mem_space;
-		} else if (cell0 == 1) {
+		} else if (cell0 & 0x01000000) {
 			pci_space = io_space;
 		} else {
 			rv = ERANGE;
-			printf("%s: %d\n", __FUNCTION__, 4);
 			goto out;
 		}
 
-		pci_space->base = cell1;
-		pci_space->len = cell2;
+		pci_space->base = fdt_data_get((void *)rangesptr,
+		    par_addr_cells);
+		rangesptr += par_addr_cells;
+
+		pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
+		rangesptr += size_cells;
 	}
 
 	rv = 0;
@@ -199,6 +205,7 @@
 	{ "ralink,rt3883-pcie",		MTK_SOC_RT3883 },
 	{ "ralink,mt7620a-pcie",	MTK_SOC_MT7620A },
 	{ "ralink,mt7621-pcie",		MTK_SOC_MT7621 },
+	{ "mediatek,mt7621-pci",	MTK_SOC_MT7621 },
 	{ "ralink,mt7628-pcie",		MTK_SOC_MT7628 },
 	{ "ralink,mt7688-pcie",		MTK_SOC_MT7628 },
 	{ NULL,				MTK_SOC_UNKNOWN }
Index: head/sys/mips/mediatek/mtk_soc.c
===================================================================
--- head/sys/mips/mediatek/mtk_soc.c
+++ head/sys/mips/mediatek/mtk_soc.c
@@ -63,6 +63,7 @@
 	{ "ralink,mtk7620a-soc",	MTK_SOC_MT7620A },
 	{ "ralink,mtk7620n-soc",	MTK_SOC_MT7620N },
 	{ "mediatek,mtk7621-soc",	MTK_SOC_MT7621 },
+	{ "mediatek,mt7621-soc",	MTK_SOC_MT7621 },
 	{ "ralink,mtk7621-soc",		MTK_SOC_MT7621 },
 	{ "ralink,mtk7628an-soc",	MTK_SOC_MT7628 },
 	{ "mediatek,mt7628an-soc",	MTK_SOC_MT7628 },
Index: head/sys/mips/mediatek/mtk_usb_phy.c
===================================================================
--- head/sys/mips/mediatek/mtk_usb_phy.c
+++ head/sys/mips/mediatek/mtk_usb_phy.c
@@ -84,9 +84,10 @@
 static void mtk_usb_phy_mt7628_init(device_t);
 
 static struct ofw_compat_data compat_data[] = {
-	{ "ralink,mt7620a-usbphy",	MTK_SOC_MT7620A },
+	{ "ralink,mt7620-usbphy",	MTK_SOC_MT7620A },
 	{ "ralink,mt7628an-usbphy",	MTK_SOC_MT7628 },
-	{ "ralink,rt3xxx-usbphy",	MTK_SOC_RT3352 },
+	{ "ralink,rt3352-usbphy",	MTK_SOC_RT3352 },
+	{ "ralink,rt3050-usbphy",	MTK_SOC_RT3050 },
 	{ NULL,				MTK_SOC_UNKNOWN }
 };
 
Index: head/sys/mips/mediatek/mtk_xhci.c
===================================================================
--- head/sys/mips/mediatek/mtk_xhci.c
+++ head/sys/mips/mediatek/mtk_xhci.c
@@ -80,7 +80,7 @@
 	if (!ofw_bus_status_okay(self))
 		return (ENXIO);
 
-	if (!ofw_bus_is_compatible(self, "mtk,usb-xhci"))
+	if (!ofw_bus_is_compatible(self, "mediatek,mt8173-xhci"))
 		return (ENXIO);
 
 	device_set_desc(self, XHCI_HC_DEVSTR);