Index: sys/boot/fdt/dts/mips/mediatek/MT7620.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/MT7620.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/include/ "mediatek/mt7620a.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+//		reg = <0x0 0x4000000>;	/* 64MiB */
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = &uartlite;
+		stdout = &uartlite;
+	};
+
+	palmbus@10000000 {
+		spi@b00 {
+			flash {
+				compatible = "st,m25p";
+				spi-chipselect = <0>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* Define slices, which are board-specific */
+				/* For example:
+				slice@0 {
+					reg = <0x0 0x20000>;
+					label = "U-Boot";
+					read-only;
+				};
+				*/
+			};
+		};
+	};
+};
Index: sys/boot/fdt/dts/mips/mediatek/MT7621.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/MT7621.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+
+/include/ "mediatek/mt7621.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x10000000>;				/* 256MiB */
+//		reg = <0x0 0x1c000000>, <0x20000000 0x4000000>;	/* 512MiB */
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = &uartlite;
+		stdout = &uartlite;
+	};
+
+	palmbus@10000000 {
+		spi@b00 {
+			flash {
+				compatible = "st,m25p";
+				spi-chipselect = <0>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* Define slices, which are board-specific */
+				/* For example:
+				slice@0 {
+					reg = <0x0 0x20000>;
+					label = "U-Boot";
+					read-only;
+				};
+				*/
+			};
+		};
+	};
+};
Index: sys/boot/fdt/dts/mips/mediatek/MT7628.dts
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/MT7628.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/include/ "mediatek/mt7628an.dtsi"
+
+/ {
+	memory@0 {
+		device_type = "memory";
+//		reg = <0x0 0x8000000>;	/* 128MiB */
+	};
+
+	chosen {
+		bootargs = "-v";
+		stdin = &uartlite;
+		stdout = &uartlite;
+	};
+
+	palmbus@10000000 {
+		spi@b00 {
+			flash {
+				compatible = "st,m25p";
+				spi-chipselect = <0>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				/* Define slices, which are board-specific */
+				/* For example:
+				slice@0 {
+					reg = <0x0 0x20000>;
+					label = "U-Boot";
+					read-only;
+				};
+				*/
+			};
+		};
+	};
+};
Index: sys/boot/fdt/dts/mips/mediatek/mt7620a.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/mt7620a.dtsi
@@ -0,0 +1,166 @@
+/ {
+	compatible = "ralink,mtk7620a-soc";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+		};
+	};
+
+	ticker {
+		compatible = "mti,mips-ticker";
+	};
+
+	cpuintc: cpuintc@0 {
+		compatible = "mti,cpu-interrupt-controller";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	palmbus@10000000 {
+		compatible = "palmbus", "simple-bus";
+		reg = <0x10000000 0x200000>;
+		ranges = <0x0 0x10000000 0x1FFFFF>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sysc@0 {
+			compatible = "ralink,mt7620a-sysc";
+			reg = <0x0 0x100>;
+		};
+
+		intc: intc@200 {
+			compatible = "ralink,mt7620a-intc";
+			reg = <0x200 0x100>;
+			resets = <&rstctrl 19>;
+			reset-names = "intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
+		};
+
+		gpio0: gpio@600 {
+			compatible = "ralink,mt7620a-gpio","ralink,rt2880-gpio";
+			reg = <0x600 0x34>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			clocks = <&clkctrl 13>;
+			resets = <&rstctrl 13>;
+			mtk,num-pins = <24>;
+			mtk,register-gap;
+		};
+
+		gpio1: gpio@638 {
+			compatible = "ralink,mt7620a-gpio","ralink,rt2880-gpio";
+			reg = <0x638 0x24>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <16>;
+		};
+
+		gpio2: gpio@660 {
+			compatible = "ralink,mt7620a-gpio","ralink,rt2880-gpio";
+			reg = <0x660 0x24>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <32>;
+		};
+
+		gpio3: gpio@688 {
+			compatible = "ralink,mt7620a-gpio","ralink,rt2880-gpio";
+			reg = <0x688 0x24>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <32>;
+		};
+
+		spi@b00 {
+			compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
+			reg = <0xb00 0x40>;
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		uartlite: uartlite@c00 {
+			compatible = "ralink,mt7620a-uart","ralink,rt2880-uart";
+			reg = <0xc00 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test;
+			resets = <&rstctrl 19>;
+			reset-names = "uartl";
+			interrupt-parent = <&intc>;
+			interrupts = <12>;
+		};
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	clkctrl: clkctrl {
+		compatible = "ralink,mt7620a-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "ralink,mt7620a-pinctrl", "ralink,rt2880-pinctrl";
+	};
+
+	usbphy: usbphy {
+		compatible = "ralink,mt7628an-usbphy";
+		#phy-cells = <1>;
+		resets = <&rstctrl 22 &rstctrl 25>;
+		clocks = <&clkctrl 22 &clkctrl 25>;
+	};
+
+	ehci@101c0000 {
+		compatible = "ralink,rt3xxx-ehci";
+		reg = <0x101c0000 0x1000>;
+		phys = <&usbphy 1>;
+		interrupt-parent = <&intc>;
+		interrupts = <18>;
+	};
+
+	ohci@101c1000 {
+		compatible = "ralink,rt3xxx-ohci";
+		reg = <0x101c1000 0x1000>;
+		phys = <&usbphy 1>;
+		phy-names = "usb";
+		interrupt-parent = <&intc>;
+		interrupts = <18>;
+        };
+
+	ethernet@10100000 {
+		compatible = "ralink,mt7620a-eth";
+		reg = <0x10100000 10000>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <5>;
+		resets = <&rstctrl 21 &rstctrl 23>;
+		reset-names = "fe", "esw";
+	};
+
+};
Index: sys/boot/fdt/dts/mips/mediatek/mt7621.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/mt7621.dtsi
@@ -0,0 +1,130 @@
+/ {
+	compatible = "ralink,mtk7621-soc";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		cpu@0 {
+			compatible = "mips,mips1004Kc";
+		};
+	};
+
+	ticker {
+		compatible = "mti,mips-ticker";
+	};
+
+	cpuintc: cpuintc@0 {
+		compatible = "mti,cpu-interrupt-controller";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	intc: intc@0x1fbc0000 {
+		compatible = "mti,gic";
+		reg = <0x1fbc0000 0x10000>;
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+	};
+
+	palmbus@10000000 {
+		compatible = "palmbus", "simple-bus";
+		reg = <0x1e000000 0x200000>;
+		ranges = <0x0 0x1e000000 0x1FFFFF>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sysc@0 {
+			compatible = "mtk,mt7621-sysc";
+			reg = <0x0 0x100>;
+		};
+
+		gpio0: gpio@0 {
+			compatible = "mtk,mt7621-gpio";
+			reg = <0x600 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <32>;
+		};
+
+		gpio1: gpio@1 {
+			compatible = "mtk,mt7621-gpio";
+			reg = <0x600 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <17>;
+		};
+
+		spi@b00 {
+			compatible = "ralink,mt7621-spi";
+			reg = <0xb00 0x100>;
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+		};
+
+
+		uartlite: uartlite@c00 {
+			compatible = "mtk,ns16550a";
+			reg = <0xc00 0x100>;
+			reg-shift = <2>;
+			resets = <&rstctrl 12>;
+			interrupt-parent = <&intc>;
+			interrupts = <26>;
+		};
+
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,mt7621-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	clkctrl: clkctrl {
+		compatible = "ralink,mt7621-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "ralink,mt7621-pinctrl", "ralink,rt2880-pinctrl";
+	};
+
+	xhci {
+		compatible = "mtk,usb-xhci";
+		reg = <0x1e1c0000 0x20000>;
+		interrupts = <22>;
+		interrupt-parent = <&intc>;
+	};
+
+	ethernet@1e100000 {
+		compatible = "ralink,mt7621-eth";
+		reg = <0x1e100000 10000>;
+		interrupt-parent = <&intc>;
+		interrupts = <3>;
+		resets = <&rstctrl 21 &rstctrl 23>;
+	};
+
+	pcie@1e140000 {
+		compatible = "ralink,mt7621-pcie";
+		reg = <0x1e140000 0x10000>;
+		ranges = <1 0x1e160000 0x00010000
+			  2 0x60000000 0x10000000>;
+		interrupt-parent = <&intc>;
+		interrupts = <4 24 25>;
+		resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
+		clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
+	};
+};
Index: sys/boot/fdt/dts/mips/mediatek/mt7628an.dtsi
===================================================================
--- /dev/null
+++ sys/boot/fdt/dts/mips/mediatek/mt7628an.dtsi
@@ -0,0 +1,149 @@
+/ {
+	compatible = "ralink,mtk7628an-soc";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+		};
+	};
+
+	ticker {
+		compatible = "mti,mips-ticker";
+	};
+
+	cpuintc: cpuintc@0 {
+		compatible = "mti,cpu-interrupt-controller";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	palmbus@10000000 {
+		compatible = "palmbus", "simple-bus";
+		reg = <0x10000000 0x200000>;
+		ranges = <0x0 0x10000000 0x1FFFFF>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sysc@0 {
+			compatible = "ralink,mt7620a-sysc";
+			reg = <0x0 0x100>;
+		};
+
+		intc: intc@200 {
+			compatible = "ralink,mt7628an-intc";
+			reg = <0x200 0x100>;
+			resets = <&rstctrl 9>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
+			ralink,intc-registers = <0x9c 0xa0
+						 0x6c 0xa4
+						 0x80 0x78>;
+		};
+
+		gpio0: gpio@0 {
+			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
+			reg = <0x600 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <32>;
+		};
+
+		gpio1: gpio@1 {
+			compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
+			reg = <0x600 0x100>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+			mtk,num-pins = <15>;
+		};
+
+		spi@b00 {
+			compatible = "ralink,mt7621-spi";
+			reg = <0xb00 0x100>;
+			resets = <&rstctrl 18>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		uartlite: uartlite@e00 {
+			compatible = "mtk,ns16550a";
+			reg = <0xe00 0x100>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			no-loopback-test;
+			resets = <&rstctrl 12>;
+			interrupt-parent = <&intc>;
+			interrupts = <22>;
+		};
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	clkctrl: clkctrl {
+		compatible = "ralink,mt7620a-clock", "ralink,rt2880-clock";
+		#clock-cells = <1>;
+	};
+
+	pinctrl: pinctrl {
+		compatible = "ralink,mt7628a-pinctrl", "ralink,rt2880-pinctrl";
+	};
+
+	usbphy: usbphy {
+		compatible = "ralink,mt7628an-usbphy";
+		#phy-cells = <1>;
+		reg = <0x10120000 0x1000>;
+		resets = <&rstctrl 22 &rstctrl 25>;
+		clocks = <&clkctrl 22 &clkctrl 25>;
+	};
+
+	ehci@101c0000 {
+		compatible = "ralink,rt3xxx-ehci";
+		reg = <0x101c0000 0x1000>;
+		phys = <&usbphy 1>;
+		interrupt-parent = <&intc>;
+		interrupts = <18>;
+	};
+
+	ohci@101c1000 {
+		compatible = "ralink,rt3xxx-ohci";
+		reg = <0x101c1000 0x1000>;
+		phys = <&usbphy 1>;
+		interrupt-parent = <&intc>;
+		interrupts = <18>;
+        };
+
+	ethernet@10100000 {
+		compatible = "ralink,rt5350-eth";
+		reg = <0x10100000 10000>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <5>;
+		resets = <&rstctrl 21 &rstctrl 23>;
+	};
+
+	pcie@10140000 {
+		compatible = "ralink,mt7628-pcie";
+		reg = <0x10140000 0x10000>;
+		ranges = <1 0x10160000 0x00010000
+			  2 0x20000000 0x10000000>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <4>;
+		resets = <&rstctrl 26>, <&rstctrl 27>;
+		clocks = <&clkctrl 26>, <&clkctrl 27>;
+	};
+
+};