Index: sys/arm/allwinner/aw_nmi.c =================================================================== --- /dev/null +++ sys/arm/allwinner/aw_nmi.c @@ -0,0 +1,329 @@ +/*- + * Copyright (c) 2016 Emmanuel Vadot + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#ifdef ARM_INTRNG + +#include "pic_if.h" + +#define NMI_IRQ_CTRL_REG 0x0 +#define NMI_IRQ_LOW_LEVEL 0x0 +#define NMI_IRQ_LOW_EDGE 0x1 +#define NMI_IRQ_HIGH_LEVEL 0x2 +#define NMI_IRQ_HIGH_EDGE 0x3 +#define NMI_IRQ_PENDING_REG 0x4 +#define NMI_IRQ_ACK (1U << 0) +#define A20_NMI_IRQ_ENABLE_REG 0x8 +#define A31_NMI_IRQ_ENABLE_REG 0x34 +#define NMI_IRQ_ENABLE (1U << 0) + +#define SC_NMI_READ(_sc, _reg) bus_read_4(_sc->res[0], _reg) +#define SC_NMI_WRITE(_sc, _reg, _val) bus_write_4(_sc->res[0], _reg, _val) + +static struct resource_spec aw_nmi_res_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0, 0 } +}; + +struct aw_nmi_softc { + device_t dev; + struct resource * res[2]; + void * intrcookie; + struct intr_irqsrc * irq; + uint8_t enable_reg; +}; + +#define A20_NMI 1 +#define A31_NMI 2 + +static struct ofw_compat_data compat_data[] = { + {"allwinner,sun7i-a20-sc-nmi", A20_NMI}, + {"allwinner,sun6i-a31-sc-nmi", A31_NMI}, + + {NULL, 0}, +}; + +static int +aw_nmi_intr(void *arg) +{ + struct aw_nmi_softc *sc; + + sc = arg; + + if (sc->irq) + intr_irq_dispatch(sc->irq, curthread->td_intr_frame); + else + device_printf(sc->dev, "Spurious interrupt\n"); + SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); + + return (FILTER_HANDLED); +} + +static void +aw_nmi_enable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct aw_nmi_softc *sc; + + sc = device_get_softc(dev); + + SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE); +} + +static void +aw_nmi_disable_intr(device_t dev, struct intr_irqsrc *isrc) +{ + struct aw_nmi_softc *sc; + + sc = device_get_softc(dev); + + SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE); +} + +static void +aw_nmi_enable_source(device_t dev, struct intr_irqsrc *isrc) +{ + struct aw_nmi_softc *sc; + + sc = device_get_softc(dev); + + SC_NMI_WRITE(sc, sc->enable_reg, NMI_IRQ_ENABLE); +} + +static void +aw_nmi_disable_source(device_t dev, struct intr_irqsrc *isrc) +{ + struct aw_nmi_softc *sc; + + sc = device_get_softc(dev); + + SC_NMI_WRITE(sc, sc->enable_reg, ~NMI_IRQ_ENABLE); +} + +static int +aw_nmi_register(device_t dev, struct intr_irqsrc *isrc, boolean_t *is_percpu) +{ + struct aw_nmi_softc *sc; + u_int irq, pol, pol_value; + + sc = device_get_softc(dev); + + if (sc->irq) { + device_printf(dev, "IRQ 0 already registered\n"); + return (EINVAL); + } + + if (isrc->isrc_ncells != 2) { + device_printf(dev, "Invalid #interrupt-cells\n"); + return (EINVAL); + } + + irq = isrc->isrc_cells[0]; + if (irq != 0) { + device_printf(dev, "Controller only support irq 0\n"); + return (EINVAL); + } + + pol = isrc->isrc_cells[1]; + + switch (pol) { + case IRQ_TYPE_EDGE_RISING: + isrc->isrc_trig = INTR_TRIGGER_EDGE; + isrc->isrc_pol = INTR_POLARITY_HIGH; + pol_value = NMI_IRQ_HIGH_EDGE; + break; + case IRQ_TYPE_EDGE_FALLING: + isrc->isrc_trig = INTR_TRIGGER_EDGE; + isrc->isrc_pol = INTR_POLARITY_LOW; + pol_value = NMI_IRQ_LOW_EDGE; + break; + case IRQ_TYPE_LEVEL_HIGH: + isrc->isrc_trig = INTR_TRIGGER_LEVEL; + isrc->isrc_pol = INTR_POLARITY_HIGH; + pol_value = NMI_IRQ_HIGH_LEVEL; + break; + case IRQ_TYPE_LEVEL_LOW: + isrc->isrc_trig = INTR_TRIGGER_LEVEL; + isrc->isrc_pol = INTR_POLARITY_LOW; + pol_value = NMI_IRQ_LOW_LEVEL; + break; + default: + device_printf(sc->dev, "unsupported polarity 0x%2x\n", pol); + return (ENOTSUP); + } + isrc->isrc_nspc_type = INTR_IRQ_NSPC_PLAIN; + isrc->isrc_nspc_num = irq; + + sc->irq = isrc; + + SC_NMI_WRITE(sc, NMI_IRQ_CTRL_REG, pol_value); + + intr_irq_set_name(isrc, "%s,%u", device_get_nameunit(sc->dev), irq); + + return (0); +} + +static int +aw_nmi_unregister(device_t dev, struct intr_irqsrc *isrc) +{ + struct aw_nmi_softc *sc = device_get_softc(dev); + + sc->irq = NULL; + intr_irq_set_name(isrc, ""); + + return (0); +} + +static void +aw_nmi_pre_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + + aw_nmi_disable_source(dev, isrc); +} + +static void +aw_nmi_post_ithread(device_t dev, struct intr_irqsrc *isrc) +{ + + arm_irq_memory_barrier(0); + aw_nmi_enable_source(dev, isrc); +} + +static void +aw_nmi_post_filter(device_t dev, struct intr_irqsrc *isrc) +{ +} + +static int +aw_nmi_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + device_set_desc(dev, "Allwinner NMI Controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_nmi_attach(device_t dev) +{ + struct aw_nmi_softc *sc; + phandle_t xref; + + sc = device_get_softc(dev); + sc->dev = dev; + + if (bus_alloc_resources(dev, aw_nmi_res_spec, sc->res) != 0) { + device_printf(dev, "can't allocate device resources\n"); + return (ENXIO); + } + if ((bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC, + aw_nmi_intr, NULL, sc, &sc->intrcookie))) { + device_printf(dev, "unable to register interrupt handler\n"); + bus_release_resources(dev, aw_nmi_res_spec, sc->res); + return (ENXIO); + } + + switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { + case A20_NMI: + sc->enable_reg = A20_NMI_IRQ_ENABLE_REG; + break; + case A31_NMI: + sc->enable_reg = A31_NMI_IRQ_ENABLE_REG; + break; + } + + /* Disable and clear interrupts */ + SC_NMI_WRITE(sc, sc->enable_reg, ~NMI_IRQ_ENABLE); + SC_NMI_WRITE(sc, NMI_IRQ_PENDING_REG, NMI_IRQ_ACK); + + xref = OF_xref_from_node(ofw_bus_get_node(dev)); + if (intr_pic_register(dev, (intptr_t)xref) != 0) { + device_printf(dev, "could not register pic\n"); + goto error; + } + return (0); + +error: + bus_teardown_intr(dev, sc->res[1], sc->intrcookie); + bus_release_resources(dev, aw_nmi_res_spec, sc->res); + return (ENXIO); +} + +static device_method_t aw_nmi_methods[] = { + DEVMETHOD(device_probe, aw_nmi_probe), + DEVMETHOD(device_attach, aw_nmi_attach), + +#ifdef ARM_INTRNG + /* Interrupt controller interface */ + DEVMETHOD(pic_disable_source, aw_nmi_disable_source), + DEVMETHOD(pic_enable_intr, aw_nmi_enable_intr), + DEVMETHOD(pic_enable_source, aw_nmi_enable_source), + DEVMETHOD(pic_post_filter, aw_nmi_post_filter), + DEVMETHOD(pic_post_ithread, aw_nmi_post_ithread), + DEVMETHOD(pic_pre_ithread, aw_nmi_pre_ithread), + DEVMETHOD(pic_register, aw_nmi_register), + DEVMETHOD(pic_unregister, aw_nmi_unregister), +#endif + + {0, 0}, +}; + +static driver_t aw_nmi_driver = { + "aw_nmi", + aw_nmi_methods, + sizeof(struct aw_nmi_softc), +}; + +static devclass_t aw_nmi_devclass; + +EARLY_DRIVER_MODULE(aw_nmi, simplebus, aw_nmi_driver, + aw_nmi_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); + +#endif /* ARM_INTRNG */ Index: sys/arm/allwinner/files.allwinner =================================================================== --- sys/arm/allwinner/files.allwinner +++ sys/arm/allwinner/files.allwinner @@ -11,6 +11,7 @@ arm/allwinner/a10_gpio.c optional gpio arm/allwinner/a10_mmc.c optional mmc arm/allwinner/a10_sramc.c standard +arm/allwinner/aw_nmi.c standard arm/allwinner/aw_rtc.c standard arm/allwinner/aw_wdog.c standard arm/allwinner/a20/a20_cpu_cfg.c standard