Index: sys/dev/bhnd/bhndb/bhndb.h
===================================================================
--- sys/dev/bhnd/bhndb/bhndb.h
+++ sys/dev/bhnd/bhndb/bhndb.h
@@ -80,8 +80,8 @@
 		int		rid;		/**< resource id */
 	} res;
 
-
-	union {
+	/** changed from unnamed to named to meet C99 */
+	union specific {
 		/** Core-specific register window (BHNDB_REGWIN_T_CORE). */
 		struct {
 			bhnd_devclass_t	class;		/**< mapped core's class */
@@ -98,7 +98,7 @@
 		struct {
 			bus_size_t	cfg_offset;	/**< window address config offset. */
 		} dyn;
-        };
+    } win_spec;
 };
 
 #define	BHNDB_REGWIN_TABLE_END	{ BHNDB_REGWIN_T_INVALID, 0, 0, { 0, 0 } }
@@ -170,4 +170,4 @@
 #define	BHNDB_HW_PRIORITY_TABLE_END	{ {}, BHNDB_PRIORITY_NONE, NULL, 0 }
 
 
-#endif /* _BHND_BHNDB_H_ */
\ No newline at end of file
+#endif /* _BHND_BHNDB_H_ */
Index: sys/dev/bhnd/bhndb/bhndb.c
===================================================================
--- sys/dev/bhnd/bhndb/bhndb.c
+++ sys/dev/bhnd/bhndb/bhndb.c
@@ -257,8 +257,8 @@
 			
 			/* Fetch the base address of the mapped port. */
 			error = bhnd_get_region_addr(child, 
-			    regw->core.port_type, regw->core.port, 
-			    regw->core.region, &addr, &size);
+			    regw->win_spec.core.port_type, regw->win_spec.core.port,
+			    regw->win_spec.core.region, &addr, &size);
 			if (error)
 			    return (error);
 
Index: sys/dev/bhnd/bhndb/bhndb_pci.c
===================================================================
--- sys/dev/bhnd/bhndb/bhndb_pci.c
+++ sys/dev/bhnd/bhndb/bhndb_pci.c
@@ -775,7 +775,7 @@
 		if ((error = bhndb_pci_fast_setregwin(sc, rw, addr)))
 			return (error);
 
-		if (pci_read_config(parent, rw->dyn.cfg_offset, 4) == addr)
+		if (pci_read_config(parent, rw->win_spec.dyn.cfg_offset, 4) == addr)
 			return (0);
 
 		DELAY(10);
@@ -805,7 +805,7 @@
 		if (addr % rw->win_size != 0)
 			return (EINVAL);
 
-		pci_write_config(parent, rw->dyn.cfg_offset, addr, 4);
+		pci_write_config(parent, rw->win_spec.dyn.cfg_offset, addr, 4);
 		break;
 	default:
 		return (ENODEV);
Index: sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
===================================================================
--- sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
+++ sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c
@@ -93,7 +93,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		BHNDB_REGWIN_TABLE_END
@@ -122,7 +122,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 
@@ -131,7 +131,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_CC,
 				.unit	= 0,
 				.port	= 0,
@@ -327,7 +327,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V0_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -344,7 +344,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
 			.win_size	= BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_PCI,
 				.unit	= 0,
 				.port	= 0,
@@ -375,7 +375,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -392,7 +392,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_PCI,
 				.unit	= 0,
 				.port	= 0,
@@ -407,7 +407,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_CC,
 				.unit	= 0,
 				.port	= 0,
@@ -439,7 +439,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -456,7 +456,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_PCIE,
 				.unit	= 0,
 				.port	= 0,
@@ -471,7 +471,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 			.win_size	= BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_CC,
 				.unit	= 0,
 				.port	= 0,
@@ -503,7 +503,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V2_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -512,7 +512,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
 			.win_size	= BHNDB_PCI_V2_BAR0_WIN1_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -521,7 +521,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
 			.win_size	= BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_PCIE,
 				.unit	= 0,
 				.port	= 0,
@@ -536,7 +536,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
 			.win_size	= BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_CC,
 				.unit	= 0,
 				.port	= 0,
@@ -568,7 +568,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
 			.win_size	= BHNDB_PCI_V3_BAR0_WIN0_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -577,7 +577,7 @@
 			.win_type	= BHNDB_REGWIN_T_DYN,
 			.win_offset	= BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
 			.win_size	= BHNDB_PCI_V3_BAR0_WIN1_SIZE,
-			.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
+			.win_spec.dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
 			.res		= { SYS_RES_MEMORY, PCIR_BAR(0) }
 		},
 		
@@ -586,7 +586,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
 			.win_size	= BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_PCIE,
 				.unit	= 0,
 				.port	= 0,
@@ -601,7 +601,7 @@
 			.win_type	= BHNDB_REGWIN_T_CORE,
 			.win_offset	= BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
 			.win_size	= BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
-			.core = {
+			.win_spec.core = {
 				.class	= BHND_DEVCLASS_CC,
 				.unit	= 0,
 				.port	= 0,
Index: sys/dev/bhnd/bhndb/bhndb_subr.c
===================================================================
--- sys/dev/bhnd/bhndb/bhndb_subr.c
+++ sys/dev/bhnd/bhndb/bhndb_subr.c
@@ -777,19 +777,19 @@
 		if (rw->win_type != BHNDB_REGWIN_T_CORE)
 			continue;
 
-		if (rw->core.class != class)
+		if (rw->win_spec.core.class != class)
 			continue;
-		
-		if (unit != -1 && rw->core.unit != unit)
+
+		if (unit != -1 && rw->win_spec.core.unit != unit)
 			continue;
 
-		if (rw->core.port_type != port_type)
+		if (rw->win_spec.core.port_type != port_type)
 			continue;
 
-		if (rw->core.port != port)
+		if (rw->win_spec.core.port != port)
 			continue;
-		
-		if (rw->core.region != region)
+
+		if (rw->win_spec.core.region != region)
 			continue;
 
 		return (rw);
@@ -848,16 +848,16 @@
 		return (false);
 
 	/* Device class must match */
-	if (bhnd_get_class(dev) != regw->core.class)
+	if (bhnd_get_class(dev) != regw->win_spec.core.class)
 		return (false);
 
 	/* Device unit must match */
-	if (bhnd_get_core_unit(dev) != regw->core.unit)
+	if (bhnd_get_core_unit(dev) != regw->win_spec.core.unit)
 		return (false);
 	
 	/* The regwin port/region must be defined. */
-	if (!bhnd_is_region_valid(dev, regw->core.port_type, regw->core.port,
-	    regw->core.region))
+	if (!bhnd_is_region_valid(dev, regw->win_spec.core.port_type, regw->win_spec.core.port,
+	    regw->win_spec.core.region))
 	{
 		return (false);
 	}