Index: sys/powerpc/aim/mmu_oea.c =================================================================== --- sys/powerpc/aim/mmu_oea.c +++ sys/powerpc/aim/mmu_oea.c @@ -384,6 +384,8 @@ switch (ma) { case VM_MEMATTR_UNCACHEABLE: return (PTE_I | PTE_G); + case VM_MEMATTR_CACHEABLE: + return (PTE_M); case VM_MEMATTR_WRITE_COMBINING: case VM_MEMATTR_WRITE_BACK: case VM_MEMATTR_PREFETCHABLE: Index: sys/powerpc/aim/mmu_oea64.c =================================================================== --- sys/powerpc/aim/mmu_oea64.c +++ sys/powerpc/aim/mmu_oea64.c @@ -434,6 +434,8 @@ switch (ma) { case VM_MEMATTR_UNCACHEABLE: return (LPTE_I | LPTE_G); + case VM_MEMATTR_CACHEABLE: + return (LPTE_M); case VM_MEMATTR_WRITE_COMBINING: case VM_MEMATTR_WRITE_BACK: case VM_MEMATTR_PREFETCHABLE: Index: sys/powerpc/booke/pmap.c =================================================================== --- sys/powerpc/booke/pmap.c +++ sys/powerpc/booke/pmap.c @@ -419,6 +419,8 @@ return (PTE_I); case VM_MEMATTR_WRITE_THROUGH: return (PTE_W | PTE_M); + case VM_MEMATTR_CACHEABLE: + return _TLB_ENTRY_MEM; } } Index: sys/powerpc/powerpc/nexus.c =================================================================== --- sys/powerpc/powerpc/nexus.c +++ sys/powerpc/powerpc/nexus.c @@ -189,15 +189,19 @@ { if (type == SYS_RES_MEMORY) { - vm_offset_t start; + vm_paddr_t start; void *p; + vm_memattr_t ma; - start = (vm_offset_t) rman_get_start(r); + start = (vm_paddr_t) rman_get_start(r); if (bootverbose) - printf("nexus mapdev: start %zx, len %ld\n", start, - rman_get_size(r)); + printf("nexus mapdev: start %jx, len %ld\n", + (uintmax_t)start, rman_get_size(r)); - p = pmap_mapdev(start, (vm_size_t) rman_get_size(r)); + ma = VM_MEMATTR_DEFAULT; + if (rman_get_flags(r) & RF_CACHEABLE) + ma = VM_MEMATTR_CACHEABLE; + p = pmap_mapdev_attr(start, (vm_size_t) rman_get_size(r), ma); if (p == NULL) return (ENOMEM); rman_set_virtual(r, p); Index: sys/sys/rman.h =================================================================== --- sys/sys/rman.h +++ sys/sys/rman.h @@ -47,6 +47,7 @@ #define RF_FIRSTSHARE 0x0020 /* first in sharing list */ #define RF_PREFETCHABLE 0x0040 /* resource is prefetchable */ #define RF_OPTIONAL 0x0080 /* for bus_alloc_resources() */ +#define RF_CACHEABLE 0x0100 /* memory resource is cacheable */ #define RF_ALIGNMENT_SHIFT 10 /* alignment size bit starts bit 10 */ #define RF_ALIGNMENT_MASK (0x003F << RF_ALIGNMENT_SHIFT)