Index: head/sys/arm64/arm64/gic_v3.c
===================================================================
--- head/sys/arm64/arm64/gic_v3.c
+++ head/sys/arm64/arm64/gic_v3.c
@@ -565,7 +565,7 @@
 	/*
 	 * 4. Route all interrupts to boot CPU.
 	 */
-	aff = CPU_AFFINITY(PCPU_GET(cpuid));
+	aff = CPU_AFFINITY(0);
 	for (i = GIC_FIRST_SPI; i < sc->gic_nirqs; i++)
 		gic_d_write(sc, 4, GICD_IROUTER(i), aff);
 
Index: head/sys/arm64/arm64/gic_v3_its.c
===================================================================
--- head/sys/arm64/arm64/gic_v3_its.c
+++ head/sys/arm64/arm64/gic_v3_its.c
@@ -1430,10 +1430,10 @@
 	}
 
 	/*
-	 * XXX ARM64TODO: Currently all interrupts are going
-	 * to be bound to the CPU that performs the configuration.
+	 * Initially all interrupts go to CPU0 but can be moved
+	 * to another CPU by bus_bind_intr() or interrupts shuffling.
 	 */
-	cpuid = PCPU_GET(cpuid);
+	cpuid = 0;
 	newdev->col = sc->its_cols[cpuid];
 
 	TAILQ_INSERT_TAIL(&sc->its_dev_list, newdev, entry);