Index: sys/powerpc/booke/pmap.c
===================================================================
--- sys/powerpc/booke/pmap.c
+++ sys/powerpc/booke/pmap.c
@@ -412,13 +412,13 @@
 	if (ma != VM_MEMATTR_DEFAULT) {
 		switch (ma) {
 		case VM_MEMATTR_UNCACHEABLE:
-			return (PTE_I | PTE_G);
+			return (MAS2_I | MAS2_G);
 		case VM_MEMATTR_WRITE_COMBINING:
 		case VM_MEMATTR_WRITE_BACK:
 		case VM_MEMATTR_PREFETCHABLE:
-			return (PTE_I);
+			return (MAS2_I);
 		case VM_MEMATTR_WRITE_THROUGH:
-			return (PTE_W | PTE_M);
+			return (MAS2_W | MAS2_M);
 		}
 	}
 
@@ -985,7 +985,7 @@
 	}
 	pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
 	pte->rpn = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
-	pte->flags |= (PTE_VALID | flags);
+	pte->flags |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
 
 	tlb_miss_unlock();
 	mtx_unlock_spin(&tlbivax_mutex);
@@ -1043,7 +1043,7 @@
 		pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
 		pte->rpn = kernload + (va - kernstart);
 		pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
-		    PTE_VALID;
+		    PTE_VALID | PTE_PS_4KB;
 	}
 }
 
@@ -1525,7 +1525,8 @@
 	    (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
 
 	flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
-	flags |= tlb_calc_wimg(pa, ma);
+	flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
+	flags |= PTE_PS_4KB;
 
 	pte = pte_find(mmu, kernel_pmap, va);
 
@@ -1542,15 +1543,15 @@
 
 	pte->rpn = PTE_RPN_FROM_PA(pa);
 	pte->flags = flags;
+	flags = pte->flags;
 
 	//debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
 	//		"pa=0x%08x rpn=0x%08x flags=0x%08x\n",
 	//		pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
 
 	/* Flush the real memory from the instruction cache. */
-	if ((flags & (PTE_I | PTE_G)) == 0) {
+	if ((flags & (PTE_I | PTE_G)) == 0)
 		__syncicache((void *)va, PAGE_SIZE);
-	}
 
 	tlb_miss_unlock();
 	mtx_unlock_spin(&tlbivax_mutex);
@@ -2340,7 +2341,8 @@
 	paddr = VM_PAGE_TO_PHYS(m);
 
 	flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
-	flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m));
+	flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
+	flags |= PTE_PS_4KB;
 
 	critical_enter();
 	qaddr = PCPU_GET(qmap_addr);
Index: sys/powerpc/booke/trap_subr.S
===================================================================
--- sys/powerpc/booke/trap_subr.S
+++ sys/powerpc/booke/trap_subr.S
@@ -686,7 +686,7 @@
 	 * This load may cause a Data TLB miss for non-kernel pmap!
 	 */
 	lwz	%r21, PTE_FLAGS(%r25)
-	andis.	%r21, %r21, PTE_VALID@h
+	andi.	%r21, %r21, PTE_VALID@l
 	bne	2f
 1:
 	li	%r25, 0
@@ -721,20 +721,21 @@
 
 	andi.	%r22, %r21, (PTE_SW | PTE_UW)@l	/* check if writable */
 	beq	2f
-	oris	%r21, %r21, PTE_MODIFIED@h	/* set modified bit */
+	ori	%r21, %r21, PTE_MODIFIED@l	/* set modified bit */
 2:
 	stwcx.	%r21, %r23, %r25		/* write it back */
 	bne-	1b
 
 	/* Update MAS2. */
-	rlwimi	%r27, %r21, 0, 27, 30		/* insert WIMG bits from pte */
+	rlwimi	%r27, %r21, 13, 27, 30		/* insert WIMG bits from pte */
 
 	/* Setup MAS3 value in r23. */
 	lwz	%r23, PTE_RPN(%r25)		/* get pte->rpn */
-	rlwinm	%r22, %r23, 12, 0, 20		/* extract MAS3 portion of RPN */
+	rlwinm	%r22, %r23, 20, 0, 11		/* extract MAS3 portion of RPN */
 
-	rlwimi	%r22, %r21, 24, 26, 31		/* insert protection bits from pte */
-	rlwinm	%r23, %r23, 12, 28, 31		/* MAS7 portion of RPN */
+	rlwimi	%r22, %r21, 30, 26, 31		/* insert protection bits from pte */
+	rlwimi	%r22, %r21, 20, 12, 19		/* insert lower 8 RPN bits to MAS3 */
+	rlwinm	%r23, %r23, 20, 24, 31		/* MAS7 portion of RPN */
 
 	/* Load MAS registers. */
 	mtspr	SPR_MAS0, %r29
Index: sys/powerpc/include/pte.h
===================================================================
--- sys/powerpc/include/pte.h
+++ sys/powerpc/include/pte.h
@@ -213,8 +213,8 @@
  */
 #ifndef	LOCORE
 struct pte {
-	vm_offset_t rpn;
-	uint32_t flags;
+	uint64_t rpn : 40;
+	uint64_t flags : 24;
 };
 typedef struct pte pte_t;
 #endif
@@ -225,13 +225,14 @@
 #if defined(BOOKE_E500)
 
 /* PTE bits assigned to MAS2, MAS3 flags */
-#define PTE_W		MAS2_W
-#define PTE_I		MAS2_I
-#define PTE_M		MAS2_M
-#define PTE_G		MAS2_G
+#define	PTE_MAS2_SHIFT	19
+#define PTE_W		(MAS2_W << PTE_MAS2_SHIFT)
+#define PTE_I		(MAS2_I << PTE_MAS2_SHIFT)
+#define PTE_M		(MAS2_M << PTE_MAS2_SHIFT)
+#define PTE_G		(MAS2_G << PTE_MAS2_SHIFT)
 #define PTE_MAS2_MASK	(MAS2_G | MAS2_M | MAS2_I | MAS2_W)
 
-#define PTE_MAS3_SHIFT	8
+#define PTE_MAS3_SHIFT	2
 #define PTE_UX		(MAS3_UX << PTE_MAS3_SHIFT)
 #define PTE_SX		(MAS3_SX << PTE_MAS3_SHIFT)
 #define PTE_UW		(MAS3_UW << PTE_MAS3_SHIFT)
@@ -241,6 +242,9 @@
 #define PTE_MAS3_MASK	((MAS3_UX | MAS3_SX | MAS3_UW	\
 			| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
 
+#define	PTE_PS_SHIFT	8
+#define	PTE_PS_4KB	(2 << PTE_PS_SHIFT)
+
 #elif defined(BOOKE_PPC4XX)
 
 #define PTE_WL1		TLB_WL1
@@ -262,11 +266,11 @@
 #endif
 
 /* Other PTE flags */
-#define PTE_VALID	0x80000000	/* Valid */
-#define PTE_MODIFIED	0x40000000	/* Modified */
-#define PTE_WIRED	0x20000000	/* Wired */
-#define PTE_MANAGED	0x10000000	/* Managed */
-#define PTE_REFERENCED	0x04000000	/* Referenced */
+#define PTE_VALID	0x00000001	/* Valid */
+#define PTE_MODIFIED	0x00001000	/* Modified */
+#define PTE_WIRED	0x00002000	/* Wired */
+#define PTE_MANAGED	0x00000002	/* Managed */
+#define PTE_REFERENCED	0x00040000	/* Referenced */
 
 /* Macro argument must of pte_t type. */
 #define PTE_PA_SHIFT		12
Index: sys/powerpc/powerpc/genassym.c
===================================================================
--- sys/powerpc/powerpc/genassym.c
+++ sys/powerpc/powerpc/genassym.c
@@ -119,8 +119,12 @@
 #endif
 #elif defined(BOOKE)
 ASSYM(PM_PDIR, offsetof(struct pmap, pm_pdir));
-ASSYM(PTE_RPN, offsetof(struct pte, rpn));
-ASSYM(PTE_FLAGS, offsetof(struct pte, flags));
+/*
+ * With pte_t being a bitfield struct, these fields cannot be addressed via
+ * offsetof().
+ */
+ASSYM(PTE_RPN, 0);
+ASSYM(PTE_FLAGS, sizeof(uint32_t));
 #if defined(BOOKE_E500)
 ASSYM(TLB0_ENTRY_SIZE, sizeof(struct tlb_entry));
 #endif