diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -374,7 +374,7 @@
 	msr	sctlr_el1, x2
 
 	/* Check for VHE */
-	CHECK_CPU_FEAT(x2, ID_AA64MMFR1, VH, .Lno_vhe)
+	CHECK_CPU_FEAT(x2, ID_AA64MMFR1, VH, IMPL, .Lno_vhe)
 
 	/*
 	 * The kernel will be running in EL2, route exceptions here rather
@@ -413,7 +413,7 @@
 	 * Configure the Extended Hypervisor register. This is only valid if
 	 * FEAT_HCX is enabled.
 	 */
-	CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, 2f)
+	CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, IMPL, 2f)
 	/* Extended Hypervisor Configuration */
 	mov x2, xzr
 	msr HCRX_EL2_REG, x2
@@ -430,7 +430,7 @@
 	msr	vttbr_el2, xzr
 
 	/* Check the CPU supports GIC, and configure the CPU interface */
-	CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, 3f)
+	CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, CPUIF_EN, 3f)
 
 	mrs	x2, icc_sre_el2
 	orr	x2, x2, #ICC_SRE_EL2_EN	/* Enable access from insecure EL1 */
@@ -1029,7 +1029,7 @@
 	 * HW management of dirty state is set in C code as it may
 	 * need to be disabled because of CPU errata.
 	 */
-	CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, 1f)
+	CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, AF, 1f)
 	orr	x2, x2, #(TCR_HA)
 1:
 
diff --git a/sys/arm64/include/asm.h b/sys/arm64/include/asm.h
--- a/sys/arm64/include/asm.h
+++ b/sys/arm64/include/asm.h
@@ -77,10 +77,11 @@
  * to the given label. The tmp register should be a register able to hold the
  * temporary data.
  */
-#define CHECK_CPU_FEAT(tmp, feat_reg, feat, label)	\
-	mrs tmp, ##feat_reg##_el1;	\
+#define CHECK_CPU_FEAT(tmp, feat_reg, feat, min_val, label)	\
+	mrs tmp, ##feat_reg##_el1;				\
 	ubfx tmp, tmp, ##feat_reg##_##feat##_SHIFT, ##feat_reg##_##feat##_WIDTH; \
-	cbz tmp, label
+	cmp tmp, #(##feat_reg##_##feat##_##min_val## >> ##feat_reg##_##feat##_SHIFT); \
+	b.lt label
 
 /*
  * Sets the trap fault handler. The exception handler will return to the