Index: sys/arm/conf/ARMADA38X =================================================================== --- sys/arm/conf/ARMADA38X +++ sys/arm/conf/ARMADA38X @@ -70,6 +70,7 @@ # USB device usb device ehci +device xhci device umass device scbus device pass Index: sys/arm/mv/files.mv =================================================================== --- sys/arm/mv/files.mv +++ sys/arm/mv/files.mv @@ -27,5 +27,6 @@ dev/mvs/mvs_soc.c optional mvs dev/uart/uart_dev_ns8250.c optional uart dev/usb/controller/ehci_mv.c optional ehci +dev/usb/controller/xhci_mv.c optional xhci kern/kern_clocksource.c standard Index: sys/arm/mv/mv_common.c =================================================================== --- sys/arm/mv/mv_common.c +++ sys/arm/mv/mv_common.c @@ -79,6 +79,7 @@ static int decode_win_cpu_valid(void); #endif static int decode_win_usb_valid(void); +static int decode_win_usb3_valid(void); static int decode_win_eth_valid(void); static int decode_win_pcie_valid(void); static int decode_win_sata_valid(void); @@ -93,6 +94,7 @@ static int decode_win_sdram_fixup(void); #endif static void decode_win_usb_setup(u_long); +static void decode_win_usb3_setup(u_long); static void decode_win_eth_setup(u_long); static void decode_win_sata_setup(u_long); @@ -100,6 +102,7 @@ static void decode_win_xor_setup(u_long); static void decode_win_usb_dump(u_long); +static void decode_win_usb3_dump(u_long); static void decode_win_eth_dump(u_long base); static void decode_win_idma_dump(u_long base); static void decode_win_xor_dump(u_long base); @@ -134,6 +137,7 @@ static struct soc_node_spec soc_nodes[] = { { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, + { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, { "mrvl,sata", &decode_win_sata_setup, NULL }, { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, @@ -559,7 +563,7 @@ if (!decode_win_cpu_valid() || !decode_win_usb_valid() || !decode_win_eth_valid() || !decode_win_idma_valid() || !decode_win_pcie_valid() || !decode_win_sata_valid() || - !decode_win_xor_valid()) + !decode_win_xor_valid() || !decode_win_usb3_valid()) return (EINVAL); decode_win_cpu_setup(); @@ -567,7 +571,7 @@ if (!decode_win_usb_valid() || !decode_win_eth_valid() || !decode_win_idma_valid() || !decode_win_pcie_valid() || !decode_win_sata_valid() || - !decode_win_xor_valid()) + !decode_win_xor_valid() || !decode_win_usb3_valid()) return (EINVAL); #endif if (MV_DUMP_WIN) @@ -600,6 +604,13 @@ WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) +#ifdef SOC_MV_ARMADA38X +WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) +WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) +WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) +WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) +#endif + WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) @@ -1118,6 +1129,85 @@ } /************************************************************************** + * USB3 windows routines + **************************************************************************/ +#ifdef SOC_MV_ARMADA38X +static int +decode_win_usb3_valid(void) +{ + + return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); +} + +static void +decode_win_usb3_dump(u_long base) +{ + int i; + + for (i = 0; i < MV_WIN_USB3_MAX; i++) + printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, + win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); +} + +/* + * Set USB3 decode windows + */ +static void +decode_win_usb3_setup(u_long base) +{ + uint32_t br, cr; + int i, j; + + for (i = 0; i < MV_WIN_USB3_MAX; i++) { + win_usb3_cr_write(base, i, 0); + win_usb3_br_write(base, i, 0); + } + + /* Only access to active DRAM banks is required */ + for (i = 0; i < MV_WIN_DDR_MAX; i++) { + if (ddr_is_active(i)) { + br = ddr_base(i); + cr = (((ddr_size(i) - 1) & + (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | + (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | + (ddr_target(i) << IO_WIN_TGT_SHIFT) | + IO_WIN_ENA_MASK); + + /* Set the first free USB3.0 window */ + for (j = 0; j < MV_WIN_USB3_MAX; j++) { + if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) + continue; + + win_usb3_br_write(base, j, br); + win_usb3_cr_write(base, j, cr); + break; + } + } + } +} +#else +/* + * Provide dummy functions to satisfy the build + * for SoCs not equipped with USB3 + */ +static int +decode_win_usb3_valid(void) +{ + + return (1); +} + +static void +decode_win_usb3_setup(u_long base) +{ +} + +static void +decode_win_usb3_dump(u_long base) +{ +} +#endif +/************************************************************************** * ETH windows routines **************************************************************************/ @@ -2077,6 +2167,17 @@ return (ENXIO); child = OF_child(node); } + /* + * Next, move one more level down to internal-regs node (if + * it is present) and its children. This node also have + * "simple-bus" compatible. + */ + if ((child == 0) && (node == OF_finddevice("simple-bus"))) { + node = fdt_find_compatible(node, "simple-bus", 0); + if (node == 0) + return (0); + child = OF_child(node); + } } return (0); Index: sys/arm/mv/mvwin.h =================================================================== --- sys/arm/mv/mvwin.h +++ sys/arm/mv/mvwin.h @@ -242,6 +242,10 @@ #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) #define MV_WIN_USB_MAX 4 +#define MV_WIN_USB3_CTRL(n) (0x8 * (n)) +#define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4) +#define MV_WIN_USB3_MAX 8 + #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) Index: sys/dev/usb/controller/xhci_mv.c =================================================================== --- /dev/null +++ sys/dev/usb/controller/xhci_mv.c @@ -0,0 +1,232 @@ +/*- + * Copyright (c) 2015 Semihalf. + * Copyright (c) 2015 Stormshield. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_bus.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#define XHCI_HC_DEVSTR "Marvell Integrated USB 3.0 controller" +#define XHCI_HC_VENDOR "Marvell" + +#define IS_DMA_32B 1 + +static device_attach_t xhci_attach; +static device_detach_t xhci_detach; + +static struct ofw_compat_data compat_data[] = { + {"marvell,armada-380-xhci", true}, + {NULL, false} +}; + +static int +xhci_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, XHCI_HC_DEVSTR); + + return (BUS_PROBE_DEFAULT); +} + +static int +xhci_attach(device_t dev) +{ + struct xhci_softc *sc = device_get_softc(dev); + int err = 0, rid = 0; + + sc->sc_bus.parent = dev; + sc->sc_bus.devices = sc->sc_devices; + sc->sc_bus.devices_max = XHCI_MAX_DEVICES; + + sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->sc_io_res == NULL) { + device_printf(dev, "Failed to map memory\n"); + xhci_detach(dev); + return (ENXIO); + } + + sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); + sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); + sc->sc_io_size = rman_get_size(sc->sc_io_res); + + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->sc_irq_res == NULL) { + device_printf(dev, "Failed to allocate IRQ\n"); + xhci_detach(dev); + return (ENXIO); + } + + sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (sc->sc_bus.bdev == NULL) { + device_printf(dev, "Failed to add USB device\n"); + xhci_detach(dev); + return (ENXIO); + } + + device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); + + sprintf(sc->sc_vendor, XHCI_HC_VENDOR); + device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR); + + err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); + if (err != 0) { + device_printf(dev, "Failed to setup error IRQ, %d\n", err); + sc->sc_intr_hdl = NULL; + xhci_detach(dev); + return (err); + } + + err = xhci_init(sc, dev, IS_DMA_32B); + if (err != 0) { + device_printf(dev, "Failed to init XHCI, with error %d\n", err); + xhci_detach(dev); + return (ENXIO); + } + + err = xhci_start_controller(sc); + if (err != 0) { + device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); + xhci_detach(dev); + return (ENXIO); + } + + err = device_probe_and_attach(sc->sc_bus.bdev); + if (err != 0) { + device_printf(dev, "Failed to initialize USB, with error %d\n", err); + xhci_detach(dev); + return (ENXIO); + } + + return (0); +} + +static int +xhci_detach(device_t dev) +{ + struct xhci_softc *sc = device_get_softc(dev); + device_t bdev; + int err; + + if (sc->sc_bus.bdev != NULL) { + bdev = sc->sc_bus.bdev; + device_detach(bdev); + device_delete_child(dev, bdev); + } + + /* during module unload there are lots of children leftover */ + device_delete_children(dev); + + if (sc->sc_irq_res != NULL && sc->sc_intr_hdl != NULL) { + err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); + if (err != 0) + device_printf(dev, "Could not tear down irq, %d\n", + err); + sc->sc_intr_hdl = NULL; + } + + if (sc->sc_irq_res != NULL) { + bus_release_resource(dev, SYS_RES_IRQ, + rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); + sc->sc_irq_res = NULL; + } + + if (sc->sc_io_res != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, + rman_get_rid(sc->sc_io_res), sc->sc_io_res); + sc->sc_io_res = NULL; + } + + xhci_uninit(sc); + + return (0); +} + +static device_method_t xhci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, xhci_probe), + DEVMETHOD(device_attach, xhci_attach), + DEVMETHOD(device_detach, xhci_detach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + DEVMETHOD_END +}; + +static driver_t xhci_driver = { + "xhci", + xhci_methods, + sizeof(struct xhci_softc), +}; + +static devclass_t xhci_devclass; + +DRIVER_MODULE(xhci, simplebus, xhci_driver, xhci_devclass, 0, 0); +MODULE_DEPEND(xhci, usb, 1, 1, 1);