diff --git a/share/man/man7/arch.7 b/share/man/man7/arch.7
--- a/share/man/man7/arch.7
+++ b/share/man/man7/arch.7
@@ -227,6 +227,43 @@
 .It powerpc64le Ta 4K
 .It riscv64     Ta 4K, 2M, 1G
 .El
+.Ss User Address Space Layout
+.Bl -column -offset indent "Architecture" "Maximum Address" "Address Space Size"
+.It Sy Architecture Ta Sy Maximum Address Ta Sy Address Space Size
+.It aarch64        Ta 0x0001000000000000 Ta 256T
+.It amd64 (LA48)   Ta 0x0000800000000000 Ta 128T
+.It amd64 (LA57)   Ta 0x0100000000000000 Ta 64P
+.It armv7          Ta 0xbfc00000         Ta 3G
+.It i386           Ta 0xffc00000         Ta 4G
+.It powerpc        Ta 0xfffff000         Ta 4G
+.It powerpcspe     Ta 0x7ffff000         Ta 2G
+.It powerpc64      Ta 0x000fffffc0000000 Ta 4P
+.It powerpc64le    Ta 0x000fffffc0000000 Ta 4P
+.It riscv64 (Sv39) Ta 0x0000004000000000 Ta 256G
+.It riscv64 (Sv48) Ta 0x0000800000000000 Ta 128T
+.El
+.Pp
+Historically, amd64 CPUs were limited to a 48-bit virtual address space.
+Newer CPUs support 5-level page tables, which extend the address space to 57
+bits (LA57 mode).
+The address space layout is determined by the CPU's support for LA57.
+The
+.Sy vm.pmap.la57
+tunable can be used to disable LA57 mode.
+The
+.Xr elfctl 1
+utility can be used to request LA48 mode for specific executables.
+.Pp
+The RISC-V specification permits 3-level (Sv39), 4-level (Sv48), and
+5-level (Sv57) page tables.
+Hardware is only required to implement Sv39; implementations which support
+Sv48 must also support Sv39, and implementations which support Sv57 must also
+support Sv48.
+The
+.Sy vm.pmap.mode
+tunable can be used to select the layout.
+.Fx
+currently supports Sv39 and Sv48 and defaults to using Sv39.
 .Ss Floating Point
 .Bl -column -offset indent "Architecture" "float, double" "long double"
 .It Sy Architecture Ta Sy float, double Ta Sy long double
@@ -424,6 +461,7 @@
 it is unused outside of that scope.
 .El
 .Sh SEE ALSO
+.Xr elfctl 1 ,
 .Xr src.conf 5 ,
 .Xr build 7 ,
 .Xr simd 7