diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -137,9 +137,11 @@ uint64_t id_aa64afr1; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; + uint64_t id_aa64dfr2; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64isar2; + uint64_t id_aa64isar3; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; @@ -149,6 +151,7 @@ uint64_t id_aa64pfr1; uint64_t id_aa64pfr2; uint64_t id_aa64zfr0; + uint64_t id_aa64smfr0; uint64_t ctr; #ifdef COMPAT_FREEBSD32 uint64_t id_isar5; @@ -158,6 +161,7 @@ uint64_t clidr; uint32_t ccsidr[MAX_CACHES][2]; /* 2 possible types. */ bool have_sve; + bool have_sme; }; static struct cpu_desc cpu_desc0; @@ -495,12 +499,22 @@ MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64dfr0_exttrcbuff[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, ExtTrcBuff, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64dfr0_brbe[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, BRBE, NONE, IMPL), MRS_FIELD_VALUE(ID_AA64DFR0_BRBE_EL3, "BRBE EL3"), MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64dfr0_sebep[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, SEBEP, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64dfr0_mtpmu[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR0, MTPMU, NONE, IMPL), MRS_FIELD_VALUE(ID_AA64DFR0_MTPMU_NONE_MT_RES0, "MTPMU res0"), @@ -585,6 +599,7 @@ static const struct mrs_field id_aa64dfr0_fields[] = { MRS_FIELD(ID_AA64DFR0, HPMN0, false, MRS_LOWER, 0, id_aa64dfr0_hpmn0), + MRS_FIELD(ID_AA64DFR0, ExtTrcBuff, false, MRS_LOWER, 0, id_aa64dfr0_exttrcbuff), MRS_FIELD(ID_AA64DFR0, BRBE, false, MRS_LOWER, 0, id_aa64dfr0_brbe), MRS_FIELD(ID_AA64DFR0, MTPMU, true, MRS_LOWER, 0, id_aa64dfr0_mtpmu), MRS_FIELD(ID_AA64DFR0, TraceBuffer, false, MRS_LOWER, 0, @@ -596,6 +611,7 @@ MRS_FIELD(ID_AA64DFR0, PMSVer, false, MRS_LOWER, 0, id_aa64dfr0_pmsver), MRS_FIELD(ID_AA64DFR0, CTX_CMPs, false, MRS_LOWER, 0, id_aa64dfr0_ctx_cmps), + MRS_FIELD(ID_AA64DFR0, SEBEP, false, MRS_LOWER, 0, id_aa64dfr0_sebep), MRS_FIELD(ID_AA64DFR0, WRPs, false, MRS_LOWER, MRS_USERSPACE, id_aa64dfr0_wrps), MRS_FIELD(ID_AA64DFR0, PMSS, false, MRS_LOWER, 0, id_aa64dfr0_pmss), @@ -616,23 +632,61 @@ MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64dfr1_ebep[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, EBEP, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64dfr1_ite[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, ITE, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64dfr1_able[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, ABLE, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64dfr1_pmicntr[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, PMICNTR, NONE, IMPL), MRS_FIELD_VALUE_END, }; static const struct mrs_field_value id_aa64dfr1_spmu[] = { - MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR1, SPMU, NONE, IMPL), + MRS_FIELD_VALUE(ID_AA64DFR1_SPMU_NONE, ""), + MRS_FIELD_VALUE(ID_AA64DFR1_SPMU_8_9, "SPMU"), + MRS_FIELD_VALUE(ID_AA64DFR1_SPMU_9_5, "SPMU2"), MRS_FIELD_VALUE_END, }; static const struct mrs_field id_aa64dfr1_fields[] = { MRS_FIELD(ID_AA64DFR1, DPFZS, false, MRS_LOWER, 0, id_aa64dfr1_dpfzs), + MRS_FIELD(ID_AA64DFR1, EBEP, false, MRS_LOWER, 0, id_aa64dfr1_ebep), + MRS_FIELD(ID_AA64DFR1, ITE, false, MRS_LOWER, 0, id_aa64dfr1_ite), + MRS_FIELD(ID_AA64DFR1, ABLE, false, MRS_LOWER, 0, id_aa64dfr1_able), MRS_FIELD(ID_AA64DFR1, PMICNTR, false, MRS_LOWER, 0, id_aa64dfr1_pmicntr), MRS_FIELD(ID_AA64DFR1, SPMU, false, MRS_LOWER, 0, id_aa64dfr1_spmu), MRS_FIELD_END, }; +/* ID_AA64DFR2_EL1 */ +static const struct mrs_field_value id_aa64dfr1_step[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64DFR2, STEP, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64dfr1_bwe[] = { + MRS_FIELD_VALUE(ID_AA64DFR2_BWE_NONE, ""), + MRS_FIELD_VALUE(ID_AA64DFR2_BWE_9_4, "BWE9p4"), + MRS_FIELD_VALUE(ID_AA64DFR2_BWE_9_5, "BWE9p5"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field id_aa64dfr2_fields[] = { + MRS_FIELD(ID_AA64DFR2, STEP, false, MRS_LOWER, 0, id_aa64dfr1_step), + MRS_FIELD(ID_AA64DFR2, BWE, false, MRS_LOWER, 0, id_aa64dfr1_bwe), + MRS_FIELD_END, +}; /* ID_AA64ISAR0_EL1 */ static const struct mrs_field_value id_aa64isar0_rndr[] = { @@ -774,7 +828,8 @@ }; static const struct mrs_field_value id_aa64isar0_aes[] = { - MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR0, AES, NONE, BASE), + MRS_FIELD_VALUE(ID_AA64ISAR0_AES_NONE, ""), + MRS_FIELD_VALUE(ID_AA64ISAR0_AES_BASE, "AES"), MRS_FIELD_VALUE(ID_AA64ISAR0_AES_PMULL, "AES+PMULL"), MRS_FIELD_VALUE_END, }; @@ -1043,6 +1098,16 @@ MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64isar2_sysinstr128[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, SYSINSTR128, NONE, IMPL), + MRS_FIELD_VALUE_END +}; + +static const struct mrs_field_value id_aa64isar2_sysreg128[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, SYSREG128, NONE, IMPL), + MRS_FIELD_VALUE_END +}; + static const struct mrs_field_value id_aa64isar2_clrbhb[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR2, CLRBHB, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -1114,6 +1179,8 @@ MRS_FIELD(ID_AA64ISAR2, CSSC, false, MRS_LOWER, 0, id_aa64isar2_cssc), MRS_FIELD(ID_AA64ISAR2, RPRFM, false, MRS_LOWER, 0, id_aa64isar2_rprfm), MRS_FIELD(ID_AA64ISAR2, PRFMSLC, false, MRS_LOWER, 0, id_aa64isar2_prfmslc), + MRS_FIELD(ID_AA64ISAR2, SYSINSTR128, false, MRS_LOWER, 0, id_aa64isar2_sysinstr128), + MRS_FIELD(ID_AA64ISAR2, SYSREG128, false, MRS_LOWER, 0, id_aa64isar2_sysreg128), MRS_FIELD(ID_AA64ISAR2, CLRBHB, false, MRS_LOWER, 0, id_aa64isar2_clrbhb), MRS_FIELD(ID_AA64ISAR2, PAC_frac, false, MRS_LOWER, 0, id_aa64isar2_pac_frac), @@ -1130,6 +1197,36 @@ MRS_FIELD_END, }; +/* ID_AA64ISAR3_EL1 */ +static const struct mrs_field_value id_aa64isar3_cpa[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR3, CPA, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64isar3_faminmax[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR3, FAMINMAX, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64isar3_tlbiw[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR3, TLBIW, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64isar3_pacm[] = { + MRS_FIELD_VALUE(ID_AA64ISAR3_PACM_NONE, ""), + MRS_FIELD_VALUE(ID_AA64ISAR3_PACM_TRIV, "PACMTriv"), + MRS_FIELD_VALUE(ID_AA64ISAR3_PACM_FULL, "PACMFull"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field id_aa64isar3_fields[] = { + MRS_FIELD(ID_AA64ISAR3, CPA, false, MRS_LOWER, 0, id_aa64isar3_cpa), + MRS_FIELD(ID_AA64ISAR3, FAMINMAX, false, MRS_LOWER, 0, id_aa64isar3_faminmax), + MRS_FIELD(ID_AA64ISAR3, TLBIW, false, MRS_LOWER, 0, id_aa64isar3_tlbiw), + MRS_FIELD(ID_AA64ISAR3, PACM, false, MRS_LOWER, 0, id_aa64isar3_pacm), + MRS_FIELD_END, +}; /* ID_AA64MMFR0_EL1 */ static const struct mrs_field_value id_aa64mmfr0_ecv[] = { @@ -1516,6 +1613,16 @@ MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64mmfr3_d128_v2[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, D128_v2, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr3_d128[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, D128, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64mmfr3_mec[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -1563,6 +1670,8 @@ MRS_FIELD(ID_AA64MMFR3, SDERR, false, MRS_LOWER, 0, id_aa64mmfr3_sderr), MRS_FIELD(ID_AA64MMFR3, ANERR, false, MRS_LOWER, 0, id_aa64mmfr3_anerr), MRS_FIELD(ID_AA64MMFR3, SNERR, false, MRS_LOWER, 0, id_aa64mmfr3_snerr), + MRS_FIELD(ID_AA64MMFR3, D128_v2, false, MRS_LOWER, 0, id_aa64mmfr3_d128_v2), + MRS_FIELD(ID_AA64MMFR3, D128, false, MRS_LOWER, 0, id_aa64mmfr3_d128), MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_LOWER, 0, id_aa64mmfr3_mec), MRS_FIELD(ID_AA64MMFR3, AIE, false, MRS_LOWER, 0, id_aa64mmfr3_aie), MRS_FIELD(ID_AA64MMFR3, S2POE, false, MRS_LOWER, 0, id_aa64mmfr3_s2poe), @@ -1577,7 +1686,52 @@ /* ID_AA64MMFR4_EL1 */ +static const struct mrs_field_value id_aa64mmfr4_eiesb[] = { + MRS_FIELD_VALUE(ID_AA64MMFR4_EIESB_NONE, ""), + MRS_FIELD_VALUE(ID_AA64MMFR4_EIESB_IMPL, "EIESB"), + MRS_FIELD_VALUE(ID_AA64MMFR4_EIESB_DF, "EIESB+DF"), + MRS_FIELD_VALUE(ID_AA64MMFR4_EIESB_DF2, "EIESB+DF2"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_asid2[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, ASID2, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_hacdbs[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, HACDBS, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_fgwte3[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, FGWTE3, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_nvfrac[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, NV_frac, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_e2h0[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, E2H0, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr4_e3dse[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR4, E3DSE, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field id_aa64mmfr4_fields[] = { + MRS_FIELD(ID_AA64MMFR4, EIESB, false, MRS_LOWER, 0, id_aa64mmfr4_eiesb), + MRS_FIELD(ID_AA64MMFR4, ASID2, false, MRS_LOWER, 0, id_aa64mmfr4_asid2), + MRS_FIELD(ID_AA64MMFR4, HACDBS, false, MRS_LOWER, 0, id_aa64mmfr4_hacdbs), + MRS_FIELD(ID_AA64MMFR4, FGWTE3, false, MRS_LOWER, 0, id_aa64mmfr4_fgwte3), + MRS_FIELD(ID_AA64MMFR4, NV_frac, false, MRS_LOWER, 0, id_aa64mmfr4_nvfrac), + MRS_FIELD(ID_AA64MMFR4, E2H0, false, MRS_LOWER, 0, id_aa64mmfr4_e2h0), + MRS_FIELD(ID_AA64MMFR4, E3DSE, false, MRS_LOWER, 0, id_aa64mmfr4_e3dse), MRS_FIELD_END, }; @@ -1752,6 +1906,11 @@ MRS_FIELD_VALUE_END, }; +static const struct mrs_field_value id_aa64pfr1_gcs[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, GCS, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64pfr1_mtefrac[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR1, MTE_frac, NONE, IMPL), MRS_FIELD_VALUE_END, @@ -1829,6 +1988,7 @@ MRS_FIELD(ID_AA64PFR1, DF2, false, MRS_LOWER, 0, id_aa64pfr1_df2), MRS_FIELD(ID_AA64PFR1, MTEX, false, MRS_LOWER, 0, id_aa64pfr1_mtex), MRS_FIELD(ID_AA64PFR1, THE, false, MRS_LOWER, 0, id_aa64pfr1_the), + MRS_FIELD(ID_AA64PFR1, GCS, false, MRS_LOWER, 0, id_aa64pfr1_gcs), MRS_FIELD(ID_AA64PFR1, MTE_frac, false, MRS_LOWER, 0, id_aa64pfr1_mtefrac), MRS_FIELD(ID_AA64PFR1, NMI, false, MRS_LOWER, 0, id_aa64pfr1_nmi), MRS_FIELD(ID_AA64PFR1, CSV2_frac, false, MRS_LOWER, 0, @@ -1850,7 +2010,31 @@ /* ID_AA64PFR2_EL1 */ +static const struct mrs_field_value id_aa64pfr2_mteperm[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR2, MTEPERM, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64pfr2_mtestoreonly[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR2, MTESTOREONLY, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64pfr2_mtefar[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR2, MTEFAR, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64pfr2_fpmr[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR2, FPMR, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field id_aa64pfr2_fields[] = { + MRS_FIELD(ID_AA64PFR2, MTEPERM, false, MRS_LOWER, 0, id_aa64pfr2_mteperm), + MRS_FIELD(ID_AA64PFR2, MTESTOREONLY, false, MRS_LOWER, 0, id_aa64pfr2_mtestoreonly), + MRS_FIELD(ID_AA64PFR2, MTEFAR, false, MRS_LOWER, 0, id_aa64pfr2_mtefar), + MRS_FIELD(ID_AA64PFR2, FPMR, false, MRS_LOWER, 0, id_aa64pfr2_fpmr), MRS_FIELD_END, }; @@ -1928,6 +2112,11 @@ MRS_HWCAP_END, }; +static const struct mrs_field_value id_aa64zfr0_eltperm[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, EltPerm, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + static const struct mrs_field_value id_aa64zfr0_aes[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, AES, NONE, BASE), MRS_FIELD_VALUE(ID_AA64ZFR0_AES_PMULL, "AES+PMULL"), @@ -1968,6 +2157,8 @@ id_aa64zfr0_bf16, id_aa64zfr0_bf16_caps), MRS_FIELD_HWCAP(ID_AA64ZFR0, BitPerm, false, MRS_LOWER, MRS_USERSPACE, id_aa64zfr0_bitperm, id_aa64zfr0_bitperm_caps), + MRS_FIELD(ID_AA64ZFR0, EltPerm, false, MRS_LOWER, MRS_USERSPACE, + id_aa64zfr0_eltperm), MRS_FIELD_HWCAP(ID_AA64ZFR0, AES, false, MRS_LOWER, MRS_USERSPACE, id_aa64zfr0_aes, id_aa64zfr0_aes_caps), MRS_FIELD_HWCAP(ID_AA64ZFR0, SVEver, false, MRS_LOWER, MRS_USERSPACE, @@ -1975,6 +2166,165 @@ MRS_FIELD_END, }; +/* ID_AA64SMFR0_EL1 */ +static const struct mrs_field_value id_aa64smfr0_smop4[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SMOP4, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_stmop[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, STMOP, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_sfexpa[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SFEXPA, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_sbitperm[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SBitPerm, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_sf8dp2[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SF8DP2, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_sf8dp4[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SF8DP4, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_sf8fma[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, SF8FMA, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f32f32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F32F32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_bi32i32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, BI32I32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_b16f32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, B16F32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f16f32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F16F32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_i8i32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, I8I32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f8f32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F8F32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f8f16[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F8F16, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f16f16[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F16F16, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_b16b16[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, B16B16, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_i16i32[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, I16I32, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_f64f64[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, F64F64, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_i16i64[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, I16I64, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_smever[] = { + MRS_FIELD_VALUE(ID_AA64SMFR0_SMEver_BASE, "SME"), + MRS_FIELD_VALUE(ID_AA64SMFR0_SMEver_2_0, "SME2"), + MRS_FIELD_VALUE(ID_AA64SMFR0_SMEver_2_1, "SME2p1"), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_lutv2[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, LUTv2, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64smfr0_fa64[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64SMFR0, FA64, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field id_aa64smfr0_fields[] = { + MRS_FIELD(ID_AA64SMFR0, SMOP4, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_smop4), + MRS_FIELD(ID_AA64SMFR0, STMOP, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_stmop), + MRS_FIELD(ID_AA64SMFR0, SFEXPA, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_sfexpa), + MRS_FIELD(ID_AA64SMFR0, SBitPerm, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_sbitperm), + MRS_FIELD(ID_AA64SMFR0, SF8DP2, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_sf8dp2), + MRS_FIELD(ID_AA64SMFR0, SF8DP4, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_sf8dp4), + MRS_FIELD(ID_AA64SMFR0, SF8FMA, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_sf8fma), + MRS_FIELD(ID_AA64SMFR0, F32F32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f32f32), + MRS_FIELD(ID_AA64SMFR0, BI32I32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_bi32i32), + MRS_FIELD(ID_AA64SMFR0, B16F32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_b16f32), + MRS_FIELD(ID_AA64SMFR0, F16F32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f16f32), + MRS_FIELD(ID_AA64SMFR0, I8I32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_i8i32), + MRS_FIELD(ID_AA64SMFR0, F8F32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f8f32), + MRS_FIELD(ID_AA64SMFR0, F8F16, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f8f16), + MRS_FIELD(ID_AA64SMFR0, F16F16, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f16f16), + MRS_FIELD(ID_AA64SMFR0, B16B16, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_b16b16), + MRS_FIELD(ID_AA64SMFR0, I16I32, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_i16i32), + MRS_FIELD(ID_AA64SMFR0, F64F64, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_f64f64), + MRS_FIELD(ID_AA64SMFR0, I16I64, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_i16i64), + MRS_FIELD(ID_AA64SMFR0, SMEver, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_smever), + MRS_FIELD(ID_AA64SMFR0, LUTv2, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_lutv2), + MRS_FIELD(ID_AA64SMFR0, FA64, false, MRS_LOWER, MRS_USERSPACE, + id_aa64smfr0_fa64), +}; #ifdef COMPAT_FREEBSD32 /* ID_ISAR5_EL1 */ @@ -3107,6 +3457,11 @@ print_id_register(sb, "Instruction Set Attributes 2", desc->id_aa64isar2, id_aa64isar2_fields); + /* AArch64 Instruction Set Attribute Register 3 */ + if (SHOULD_PRINT_REG(id_aa64isar3)) + print_id_register(sb, "Instruction Set Attributes 3", + desc->id_aa64isar3, id_aa64isar3_fields); + /* AArch64 Processor Feature Register 0 */ if (SHOULD_PRINT_REG(id_aa64pfr0)) print_id_register(sb, "Processor Features 0", @@ -3152,11 +3507,16 @@ print_id_register(sb, "Debug Features 0", desc->id_aa64dfr0, id_aa64dfr0_fields); - /* AArch64 Memory Model Feature Register 1 */ + /* AArch64 Debug Feature Register 1 */ if (SHOULD_PRINT_REG(id_aa64dfr1)) print_id_register(sb, "Debug Features 1", desc->id_aa64dfr1, id_aa64dfr1_fields); + /* AArch64 Debug Feature Register 2 */ + if (SHOULD_PRINT_REG(id_aa64dfr2)) + print_id_register(sb, "Debug Features 2", + desc->id_aa64dfr2, id_aa64dfr2_fields); + /* AArch64 Auxiliary Feature Register 0 */ if (SHOULD_PRINT_REG(id_aa64afr0)) print_id_register(sb, "Auxiliary Features 0", @@ -3176,6 +3536,15 @@ } } + /* AArch64 SME Feature Register 0 */ + if (desc->have_sme) { + if (SHOULD_PRINT_REG(id_aa64smfr0) || + !prev_desc->have_sme) { + print_id_register(sb, "SME Features 0", + desc->id_aa64smfr0, id_aa64smfr0_fields); + } + } + #ifdef COMPAT_FREEBSD32 /* AArch32 Instruction Set Attribute Register 5 */ if (SHOULD_PRINT_REG(id_isar5)) @@ -3252,9 +3621,11 @@ desc->ctr = READ_SPECIALREG(ctr_el0); desc->id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1_REG); desc->id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1_REG); + desc->id_aa64dfr2 = READ_SPECIALREG(ID_AA64DFR2_EL1_REG); desc->id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1_REG); desc->id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1_REG); desc->id_aa64isar2 = READ_SPECIALREG(ID_AA64ISAR2_EL1_REG); + desc->id_aa64isar3 = READ_SPECIALREG(ID_AA64ISAR3_EL1_REG); desc->id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1_REG); desc->id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1_REG); desc->id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1_REG); @@ -3265,17 +3636,16 @@ desc->id_aa64pfr2 = READ_SPECIALREG(ID_AA64PFR2_EL1_REG); /* - * ID_AA64ZFR0_EL1 is only valid when at least one of: - * - ID_AA64PFR0_EL1.SVE is non-zero - * - ID_AA64PFR1_EL1.SME is non-zero - * In other cases it is zero, but still safe to read + * ID_AA64ZFR0_EL1 and ID_AA64SMFR0_EL1 are only valid when at least one of + * ID_AA64PFR0_EL1.SVE or ID_AA64PFR1_EL1.SME are non-zero. In other cases + * it is zero, but still safe to read. */ - desc->have_sve = - (ID_AA64PFR0_SVE_VAL(desc->id_aa64pfr0) != 0); - desc->id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG); + desc->have_sve = (ID_AA64PFR0_SVE_VAL(desc->id_aa64pfr0) != 0); + desc->have_sme = (ID_AA64PFR1_SME_VAL(desc->id_aa64pfr1) != 0); + desc->id_aa64zfr0 = READ_SPECIALREG(ID_AA64ZFR0_EL1_REG); + desc->id_aa64smfr0 = READ_SPECIALREG(ID_AA64SMFR0_EL1_REG); desc->clidr = READ_SPECIALREG(clidr_el1); - clidr = desc->clidr; for (int i = 0; (clidr & CLIDR_CTYPE_MASK) != 0; i++, clidr >>= 3) { diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -831,6 +831,12 @@ #define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT) #define ID_AA64DFR0_WRPs_VAL(x) \ ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1) +#define ID_AA64DFR0_SEBEP_SHIFT 24 +#define ID_AA64DFR0_SEBEP_WIDTH 4 +#define ID_AA64DFR0_SEBEP_MASK (UL(0xf) << ID_AA64DFR0_SEBEP_SHIFT) +#define ID_AA64DFR0_SEBEP_VAL(x) ((x) & ID_AA64DFR0_SEBEP_MASK) +#define ID_AA64DFR0_SEBEP_NONE (UL(0x0) << ID_AA64DFR0_SEBEP_SHIFT) +#define ID_AA64DFR0_SEBEP_IMPL (UL(0x1) << ID_AA64DFR0_SEBEP_SHIFT) #define ID_AA64DFR0_CTX_CMPs_SHIFT 28 #define ID_AA64DFR0_CTX_CMPs_WIDTH 4 #define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT) @@ -878,6 +884,12 @@ #define ID_AA64DFR0_BRBE_NONE (UL(0x0) << ID_AA64DFR0_BRBE_SHIFT) #define ID_AA64DFR0_BRBE_IMPL (UL(0x1) << ID_AA64DFR0_BRBE_SHIFT) #define ID_AA64DFR0_BRBE_EL3 (UL(0x2) << ID_AA64DFR0_BRBE_SHIFT) +#define ID_AA64DFR0_ExtTrcBuff_SHIFT 56 +#define ID_AA64DFR0_ExtTrcBuff_WIDTH 4 +#define ID_AA64DFR0_ExtTrcBuff_MASK (UL(0xf) << ID_AA64DFR0_ExtTrcBuff_SHIFT) +#define ID_AA64DFR0_ExtTrcBuff_VAL(x) ((x) & ID_AA64DFR0_ExtTrcBuff_MASK) +#define ID_AA64DFR0_ExtTrcBuff_NONE (UL(0x0) << ID_AA64DFR0_ExtTrcBuff_SHIFT) +#define ID_AA64DFR0_ExtTrcBuff_IMPL (UL(0x1) << ID_AA64DFR0_ExtTrcBuff_SHIFT) #define ID_AA64DFR0_HPMN0_SHIFT 60 #define ID_AA64DFR0_HPMN0_WIDTH 4 #define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT) @@ -898,13 +910,32 @@ #define ID_AA64DFR1_SPMU_MASK (UL(0xf) << ID_AA64DFR1_SPMU_SHIFT) #define ID_AA64DFR1_SPMU_VAL(x) ((x) & ID_AA64DFR1_SPMU_MASK) #define ID_AA64DFR1_SPMU_NONE (UL(0x0) << ID_AA64DFR1_SPMU_SHIFT) -#define ID_AA64DFR1_SPMU_IMPL (UL(0x1) << ID_AA64DFR1_SPMU_SHIFT) +#define ID_AA64DFR1_SPMU_8_9 (UL(0x1) << ID_AA64DFR1_SPMU_SHIFT) +#define ID_AA64DFR1_SPMU_9_5 (UL(0x2) << ID_AA64DFR1_SPMU_SHIFT) #define ID_AA64DFR1_PMICNTR_SHIFT 36 #define ID_AA64DFR1_PMICNTR_WIDTH 4 #define ID_AA64DFR1_PMICNTR_MASK (UL(0xf) << ID_AA64DFR1_PMICNTR_SHIFT) #define ID_AA64DFR1_PMICNTR_VAL(x) ((x) & ID_AA64DFR1_PMICNTR_MASK) #define ID_AA64DFR1_PMICNTR_NONE (UL(0x0) << ID_AA64DFR1_PMICNTR_SHIFT) #define ID_AA64DFR1_PMICNTR_IMPL (UL(0x1) << ID_AA64DFR1_PMICNTR_SHIFT) +#define ID_AA64DFR1_ABLE_SHIFT 40 +#define ID_AA64DFR1_ABLE_WIDTH 4 +#define ID_AA64DFR1_ABLE_MASK (UL(0xf) << ID_AA64DFR1_ABLE_SHIFT) +#define ID_AA64DFR1_ABLE_VAL(x) ((x) & ID_AA64DFR1_ABLE_MASK) +#define ID_AA64DFR1_ABLE_NONE (UL(0x0) << ID_AA64DFR1_ABLE_SHIFT) +#define ID_AA64DFR1_ABLE_IMPL (UL(0x1) << ID_AA64DFR1_ABLE_SHIFT) +#define ID_AA64DFR1_ITE_SHIFT 44 +#define ID_AA64DFR1_ITE_WIDTH 4 +#define ID_AA64DFR1_ITE_MASK (UL(0xf) << ID_AA64DFR1_ITE_SHIFT) +#define ID_AA64DFR1_ITE_VAL(x) ((x) & ID_AA64DFR1_ITE_MASK) +#define ID_AA64DFR1_ITE_NONE (UL(0x0) << ID_AA64DFR1_ITE_SHIFT) +#define ID_AA64DFR1_ITE_IMPL (UL(0x1) << ID_AA64DFR1_ITE_SHIFT) +#define ID_AA64DFR1_EBEP_SHIFT 48 +#define ID_AA64DFR1_EBEP_WIDTH 4 +#define ID_AA64DFR1_EBEP_MASK (UL(0xf) << ID_AA64DFR1_EBEP_SHIFT) +#define ID_AA64DFR1_EBEP_VAL(x) ((x) & ID_AA64DFR1_EBEP_MASK) +#define ID_AA64DFR1_EBEP_NONE (UL(0x0) << ID_AA64DFR1_EBEP_SHIFT) +#define ID_AA64DFR1_EBEP_IMPL (UL(0x1) << ID_AA64DFR1_EBEP_SHIFT) #define ID_AA64DFR1_DPFZS_SHIFT 52 #define ID_AA64DFR1_DPFZS_WIDTH 4 #define ID_AA64DFR1_DPFZS_MASK (UL(0xf) << ID_AA64DFR1_DPFZS_SHIFT) @@ -912,6 +943,28 @@ #define ID_AA64DFR1_DPFZS_NONE (UL(0x0) << ID_AA64DFR1_DPFZS_SHIFT) #define ID_AA64DFR1_DPFZS_IMPL (UL(0x1) << ID_AA64DFR1_DPFZS_SHIFT) +/* ID_AA64DFR2_EL1 */ +#define ID_AA64DFR2_EL1 MRS_REEG(ID_AA64DFR2_EL1) +#define ID_AA64DFR2_EL1_REG MRS_REG_ALT_NAME(ID_AA64DFR2_EL1) +#define ID_AA64DFR2_EL1_op0 3 +#define ID_AA64DFR2_EL1_op1 0 +#define ID_AA64DFR2_EL1_CRn 0 +#define ID_AA64DFR2_EL1_CRm 5 +#define ID_AA64DFR2_EL1_op2 2 +#define ID_AA64DFR2_STEP_SHIFT 0 +#define ID_AA64DFR2_STEP_WIDTH 4 +#define ID_AA64DFR2_STEP_MASK (UL(0xf) << ID_AA64DFR2_STEP_SHIFT) +#define ID_AA64DFR2_STEP_VAL(x) ((x) & ID_AA64DFR2_STEP_MASK) +#define ID_AA64DFR2_STEP_NONE (UL(0x0) << ID_AA64DFR2_STEP_SHIFT) +#define ID_AA64DFR2_STEP_IMPL (UL(0x1) << ID_AA64DFR2_STEP_SHIFT) +#define ID_AA64DFR2_BWE_SHIFT 4 +#define ID_AA64DFR2_BWE_WIDTH 4 +#define ID_AA64DFR2_BWE_MASK (UL(0xf) << ID_AA64DFR2_BWE_SHIFT) +#define ID_AA64DFR2_BWE_VAL(x) ((x) & ID_AA64DFR2_BWE_MASK) +#define ID_AA64DFR2_BWE_NONE (UL(0x0) << ID_AA64DFR2_BWE_SHIFT) +#define ID_AA64DFR2_BWE_9_4 (UL(0x1) << ID_AA64DFR2_BWE_SHIFT) +#define ID_AA64DFR2_BWE_9_5 (UL(0x2) << ID_AA64DFR2_BWE_SHIFT) + /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_EL1 MRS_REG(ID_AA64ISAR0_EL1) #define ID_AA64ISAR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1) @@ -1193,6 +1246,21 @@ #define ID_AA64ISAR2_CLRBHB_VAL(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) #define ID_AA64ISAR2_CLRBHB_NONE (UL(0x0) << ID_AA64ISAR2_CLRBHB_SHIFT) #define ID_AA64ISAR2_CLRBHB_IMPL (UL(0x1) << ID_AA64ISAR2_CLRBHB_SHIFT) +#define ID_AA64ISAR2_SYSREG128_SHIFT 32 +#define ID_AA64ISAR2_SYSREG128_WIDTH 4 +#define ID_AA64ISAR2_SYSREG128_MASK (UL(0xf) << ID_AA64ISAR2_SYSREG128_SHIFT) +#define ID_AA64ISAR2_SYSREG128_VAL(x) ((x) & ID_AA64ISAR2_SYSREG128_MASK) +#define ID_AA64ISAR2_SYSREG128_NONE (UL(0x0) << ID_AA64ISAR2_SYSREG128_SHIFT) +#define ID_AA64ISAR2_SYSREG128_IMPL (UL(0x1) << ID_AA64ISAR2_SYSREG128_SHIFT) +#define ID_AA64ISAR2_SYSINSTR128_SHIFT 36 +#define ID_AA64ISAR2_SYSINSTR128_WIDTH 4 +#define ID_AA64ISAR2_SYSINSTR128_MASK \ + (UL(0xf) << ID_AA64ISAR2_SYSINSTR128_SHIFT) +#define ID_AA64ISAR2_SYSINSTR128_VAL(x) ((x) & ID_AA64ISAR2_SYSINSTR128_MASK) +#define ID_AA64ISAR2_SYSINSTR128_NONE \ + (UL(0x0) << ID_AA64ISAR2_SYSINSTR128_SHIFT) +#define ID_AA64ISAR2_SYSINSTR128_IMPL \ + (UL(0x1) << ID_AA64ISAR2_SYSINSTR128_SHIFT) #define ID_AA64ISAR2_PRFMSLC_SHIFT 40 #define ID_AA64ISAR2_PRFMSLC_WIDTH 4 #define ID_AA64ISAR2_PRFMSLC_MASK (UL(0xf) << ID_AA64ISAR2_PRFMSLC_SHIFT) @@ -1218,6 +1286,41 @@ #define ID_AA64ISAR2_ATS1A_NONE (UL(0x0) << ID_AA64ISAR2_ATS1A_SHIFT) #define ID_AA64ISAR2_ATS1A_IMPL (UL(0x1) << ID_AA64ISAR2_ATS1A_SHIFT) +/* ID_AA64ISAR3_EL1 */ +#define ID_AA64ISAR3_EL1 MRS_REG(ID_AA64ISAR3_EL1) +#define ID_AA64ISAR3_EL1_REG MRS_REG_ALT_NAME(ID_AA64ISAR3_EL1) +#define ID_AA64ISAR3_EL1_op0 2 +#define ID_AA64ISAR3_EL1_op1 0 +#define ID_AA64ISAR3_EL1_CRn 0 +#define ID_AA64ISAR3_EL1_CRm 6 +#define ID_AA64ISAR3_EL1_op2 6 +#define ID_AA64ISAR3_CPA_SHIFT 0 +#define ID_AA64ISAR3_CPA_WIDTH 4 +#define ID_AA64ISAR3_CPA_MASK (UL(0xf) << ID_AA64ISAR3_CPA_SHIFT) +#define ID_AA64ISAR3_CPA_VAL(x) ((x) & ID_AA64ISAR3_CPA_MASK) +#define ID_AA64ISAR3_CPA_NONE (UL(0x0) << ID_AA64ISAR3_CPA_SHIFT) +#define ID_AA64ISAR3_CPA_IMPL (UL(0x1) << ID_AA64ISAR3_CPA_SHIFT) +#define ID_AA64ISAR3_CPA_IMPLEn (UL(0x2) << ID_AA64ISAR3_CPA_SHIFT) +#define ID_AA64ISAR3_FAMINMAX_SHIFT 4 +#define ID_AA64ISAR3_FAMINMAX_WIDTH 4 +#define ID_AA64ISAR3_FAMINMAX_MASK (UL(0xf) << ID_AA64ISAR3_FAMINMAX_SHIFT) +#define ID_AA64ISAR3_FAMINMAX_VAL(x)((x) & ID_AA64ISAR3_FAMINMAX_MASK) +#define ID_AA64ISAR3_FAMINMAX_NONE (UL(0x0) << ID_AA64ISAR3_FAMINMAX_SHIFT) +#define ID_AA64ISAR3_FAMINMAX_IMPL (UL(0x1) << ID_AA64ISAR3_FAMINMAX_SHIFT) +#define ID_AA64ISAR3_TLBIW_SHIFT 8 +#define ID_AA64ISAR3_TLBIW_WIDTH 4 +#define ID_AA64ISAR3_TLBIW_MASK (UL(0xf) << ID_AA64ISAR3_TLBIW_SHIFT) +#define ID_AA64ISAR3_TLBIW_VAL(x) ((x) & ID_AA64ISAR3_TLBIW_MASK) +#define ID_AA64ISAR3_TLBIW_NONE (UL(0x0) << ID_AA64ISAR3_TLBIW_SHIFT) +#define ID_AA64ISAR3_TLBIW_IMPL (UL(0x1) << ID_AA64ISAR3_TLBIW_SHIFT) +#define ID_AA64ISAR3_PACM_SHIFT 12 +#define ID_AA64ISAR3_PACM_WIDTH 4 +#define ID_AA64ISAR3_PACM_MASK (UL(0xf) << ID_AA64ISAR3_PACM_SHIFT) +#define ID_AA64ISAR3_PACM_VAL(x) ((x) & ID_AA64ISAR3_PACM_MASK) +#define ID_AA64ISAR3_PACM_NONE (UL(0x0) << ID_AA64ISAR3_PACM_SHIFT) +#define ID_AA64ISAR3_PACM_TRIV (UL(0x1) << ID_AA64ISAR3_PACM_SHIFT) +#define ID_AA64ISAR3_PACM_FULL (UL(0x2) << ID_AA64ISAR3_PACM_SHIFT) + /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_EL1 MRS_REG(ID_AA64MMFR0_EL1) #define ID_AA64MMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1) @@ -1593,6 +1696,18 @@ #define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) #define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT) #define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT) +#define ID_AA64MMFR3_D128_SHIFT 32 +#define ID_AA64MMFR3_D128_WIDTH 4 +#define ID_AA64MMFR3_D128_MASK (UL(0xf) << ID_AA64MMFR3_D128_SHIFT) +#define ID_AA64MMFR3_D128_VAL(x) ((x) & ID_AA64MMFR3_D128_MASK) +#define ID_AA64MMFR3_D128_NONE (UL(0x0) << ID_AA64MMFR3_D128_SHIFT) +#define ID_AA64MMFR3_D128_IMPL (UL(0x1) << ID_AA64MMFR3_D128_SHIFT) +#define ID_AA64MMFR3_D128_v2_SHIFT 36 +#define ID_AA64MMFR3_D128_v2_WIDTH 4 +#define ID_AA64MMFR3_D128_v2_MASK (UL(0xf) << ID_AA64MMFR3_D128_v2_SHIFT) +#define ID_AA64MMFR3_D128_v2_VAL(x) ((x) & ID_AA64MMFR3_D128_v2_MASK) +#define ID_AA64MMFR3_D128_v2_NONE (UL(0x0) << ID_AA64MMFR3_D128_v2_SHIFT) +#define ID_AA64MMFR3_D128_v2_IMPL (UL(0x1) << ID_AA64MMFR3_D128_v2_SHIFT) #define ID_AA64MMFR3_SNERR_SHIFT 40 #define ID_AA64MMFR3_SNERR_WIDTH 4 #define ID_AA64MMFR3_SNERR_MASK (UL(0xf) << ID_AA64MMFR3_SNERR_SHIFT) @@ -1632,6 +1747,51 @@ #define ID_AA64MMFR4_EL1_CRn 0 #define ID_AA64MMFR4_EL1_CRm 7 #define ID_AA64MMFR4_EL1_op2 4 +#define ID_AA64MMFR4_EIESB_SHIFT 4 +#define ID_AA64MMFR4_EIESB_WIDTH 4 +#define ID_AA64MMFR4_EIESB_MASK (UL(0xf) << ID_AA64MMFR4_EIESB_SHIFT) +#define ID_AA64MMFR4_EIESB_VAL(x) ((x) & ID_AA64MMFR4_EIESB_MASK) +#define ID_AA64MMFR4_EIESB_NONE (UL(0x0) << ID_AA64MMFR4_EIESB_SHIFT) +#define ID_AA64MMFR4_EIESB_IMPL (UL(0x1) << ID_AA64MMFR4_EIESB_SHIFT) +#define ID_AA64MMFR4_EIESB_DF (UL(0xf) << ID_AA64MMFR4_EIESB_SHIFT) +#define ID_AA64MMFR4_EIESB_DF2 (UL(0x2) << ID_AA64MMFR4_EIESB_SHIFT) +#define ID_AA64MMFR4_ASID2_SHIFT 8 +#define ID_AA64MMFR4_ASID2_WIDTH 4 +#define ID_AA64MMFR4_ASID2_MASK (UL(0xf) << ID_AA64MMFR4_ASID2_SHIFT) +#define ID_AA64MMFR4_ASID2_VAL(x) ((x) & ID_AA64MMFR4_ASID2_MASK) +#define ID_AA64MMFR4_ASID2_NONE (UL(0x0) << ID_AA64MMFR4_ASID2_SHIFT) +#define ID_AA64MMFR4_ASID2_IMPL (UL(0x1) << ID_AA64MMFR4_ASID2_SHIFT) +#define ID_AA64MMFR4_HACDBS_SHIFT 12 +#define ID_AA64MMFR4_HACDBS_WIDTH 4 +#define ID_AA64MMFR4_HACDBS_MASK (UL(0xf) << ID_AA64MMFR4_HACDBS_SHIFT) +#define ID_AA64MMFR4_HACDBS_VAL(x) ((x) & ID_AA64MMFR4_HACDBS_MASK) +#define ID_AA64MMFR4_HACDBS_NONE (UL(0x0) << ID_AA64MMFR4_HACDBS_SHIFT) +#define ID_AA64MMFR4_HACDBS_IMPL (UL(0x1) << ID_AA64MMFR4_HACDBS_SHIFT) +#define ID_AA64MMFR4_FGWTE3_SHIFT 16 +#define ID_AA64MMFR4_FGWTE3_WIDTH 4 +#define ID_AA64MMFR4_FGWTE3_MASK (UL(0xf) << ID_AA64MMFR4_FGWTE3_SHIFT) +#define ID_AA64MMFR4_FGWTE3_VAL(x) ((x) & ID_AA64MMFR4_FGWTE3_MASK) +#define ID_AA64MMFR4_FGWTE3_NONE (UL(0x0) << ID_AA64MMFR4_FGWTE3_SHIFT) +#define ID_AA64MMFR4_FGWTE3_IMPL (UL(0x1) << ID_AA64MMFR4_FGWTE3_SHIFT) +#define ID_AA64MMFR4_NV_frac_SHIFT 20 +#define ID_AA64MMFR4_NV_frac_WIDTH 4 +#define ID_AA64MMFR4_NV_frac_MASK (UL(0xf) << ID_AA64MMFR4_NV_frac_SHIFT) +#define ID_AA64MMFR4_NV_frac_VAL(x) ((x) & ID_AA64MMFR4_NV_frac_MASK) +#define ID_AA64MMFR4_NV_frac_NONE (UL(0x0) << ID_AA64MMFR4_NV_frac_SHIFT) +#define ID_AA64MMFR4_NV_frac_IMPL (UL(0x1) << ID_AA64MMFR4_NV_frac_SHIFT) +#define ID_AA64MMFR4_E2H0_SHIFT 24 +#define ID_AA64MMFR4_E2H0_WIDTH 4 +#define ID_AA64MMFR4_E2H0_MASK (UL(0xf) << ID_AA64MMFR4_E2H0_SHIFT) +#define ID_AA64MMFR4_E2H0_VAL(x) ((x) & ID_AA64MMFR4_E2H0_MASK) +#define ID_AA64MMFR4_E2H0_IMPL (UL(0x0) << ID_AA64MMFR4_E2H0_SHIFT) +#define ID_AA64MMFR4_E2H0_NONE_NV1 (UL(0xe) << ID_AA64MMFR4_E2H0_SHIFT) +#define ID_AA64MMFR4_E2H0_NONE (UL(0xf) << ID_AA64MMFR4_E2H0_SHIFT) +#define ID_AA64MMFR4_E3DSE_SHIFT 36 +#define ID_AA64MMFR4_E3DSE_WIDTH 4 +#define ID_AA64MMFR4_E3DSE_MASK (UL(0xf) << ID_AA64MMFR4_E3DSE_SHIFT) +#define ID_AA64MMFR4_E3DSE_VAL(x) ((x) & ID_AA64MMFR4_E3DSE_MASK) +#define ID_AA64MMFR4_E3DSE_NONE (UL(0x0) << ID_AA64MMFR4_E3DSE_SHIFT) +#define ID_AA64MMFR4_E3DSE_IMPL (UL(0x1) << ID_AA64MMFR4_E3DSE_SHIFT) /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) @@ -1822,6 +1982,12 @@ #define ID_AA64PFR1_MTE_frac_VAL(x) ((x) & ID_AA64PFR1_MTE_frac_MASK) #define ID_AA64PFR1_MTE_frac_IMPL (UL(0x0) << ID_AA64PFR1_MTE_frac_SHIFT) #define ID_AA64PFR1_MTE_frac_NONE (UL(0xf) << ID_AA64PFR1_MTE_frac_SHIFT) +#define ID_AA64PFR1_GCS_SHIFT 44 +#define ID_AA64PFR1_GCS_WIDTH 4 +#define ID_AA64PFR1_GCS_MASK (UL(0xf) << ID_AA64PFR1_GCS_SHIFT) +#define ID_AA64PFR1_GCS_VAL(x) ((x) & ID_AA64PFR1_GCS_MASK) +#define ID_AA64PFR1_GCS_NONE (UL(0x0) << ID_AA64PFR1_GCS_SHIFT) +#define ID_AA64PFR1_GCS_IMPL (UL(0x1) << ID_AA64PFR1_GCS_SHIFT) #define ID_AA64PFR1_THE_SHIFT 48 #define ID_AA64PFR1_THE_WIDTH 4 #define ID_AA64PFR1_THE_MASK (UL(0xf) << ID_AA64PFR1_THE_SHIFT) @@ -1855,6 +2021,33 @@ #define ID_AA64PFR2_EL1_CRn 0 #define ID_AA64PFR2_EL1_CRm 4 #define ID_AA64PFR2_EL1_op2 2 +#define ID_AA64PFR2_MTEPERM_SHIFT 0 +#define ID_AA64PFR2_MTEPERM_WIDTH 4 +#define ID_AA64PFR2_MTEPERM_MASK (UL(0xf) << ID_AA64PFR2_MTEPERM_SHIFT) +#define ID_AA64PFR2_MTEPERM_VAL(x) ((x) & ID_AA64PFR2_MTEPERM_MASK) +#define ID_AA64PFR2_MTEPERM_NONE (UL(0x0) << ID_AA64PFR2_MTEPERM_SHIFT) +#define ID_AA64PFR2_MTEPERM_IMPL (UL(0x1) << ID_AA64PFR2_MTEPERM_SHIFT) +#define ID_AA64PFR2_MTESTOREONLY_SHIFT 4 +#define ID_AA64PFR2_MTESTOREONLY_WIDTH 4 +#define ID_AA64PFR2_MTESTOREONLY_MASK \ + (UL(0xf) << ID_AA64PFR2_MTESTOREONLY_SHIFT) +#define ID_AA64PFR2_MTESTOREONLY_VAL(x) ((x) & ID_AA64PFR2_MTESTOREONLY_MASK) +#define ID_AA64PFR2_MTESTOREONLY_NONE \ + (UL(0x0) << ID_AA64PFR2_MTESTOREONLY_SHIFT) +#define ID_AA64PFR2_MTESTOREONLY_IMPL \ + (UL(0x1) << ID_AA64PFR2_MTESTOREONLY_SHIFT) +#define ID_AA64PFR2_MTEFAR_SHIFT 8 +#define ID_AA64PFR2_MTEFAR_WIDTH 4 +#define ID_AA64PFR2_MTEFAR_MASK (UL(0xf) << ID_AA64PFR2_MTEFAR_SHIFT) +#define ID_AA64PFR2_MTEFAR_VAL(x) ((x) & ID_AA64PFR2_MTEFAR_MASK) +#define ID_AA64PFR2_MTEFAR_NONE (UL(0x0) << ID_AA64PFR2_MTEFAR_SHIFT) +#define ID_AA64PFR2_MTEFAR_IMPL (UL(0x1) << ID_AA64PFR2_MTEFAR_SHIFT) +#define ID_AA64PFR2_FPMR_SHIFT 0 +#define ID_AA64PFR2_FPMR_WIDTH 4 +#define ID_AA64PFR2_FPMR_MASK (UL(0xf) << ID_AA64PFR2_FPMR_SHIFT) +#define ID_AA64PFR2_FPMR_VAL(x) ((x) & ID_AA64PFR2_FPMR_MASK) +#define ID_AA64PFR2_FPMR_NONE (UL(0x0) << ID_AA64PFR2_FPMR_SHIFT) +#define ID_AA64PFR2_FPMR_IMPL (UL(0x1) << ID_AA64PFR2_FPMR_SHIFT) /* ID_AA64ZFR0_EL1 */ #define ID_AA64ZFR0_EL1 MRS_REG(ID_AA64ZFR0_EL1) @@ -1878,6 +2071,12 @@ #define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT) #define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT) +#define ID_AA64ZFR0_EltPerm_SHIFT 12 +#define ID_AA64ZFR0_EltPerm_WIDTH 4 +#define ID_AA64ZFR0_EltPerm_MASK (UL(0xf) << ID_AA64ZFR0_EltPerm_SHIFT) +#define ID_AA64ZFR0_EltPerm_VAL(x) ((x) & ID_AA64ZFR0_EltPerm_MASK) +#define ID_AA64ZFR0_EltPerm_NONE (UL(0x0) << ID_AA64ZFR0_EltPerm_SHIFT) +#define ID_AA64ZFR0_EltPerm_IMPL (UL(0x1) << ID_AA64ZFR0_EltPerm_SHIFT) #define ID_AA64ZFR0_BitPerm_SHIFT 16 #define ID_AA64ZFR0_BitPerm_WIDTH 4 #define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT) @@ -1890,7 +2089,14 @@ #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK) #define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT) #define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) -#define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT) +#define ID_AA64ZFR0_BF16_EBF (UL(0x2) << ID_AA64ZFR0_BF16_SHIFT) +#define ID_AA64ZFR0_B16B16_SHIFT 24 +#define ID_AA64ZFR0_B16B16_WIDTH 4 +#define ID_AA64ZFR0_B16B16_MASK (UL(0xf) << ID_AA64ZFR0_B16B16_SHIFT) +#define ID_AA64ZFR0_B16B16_VAL(x) ((x) & ID_AA64ZFR0_B16B16_MASK) +#define ID_AA64ZFR0_B16B16_NONE (UL(0x0) << ID_AA64ZFR0_B16B16_SHIFT) +#define ID_AA64ZFR0_B16B16_BASE (UL(0x1) << ID_AA64ZFR0_B16B16_SHIFT) +#define ID_AA64ZFR0_B16B16_BFS (UL(0x2) << ID_AA64ZFR0_B16B16_SHIFT) #define ID_AA64ZFR0_SHA3_SHIFT 32 #define ID_AA64ZFR0_SHA3_WIDTH 4 #define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT) @@ -1922,6 +2128,148 @@ #define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT) #define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT) +/* ID_AA64SMFR0_EL1 */ +#define ID_AA64SMFR0_EL1 MRS_REG(ID_AA64SMFR0_EL1) +#define ID_AA64SMFR0_EL1_REG MRS_REG_ALT_NAME(ID_AA64SMFR0_EL1) +#define ID_AA64SMFR0_EL1_op0 2 +#define ID_AA64SMFR0_EL1_op1 0 +#define ID_AA64SMFR0_EL1_CRn 0 +#define ID_AA64SMFR0_EL1_CRm 4 +#define ID_AA64SMFR0_EL1_op2 5 +#define ID_AA64SMFR0_SMOP4_SHIFT 0 +#define ID_AA64SMFR0_SMOP4_WIDTH 4 +#define ID_AA64SMFR0_SMOP4_MASK (UL(0xf) << ID_AA64SMFR0_SMOP4_SHIFT) +#define ID_AA64SMFR0_SMOP4_VAL(x) ((x) & ID_AA64SMFR0_SMOP4_MASK) +#define ID_AA64SMFR0_SMOP4_NONE (UL(0x0) << ID_AA64SMFR0_SMOP4_SHIFT) +#define ID_AA64SMFR0_SMOP4_IMPL (UL(0x1) << ID_AA64SMFR0_SMOP4_SHIFT) +#define ID_AA64SMFR0_STMOP_SHIFT 16 +#define ID_AA64SMFR0_STMOP_WIDTH 4 +#define ID_AA64SMFR0_STMOP_MASK (UL(0xf) << ID_AA64SMFR0_STMOP_SHIFT) +#define ID_AA64SMFR0_STMOP_VAL(x) ((x) & ID_AA64SMFR0_STMOP_MASK) +#define ID_AA64SMFR0_STMOP_NONE (UL(0x0) << ID_AA64SMFR0_STMOP_SHIFT) +#define ID_AA64SMFR0_STMOP_IMPL (UL(0x1) << ID_AA64SMFR0_STMOP_SHIFT) +#define ID_AA64SMFR0_SFEXPA_SHIFT 23 +#define ID_AA64SMFR0_SFEXPA_WIDTH 1 +#define ID_AA64SMFR0_SFEXPA_MASK (UL(0x1) << ID_AA64SMFR0_SFEXPA_SHIFT) +#define ID_AA64SMFR0_SFEXPA_VAL(x) ((x) & ID_AA64SMFR0_SFEXPA_MASK) +#define ID_AA64SMFR0_SFEXPA_NONE (UL(0x0) << ID_AA64SMFR0_SFEXPA_SHIFT) +#define ID_AA64SMFR0_SFEXPA_IMPL (UL(0x1) << ID_AA64SMFR0_SFEXPA_SHIFT) +#define ID_AA64SMFR0_SBitPerm_SHIFT 25 +#define ID_AA64SMFR0_SBitPerm_WIDTH 1 +#define ID_AA64SMFR0_SBitPerm_MASK (UL(0x1) << ID_AA64SMFR0_SBitPerm_SHIFT) +#define ID_AA64SMFR0_SBitPerm_VAL(x)((x) & ID_AA64SMFR0_SBitPerm_MASK) +#define ID_AA64SMFR0_SBitPerm_NONE (UL(0x0) << ID_AA64SMFR0_SBitPerm_SHIFT) +#define ID_AA64SMFR0_SBitPerm_IMPL (UL(0x1) << ID_AA64SMFR0_SBitPerm_SHIFT) +#define ID_AA64SMFR0_SF8DP2_SHIFT 28 +#define ID_AA64SMFR0_SF8DP2_WIDTH 1 +#define ID_AA64SMFR0_SF8DP2_MASK (UL(0x1) << ID_AA64SMFR0_SF8DP2_SHIFT) +#define ID_AA64SMFR0_SF8DP2_VAL(x) ((x) & ID_AA64SMFR0_SF8DP2_MASK) +#define ID_AA64SMFR0_SF8DP2_NONE (UL(0x0) << ID_AA64SMFR0_SF8DP2_SHIFT) +#define ID_AA64SMFR0_SF8DP2_IMPL (UL(0x1) << ID_AA64SMFR0_SF8DP2_SHIFT) +#define ID_AA64SMFR0_SF8DP4_SHIFT 29 +#define ID_AA64SMFR0_SF8DP4_WIDTH 1 +#define ID_AA64SMFR0_SF8DP4_MASK (UL(0x1) << ID_AA64SMFR0_SF8DP4_SHIFT) +#define ID_AA64SMFR0_SF8DP4_VAL(x) ((x) & ID_AA64SMFR0_SF8DP4_MASK) +#define ID_AA64SMFR0_SF8DP4_NONE (UL(0x0) << ID_AA64SMFR0_SF8DP4_SHIFT) +#define ID_AA64SMFR0_SF8DP4_IMPL (UL(0x1) << ID_AA64SMFR0_SF8DP4_SHIFT) +#define ID_AA64SMFR0_SF8FMA_SHIFT 30 +#define ID_AA64SMFR0_SF8FMA_WIDTH 1 +#define ID_AA64SMFR0_SF8FMA_MASK (UL(0x1) << ID_AA64SMFR0_SF8FMA_SHIFT) +#define ID_AA64SMFR0_SF8FMA_VAL(x) ((x) & ID_AA64SMFR0_SF8FMA_MASK) +#define ID_AA64SMFR0_SF8FMA_NONE (UL(0x0) << ID_AA64SMFR0_SF8FMA_SHIFT) +#define ID_AA64SMFR0_SF8FMA_IMPL (UL(0x1) << ID_AA64SMFR0_SF8FMA_SHIFT) +#define ID_AA64SMFR0_F32F32_SHIFT 32 +#define ID_AA64SMFR0_F32F32_WIDTH 1 +#define ID_AA64SMFR0_F32F32_MASK (UL(0x1) << ID_AA64SMFR0_F32F32_SHIFT) +#define ID_AA64SMFR0_F32F32_VAL(x) ((x) & ID_AA64SMFR0_F32F32_MASK) +#define ID_AA64SMFR0_F32F32_NONE (UL(0x0) << ID_AA64SMFR0_F32F32_SHIFT) +#define ID_AA64SMFR0_F32F32_IMPL (UL(0x1) << ID_AA64SMFR0_F32F32_SHIFT) +#define ID_AA64SMFR0_BI32I32_SHIFT 33 +#define ID_AA64SMFR0_BI32I32_WIDTH 1 +#define ID_AA64SMFR0_BI32I32_MASK (UL(0x1) << ID_AA64SMFR0_BI32I32_SHIFT) +#define ID_AA64SMFR0_BI32I32_VAL(x) ((x) & ID_AA64SMFR0_BI32I32_WIDTH) +#define ID_AA64SMFR0_BI32I32_NONE (UL(0x0) << ID_AA64SMFR0_BI32I32_SHIFT) +#define ID_AA64SMFR0_BI32I32_IMPL (UL(0x1) << ID_AA64SMFR0_BI32I32_SHIFT) +#define ID_AA64SMFR0_B16F32_SHIFT 34 +#define ID_AA64SMFR0_B16F32_WIDTH 1 +#define ID_AA64SMFR0_B16F32_MASK (UL(0x1) << ID_AA64SMFR0_B16F32_SHIFT) +#define ID_AA64SMFR0_B16F32_VAL(x) ((x) & ID_AA64SMFR0_B16F32_MASK) +#define ID_AA64SMFR0_B16F32_NONE (UL(0x0) << ID_AA64SMFR0_B16F32_SHIFT) +#define ID_AA64SMFR0_B16F32_IMPL (UL(0x1) << ID_AA64SMFR0_B16F32_SHIFT) +#define ID_AA64SMFR0_F16F32_SHIFT 35 +#define ID_AA64SMFR0_F16F32_WIDTH 1 +#define ID_AA64SMFR0_F16F32_MASK (UL(0x1) << ID_AA64SMFR0_F16F32_SHIFT) +#define ID_AA64SMFR0_F16F32_VAL(x) ((x) & ID_AA64SMFR0_F16F32_MASK) +#define ID_AA64SMFR0_F16F32_NONE (UL(0x0) << ID_AA64SMFR0_F16F32_SHIFT) +#define ID_AA64SMFR0_F16F32_IMPL (UL(0x1) << ID_AA64SMFR0_F16F32_SHIFT) +#define ID_AA64SMFR0_I8I32_SHIFT 36 +#define ID_AA64SMFR0_I8I32_WIDTH 4 +#define ID_AA64SMFR0_I8I32_MASK (UL(0xf) << ID_AA64SMFR0_I8I32_SHIFT) +#define ID_AA64SMFR0_I8I32_VAL(x) ((x) & ID_AA64SMFR0_I8I32_MASK) +#define ID_AA64SMFR0_I8I32_NONE (UL(0x0) << ID_AA64SMFR0_I8I32_SHIFT) +#define ID_AA64SMFR0_I8I32_IMPL (UL(0xf) << ID_AA64SMFR0_I8I32_SHIFT) +#define ID_AA64SMFR0_F8F32_SHIFT 40 +#define ID_AA64SMFR0_F8F32_WIDTH 1 +#define ID_AA64SMFR0_F8F32_MASK (UL(0x1) << ID_AA64SMFR0_F8F32_SHIFT) +#define ID_AA64SMFR0_F8F32_VAL(x) ((x) & ID_AA64SMFR0_F8F32_MASK) +#define ID_AA64SMFR0_F8F32_NONE (UL(0x0) << ID_AA64SMFR0_F8F32_SHIFT) +#define ID_AA64SMFR0_F8F32_IMPL (UL(0x1) << ID_AA64SMFR0_F8F32_SHIFT) +#define ID_AA64SMFR0_F8F16_SHIFT 41 +#define ID_AA64SMFR0_F8F16_WIDTH 1 +#define ID_AA64SMFR0_F8F16_MASK (UL(0x1) << ID_AA64SMFR0_F8F16_SHIFT) +#define ID_AA64SMFR0_F8F16_VAL(x) ((x) & ID_AA64SMFR0_F8F16_WIDTH) +#define ID_AA64SMFR0_F8F16_NONE (UL(0x0) << ID_AA64SMFR0_F8F16_SHIFT) +#define ID_AA64SMFR0_F8F16_IMPL (UL(0x1) << ID_AA64SMFR0_F8F16_SHIFT) +#define ID_AA64SMFR0_F16F16_SHIFT 42 +#define ID_AA64SMFR0_F16F16_WIDTH 1 +#define ID_AA64SMFR0_F16F16_MASK (UL(0x1) << ID_AA64SMFR0_F16F16_SHIFT) +#define ID_AA64SMFR0_F16F16_VAL(x) ((x) & ID_AA64SMFR0_F16F16_MASK) +#define ID_AA64SMFR0_F16F16_NONE (UL(0x0) << ID_AA64SMFR0_F16F16_SHIFT) +#define ID_AA64SMFR0_F16F16_IMPL (UL(0x1) << ID_AA64SMFR0_F16F16_SHIFT) +#define ID_AA64SMFR0_B16B16_SHIFT 43 +#define ID_AA64SMFR0_B16B16_WIDTH 1 +#define ID_AA64SMFR0_B16B16_MASK (UL(0x1) << ID_AA64SMFR0_B16B16_SHIFT) +#define ID_AA64SMFR0_B16B16_VAL(x) ((x) & ID_AA64SMFR0_B16B16_MASK) +#define ID_AA64SMFR0_B16B16_NONE (UL(0x0) << ID_AA64SMFR0_B16B16_SHIFT) +#define ID_AA64SMFR0_B16B16_IMPL (UL(0x1) << ID_AA64SMFR0_B16B16_SHIFT) +#define ID_AA64SMFR0_I16I32_SHIFT 44 +#define ID_AA64SMFR0_I16I32_WIDTH 4 +#define ID_AA64SMFR0_I16I32_MASK (UL(0xf) << ID_AA64SMFR0_I16I32_SHIFT) +#define ID_AA64SMFR0_I16I32_VAL(x) ((x) & ID_AA64SMFR0_I16I32_MASK) +#define ID_AA64SMFR0_I16I32_NONE (UL(0x0) << ID_AA64SMFR0_I16I32_SHIFT) +#define ID_AA64SMFR0_I16I32_IMPL (UL(0xf) << ID_AA64SMFR0_I16I32_SHIFT) +#define ID_AA64SMFR0_F64F64_SHIFT 48 +#define ID_AA64SMFR0_F64F64_WIDTH 1 +#define ID_AA64SMFR0_F64F64_MASK (UL(0x1) << ID_AA64SMFR0_F64F64_SHIFT) +#define ID_AA64SMFR0_F64F64_VAL(x) ((x) & ID_AA64SMFR0_F64F64_MASK) +#define ID_AA64SMFR0_F64F64_NONE (UL(0x0) << ID_AA64SMFR0_F64F64_SHIFT) +#define ID_AA64SMFR0_F64F64_IMPL (UL(0x1) << ID_AA64SMFR0_F64F64_SHIFT) +#define ID_AA64SMFR0_I16I64_SHIFT 52 +#define ID_AA64SMFR0_I16I64_WIDTH 4 +#define ID_AA64SMFR0_I16I64_MASK (UL(0xf) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_I16I64_VAL(x) ((x) & ID_AA64SMFR0_I16I64_MASK) +#define ID_AA64SMFR0_I16I64_NONE (UL(0x0) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_I16I64_IMPL (UL(0xf) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_SMEver_SHIFT 56 +#define ID_AA64SMFR0_SMEver_WIDTH 4 +#define ID_AA64SMFR0_SMEver_MASK (UL(0xf) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_SMEver_VAL(x) ((x) & ID_AA64SMFR0_I16I64_MASK) +#define ID_AA64SMFR0_SMEver_BASE (UL(0x0) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_SMEver_2_0 (UL(0x1) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_SMEver_2_1 (UL(0x2) << ID_AA64SMFR0_I16I64_SHIFT) +#define ID_AA64SMFR0_LUTv2_SHIFT 60 +#define ID_AA64SMFR0_LUTv2_WIDTH 1 +#define ID_AA64SMFR0_LUTv2_MASK (UL(0x1) << ID_AA64SMFR0_LUTv2_SHIFT) +#define ID_AA64SMFR0_LUTv2_VAL(x) ((x) & ID_AA64SMFR0_LUTv2_MASK) +#define ID_AA64SMFR0_LUTv2_NONE (UL(0x0) << ID_AA64SMFR0_LUTv2_SHIFT) +#define ID_AA64SMFR0_LUTv2_IMPL (UL(0x1) << ID_AA64SMFR0_LUTv2_SHIFT) +#define ID_AA64SMFR0_FA64_SHIFT 63 +#define ID_AA64SMFR0_FA64_WIDTH 1 +#define ID_AA64SMFR0_FA64_MASK (UL(0x1) << ID_AA64SMFR0_FA64_SHIFT) +#define ID_AA64SMFR0_FA64_VAL(x) ((x) & ID_AA64SMFR0_FA64_MASK) +#define ID_AA64SMFR0_FA64_NONE (UL(0x0) << ID_AA64SMFR0_FA64_SHIFT) +#define ID_AA64SMFR0_FA64_IMPL (UL(0x1) << ID_AA64SMFR0_FA64_SHIFT) + /* ID_ISAR5_EL1 */ #define ID_ISAR5_EL1 MRS_REG(ID_ISAR5_EL1) #define ID_ISAR5_EL1_op0 0x3