Index: sys/riscv/eswin/eswin_clk.c =================================================================== --- /dev/null +++ sys/riscv/eswin/eswin_clk.c @@ -0,0 +1,292 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Ruslan Bukin + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "clkdev_if.h" +#include "syscon_if.h" + +#include + +struct eswin_clk_softc { + device_t dev; + struct mtx mtx; + struct clkdom *clkdom; + struct syscon *syscon; +}; + +#define ECLK_LOCK(sc) mtx_lock(&(sc)->mtx) +#define ECLK_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define ECLK_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); +#define ECLK_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); + +#define ECLK_READ(_sc, _reg) \ + SYSCON_READ_4(sc->syscon, (_reg)) +#define ECLK_WRITE(_sc, _reg, _val) \ + SYSCON_WRITE_4(sc->syscon, (_reg), (_val)) + +struct eswin_clk_gate_def { + uint32_t id; + const char *name; + const char *parent_name; + uint32_t reg; + uint32_t bit; +}; + +#define GATE(_id, _name, _parent_name, _base, _bit) \ +{ \ + .id = (_id), \ + .name = (_name), \ + .parent_name = (_parent_name), \ + .reg = (_base), \ + .bit = (_bit), \ +} + +#define GATE_END GATE(0, NULL, NULL, 0, 0) + +struct eswin_clk_config { + struct eswin_clk_gate_def *gate_clks; +}; + +/* Eswin clock numbers. */ +#define EIC7700_CLK_PCIET_ACLK 562 +#define EIC7700_CLK_PCIET_CFG_CLK 563 +#define EIC7700_CLK_PCIET_CR_CLK 564 +#define EIC7700_CLK_PCIET_AUX_CLK 565 + +/* Eswin clock registers. */ +#define PCIE_ACLK_CTRL 0x170 +#define PCIE_CFG_CTRL 0x174 + +static struct eswin_clk_gate_def eic7700_gate_clks[] = { + GATE(EIC7700_CLK_PCIET_CFG_CLK, "pcie_cfg", "hfclk", + PCIE_CFG_CTRL, 31), + GATE(EIC7700_CLK_PCIET_AUX_CLK, "pcie_aux_clk", "hfclk", + PCIE_CFG_CTRL, 1), + GATE(EIC7700_CLK_PCIET_CR_CLK, "pcie_cr", "hfclk", + PCIE_CFG_CTRL, 0), + GATE_END +}; + +struct eswin_clk_config eswin_eic7700_clk_config = { + .gate_clks = eic7700_gate_clks, +}; + +static struct ofw_compat_data compat_data[] = { + { "eswin,eic7700-clock", (uintptr_t)&eswin_eic7700_clk_config }, + { NULL, 0 }, +}; + +static int +eswin_clk_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Eswin Clock subsystem"); + + return (BUS_PROBE_DEFAULT); +} + +static int +eswin_clk_attach(device_t dev) +{ + struct clk_gate_def clkdef_gate; + struct clknode_init_def clkdef; + struct eswin_clk_gate_def *gate_clk; + struct eswin_clk_config *cfg; + struct eswin_clk_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + + cfg = (struct eswin_clk_config *)ofw_bus_search_compatible(dev, + compat_data)->ocd_data; + + mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF); + + error = syscon_get_by_ofw_node(dev, OF_parent(ofw_bus_get_node(dev)), + &sc->syscon); + if (error != 0) { + device_printf(dev, "Couldn't get syscon handle of parent\n"); + return (error); + } + + bzero(&clkdef, sizeof(clkdef)); + clkdef.parent_names = malloc(sizeof(char *), M_OFWPROP, M_WAITOK); + clkdef.parent_names[0] = "hfclk"; + clkdef.parent_cnt = 1; + + sc->clkdom = clkdom_create(dev); + if (sc->clkdom == NULL) { + device_printf(dev, "Couldn't create clock domain\n"); + goto fail; + } + + if (cfg->gate_clks != NULL) { + bzero(&clkdef_gate, sizeof(clkdef_gate)); + for (gate_clk = cfg->gate_clks; gate_clk->name; gate_clk++) { + clkdef_gate.clkdef.id = gate_clk->id; + clkdef_gate.clkdef.name = gate_clk->name; + clkdef_gate.clkdef.parent_names =&gate_clk->parent_name; + clkdef_gate.clkdef.parent_cnt = 1; + clkdef_gate.offset = gate_clk->reg; + clkdef_gate.shift = gate_clk->bit; + clkdef_gate.mask = 1; + clkdef_gate.on_value = 1; + clkdef_gate.off_value = 0; + error = clknode_gate_register(sc->clkdom, + &clkdef_gate); + if (error != 0) { + device_printf(dev, + "Couldn't create gated clock %s: %d\n", + gate_clk->name, error); + goto fail; + } + } + } + + error = clkdom_finit(sc->clkdom); + if (error) + panic("Couldn't finalise clock domain"); + + return (0); + +fail: + mtx_destroy(&sc->mtx); + return (error); +} + +static int +eswin_clk_write_4(device_t dev, bus_addr_t addr, uint32_t val) +{ + struct eswin_clk_softc *sc; + + sc = device_get_softc(dev); + + ECLK_WRITE(sc, addr, val); + + return (0); +} + +static int +eswin_clk_read_4(device_t dev, bus_addr_t addr, uint32_t *val) +{ + struct eswin_clk_softc *sc; + + sc = device_get_softc(dev); + + *val = ECLK_READ(sc, addr); + + return (0); +} + +static int +eswin_clk_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) +{ + struct eswin_clk_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + + reg = ECLK_READ(sc, addr); + reg &= ~clr; + reg |= set; + ECLK_WRITE(sc, addr, reg); + + return (0); +} + +static void +eswin_clk_device_lock(device_t dev) +{ + struct eswin_clk_softc *sc; + + sc = device_get_softc(dev); + + ECLK_LOCK(sc); +} + +static void +eswin_clk_device_unlock(device_t dev) +{ + struct eswin_clk_softc *sc; + + sc = device_get_softc(dev); + + ECLK_UNLOCK(sc); +} + +static device_method_t eswin_clk_methods[] = { + DEVMETHOD(device_probe, eswin_clk_probe), + DEVMETHOD(device_attach, eswin_clk_attach), + + /* clkdev interface */ + DEVMETHOD(clkdev_write_4, eswin_clk_write_4), + DEVMETHOD(clkdev_read_4, eswin_clk_read_4), + DEVMETHOD(clkdev_modify_4, eswin_clk_modify_4), + DEVMETHOD(clkdev_device_lock, eswin_clk_device_lock), + DEVMETHOD(clkdev_device_unlock, eswin_clk_device_unlock), + + DEVMETHOD_END +}; + +static driver_t eswin_clk_driver = { + "eswin_clk", + eswin_clk_methods, + sizeof(struct eswin_clk_softc) +}; + +/* + * hfclk appears later in the device tree than eswin_clk, so we must + * attach late. + */ +EARLY_DRIVER_MODULE(eswin_clk, simplebus, eswin_clk_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_LATE);