Index: sys/riscv/conf/std.eswin =================================================================== --- sys/riscv/conf/std.eswin +++ sys/riscv/conf/std.eswin @@ -2,4 +2,6 @@ # Eswin SoC support # +device pci_eic + files "../eswin/files.eswin" Index: sys/riscv/eswin/eswin_pcie.c =================================================================== --- /dev/null +++ sys/riscv/eswin/eswin_pcie.c @@ -0,0 +1,430 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Ruslan Bukin + * + * This software was developed by the University of Cambridge Computer + * Laboratory (Department of Computer Science and Technology) under Innovate + * UK project 105694, "Digital Security by Design (DSbD) Technology Platform + * Prototype". + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* Eswin EIC7700 (Synopsys DesignWare) PCIe driver. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcib_if.h" +#include "pci_dw_if.h" + +#define PCIEMGMT_APP_LTSSM_ENABLE (1 << 5) +#define PCIEMGMT_LINKUP_STATE_VALIDATE ((0x11 << 2) | 0x3) +#define PCIEMGMT_LINKUP_STATE_MASK 0xff + +#define PCIE_STATUS0 0x100 + +#define PCIE_PM_SEL_AUX_CLK (1 << 16) + +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define MAX_PAYLOAD_SIZE 512 + +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) +#define MAX_READ_REQ_SIZE 512 + +#define PCI_EXP_DEVCTL 8 /* Device Control */ +#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ +#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ + +#define RD4(sc, reg) bus_read_4(sc->mgmt_res, (reg)) +#define WR4(sc, reg, val) bus_write_4(sc->mgmt_res, (reg), (val)) + +struct pci_eic_softc { + struct pci_dw_softc dw_sc; + device_t dev; + phandle_t node; + struct resource *mgmt_res; + clk_t pcie_aux_clk; + hwreset_t pcie_cfg; + hwreset_t pcie_powerup; + hwreset_t pcie_pwren; +}; + +/* Compatible devices. */ +static struct ofw_compat_data compat_data[] = { + {"eswin,eic7700-pcie", 1}, + {NULL, 0}, +}; + +static void +pci_eic_dbi_write_enable(struct pci_eic_softc *sc, bool enable) +{ + uint32_t reg; + + reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1); + if (enable) + reg |= DBI_RO_WR_EN; + else + reg &= ~DBI_RO_WR_EN; + pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg); +} + +static int +eswin_size_to_payload(int size) +{ + /* + * dwc supports 2^(val+7) payload size, where val is 0..5 (default 1). + * So if input size is not 2^order alignment or less than 2^7 or bigger + * than 2^12, just set to default size 2^(1+7). + */ + if (!powerof2(size) || size < 128 || size > 4096) + return (1); + + return (fls(size) - 8); +} + +static void +set_max_payload(struct pci_eic_softc *sc) +{ + uint32_t reg; + int size; + + size = eswin_size_to_payload(MAX_PAYLOAD_SIZE); + + pci_eic_dbi_write_enable(sc, true); + reg = pci_dw_dbi_rd4(sc->dev, PCI_EXP_DEVCTL + 0x70); + reg &= ~PCI_EXP_DEVCTL_PAYLOAD; + reg |= PCIE_CAP_MAX_PAYLOAD_SIZE(size); + pci_dw_dbi_wr4(sc->dev, PCI_EXP_DEVCTL + 0x70, reg); + pci_eic_dbi_write_enable(sc, false); +} + +static void +set_max_rd_req_size(struct pci_eic_softc *sc) +{ + uint32_t reg; + int size; + + size = eswin_size_to_payload(MAX_PAYLOAD_SIZE); + + pci_eic_dbi_write_enable(sc, true); + reg = pci_dw_dbi_rd4(sc->dev, PCI_EXP_DEVCTL + 0x70); + reg &= ~PCI_EXP_DEVCTL_READRQ; + reg |= PCIE_CAP_MAX_READ_REQ_SIZE(size); + pci_dw_dbi_wr4(sc->dev, PCI_EXP_DEVCTL + 0x70, reg); + pci_eic_dbi_write_enable(sc, false); +} + +static int +pci_eic_phy_init(struct pci_eic_softc *sc) +{ + uint32_t reg; + int error; + + /* Enable the aux clock */ + error = clk_enable(sc->pcie_aux_clk); + if (error != 0) { + device_printf(sc->dev, "Cannot enable aux clock: %d\n", error); + return (error); + } + + /* Deassert the cfg reset */ + error = hwreset_deassert(sc->pcie_cfg); + if (error != 0) { + device_printf(sc->dev, "Cannot deassert cfg reset: %d\n", + error); + return (error); + } + + /* Deassert the powerup reset */ + error = hwreset_deassert(sc->pcie_powerup); + if (error != 0) { + device_printf(sc->dev, "Cannot deassert powerup reset: %d\n", + error); + return (error); + } + + /* Set device type: Root-Complex. */ + reg = RD4(sc, 0x00); + reg &= ~(0xf << 0); + reg |= (1 << 2); + WR4(sc, 0x00, reg); + + /* Assert the perst reset. */ + error = hwreset_assert(sc->pcie_pwren); + if (error != 0) { + device_printf(sc->dev, "Cannot assert pwren reset: %d\n", + error); + return (error); + } + + DELAY(1000); + + /* Deassert the perst reset. */ + error = hwreset_deassert(sc->pcie_pwren); + if (error != 0) { + device_printf(sc->dev, "Cannot deassert pwren reset: %d\n", + error); + return (error); + } + + /* app_hold_phy_rst */ + reg = RD4(sc, 0x00); + reg &= ~(1 << 6); + WR4(sc, 0x00, reg); + + /* Wait pm_sel_aux_clk to clear. */ + do { + reg = RD4(sc, PCIE_STATUS0); + if (!(reg & PCIE_PM_SEL_AUX_CLK)) + break; + DELAY(1000); + } while (1); + + return (0); +} + +static int +pci_eic_get_link(device_t dev, bool *status) +{ + struct pci_eic_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + + reg = RD4(sc, PCIE_STATUS0); + if ((reg & PCIEMGMT_LINKUP_STATE_MASK) == + PCIEMGMT_LINKUP_STATE_VALIDATE) { + *status = true; + return (0); + } + + *status = false; + + return (0); +} + +static void +pcie_eic_wait_link_up(struct pci_eic_softc *sc) +{ + int timeout; + bool status; + + timeout = 500; + + do { + pci_eic_get_link(sc->dev, &status); + if (status == true) + break; + DELAY(1000); + } while (timeout--); + + if (status == true) + device_printf(sc->dev, "link is UP\n"); +} + +static void +pci_eic_init(struct pci_eic_softc *sc) +{ + uint32_t reg; + + pci_eic_dbi_write_enable(sc, true); + + /* Set device/vendor ID. */ + pci_dw_dbi_wr4(sc->dev, 0, 0x20301fe1); + + /* Gen-X 3 */ + pci_dw_dbi_wr4(sc->dev, 0xa0, 0x00010003); + + reg = pci_dw_dbi_rd4(sc->dev, 0x7c); + reg &= 0xfffffff0; + reg |= 0x3; /* Gen3 */ + pci_dw_dbi_wr4(sc->dev, 0x7c, reg); + + reg = pci_dw_dbi_rd4(sc->dev, 0x7c); + reg &= 0xfffffc0f; + reg |= 0x40; /* LaneX 4 */ + pci_dw_dbi_wr4(sc->dev, 0x7c, reg); + + /* Lane config */ + reg = pci_dw_dbi_rd4(sc->dev, 0x8c0); + reg &= 0xffffff80; + reg |= 0x44; /* 4 lane */ + pci_dw_dbi_wr4(sc->dev, 0x8c0, reg); + + set_max_payload(sc); + set_max_rd_req_size(sc); + + /* + * Config MSI-X table size to 0 in RC mode because our RC does not + * support MSI-X. + */ + reg = pci_dw_dbi_rd4(sc->dev, 0xb0); + reg &= ~(0x7ff << 16); + pci_dw_dbi_wr4(sc->dev, 0xb0, reg); + + /* Config support 32 msi vectors. */ + pci_dw_dbi_wr4(sc->dev, 0x50, 0x018a7005); + + /* Disable MSI-X capability. */ + reg = pci_dw_dbi_rd4(sc->dev, 0x70); + reg &= 0xffff00ff; + pci_dw_dbi_wr4(sc->dev, 0x70, reg); + + pci_eic_dbi_write_enable(sc, false); + + /* Start link */ + reg = RD4(sc, 0x00); + reg |= PCIEMGMT_APP_LTSSM_ENABLE; + WR4(sc, 0x00, reg); + + pcie_eic_wait_link_up(sc); +} + +static int +pci_eic_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Eswin EIC7700 PCIe Controller"); + + return (BUS_PROBE_DEFAULT); +} + +static int +pci_eic_attach(device_t dev) +{ + struct pci_eic_softc *sc; + phandle_t node; + int error; + int rid; + + sc = device_get_softc(dev); + node = ofw_bus_get_node(dev); + sc->dev = dev; + sc->node = node; + + rid = 0; + sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->dw_sc.dbi_res == NULL) { + device_printf(dev, "Cannot allocate DBI memory\n"); + error = ENXIO; + goto out; + } + + rid = 2; + sc->mgmt_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->mgmt_res == NULL) { + device_printf(dev, "Cannot allocate MGMT memory\n"); + error = ENXIO; + goto out; + } + + error = clk_get_by_ofw_name(dev, node, "pcie_aux_clk", + &sc->pcie_aux_clk); + if (error != 0) { + device_printf(dev, "Cannot get aux clock: %d\n", error); + goto out; + } + + error = hwreset_get_by_ofw_idx(dev, node, 0, &sc->pcie_cfg); + if (error != 0) { + device_printf(dev, "Cannot get cfg reset: %d\n", error); + goto out; + } + + error = hwreset_get_by_ofw_idx(dev, node, 1, &sc->pcie_powerup); + if (error != 0) { + device_printf(dev, "Cannot get powerup reset: %d\n", error); + goto out; + } + + error = hwreset_get_by_ofw_idx(dev, node, 2, &sc->pcie_pwren); + if (error != 0) { + device_printf(dev, "Cannot get pwren reset: %d\n", error); + goto out; + } + + error = pci_eic_phy_init(sc); + if (error) + goto out; + + pci_eic_init(sc); + + error = pci_dw_init(dev); + if (error != 0) + goto out; + + bus_delayed_attach_children(dev); + + return (0); + +out: + return (error); +} + +static device_method_t pci_eic_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, pci_eic_probe), + DEVMETHOD(device_attach, pci_eic_attach), + + /* pci_dw interface. */ + DEVMETHOD(pci_dw_get_link, pci_eic_get_link), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(pcib, pci_eic_driver, pci_eic_methods, + sizeof(struct pci_eic_softc), pci_dw_driver); +DRIVER_MODULE(pci_eic, simplebus, pci_eic_driver, NULL, NULL); Index: sys/riscv/eswin/files.eswin =================================================================== --- sys/riscv/eswin/files.eswin +++ sys/riscv/eswin/files.eswin @@ -1,2 +1,3 @@ riscv/sifive/sifive_ccache.c standard +riscv/eswin/eswin_pcie.c optional pci_eic pci fdt riscv/eswin/eswin_reset.c optional hwreset