Index: sys/riscv/sifive/sifive_ccache.c
===================================================================
--- /dev/null
+++ sys/riscv/sifive/sifive_ccache.c
@@ -0,0 +1,143 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2024 Ruslan Bukin <br@bsdpad.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#define	SIFIVE_CCACHE_CONFIG	0x000
+#define	 CCACHE_CONFIG_WAYS_S	8
+#define	 CCACHE_CONFIG_WAYS_M	(0xff << CCACHE_CONFIG_WAYS_S)
+#define	SIFIVE_CCACHE_WAYENABLE	0x008
+#define	SIFIVE_CCACHE_FLUSH64	0x200
+
+#define	SIFIVE_CCACHE_LINE_SIZE	64
+
+enum ccache_type {
+	CC_EIC7700 = 1,
+};
+
+static struct ofw_compat_data compat_data[] = {
+	{ "sifive,eic7700",	CC_EIC7700 },
+	{ NULL,				 0 }
+};
+
+static void *ccache_va = NULL;
+
+#define	CC_READ(offset)		\
+    *(volatile uint64_t *)((uintptr_t)ccache_va + (offset))
+#define	CC_WRITE(offset, value)	\
+    *(volatile uint64_t *)((uintptr_t)ccache_va + (offset)) = (value)
+
+/*
+ * Non-standard EIC7700 cache-flushing routine.
+ */
+static void
+ccache_flush_range(vm_offset_t start, size_t len)
+{
+	vm_offset_t paddr;
+	vm_offset_t sva;
+	vm_offset_t step;
+	uint64_t line;
+
+	if (ccache_va == 0 || len == 0)
+		return;
+
+	mb();
+
+	for (sva = start; len > 0;) {
+		paddr = pmap_kextract(sva);
+		step = min(PAGE_SIZE - (paddr & PAGE_MASK), len);
+		for (line = rounddown2(paddr, SIFIVE_CCACHE_LINE_SIZE);
+		    line < paddr + step;
+		    line += SIFIVE_CCACHE_LINE_SIZE)
+			CC_WRITE(SIFIVE_CCACHE_FLUSH64, line);
+		sva += step;
+		len -= step;
+	}
+
+	mb();
+}
+
+static void
+ccache_install_hooks(void)
+{
+	struct riscv_cache_ops eswin_ops;
+
+	eswin_ops.dcache_wbinv_range = ccache_flush_range;
+	eswin_ops.dcache_inv_range = ccache_flush_range;
+	eswin_ops.dcache_wb_range = ccache_flush_range;
+
+	riscv_cache_install_hooks(&eswin_ops, SIFIVE_CCACHE_LINE_SIZE);
+}
+
+static void
+ccache_init(const void *dummy __unused)
+{
+	struct ofw_compat_data *compat;
+	size_t config, ways;
+	phandle_t root_node;
+	phandle_t ccache_node;
+	vm_paddr_t pa;
+	u_long base;
+        u_long size;
+
+	if ((root_node = OF_finddevice("/")) == -1)
+		return;
+
+	ccache_node = 0;
+
+	compat = compat_data;
+	for (; compat->ocd_str != NULL; ++compat)
+		if ((ccache_node =
+		    ofw_bus_find_compatible(root_node, compat->ocd_str)) > 0)
+			break;
+	if (compat == NULL)
+		return;
+
+	if (fdt_regsize(ccache_node, &base, &size))
+		return;
+
+	ccache_va = (void *)kva_alloc(size);
+	pa = (vm_paddr_t)base;
+	pmap_kenter_device((vm_offset_t)ccache_va, size, pa);
+
+	/* Non-standard EIC7700 cache unit configuration. */
+	config = CC_READ(SIFIVE_CCACHE_CONFIG);
+	ways = (config & CCACHE_CONFIG_WAYS_M) >> CCACHE_CONFIG_WAYS_S;
+	CC_WRITE(SIFIVE_CCACHE_WAYENABLE, (ways - 1));
+
+	ccache_install_hooks();
+}
+
+SYSINIT(ccache, SI_SUB_CPU, SI_ORDER_FIRST, ccache_init, NULL);