diff --git a/sys/dev/acpica/acpi_cpu.c b/sys/dev/acpica/acpi_cpu.c
--- a/sys/dev/acpica/acpi_cpu.c
+++ b/sys/dev/acpica/acpi_cpu.c
@@ -131,6 +131,7 @@
 #define PIIX4_PCNTRL_BST_EN	(1<<10)
 
 #define	CST_FFH_VENDOR_INTEL	1
+#define	CST_FFH_VENDOR_AMD	2
 #define	CST_FFH_INTEL_CL_C1IO	1
 #define	CST_FFH_INTEL_CL_MWAIT	2
 #define	CST_FFH_MWAIT_HW_COORD	0x0001
@@ -855,7 +856,8 @@
 	    acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr);
 #if defined(__i386__) || defined(__amd64__)
 	    if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address,
-	      &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) {
+	      &accsize) == 0 &&
+		(vendor == CST_FFH_VENDOR_INTEL || vendor == CST_FFH_VENDOR_AMD)) {
 		if (class == CST_FFH_INTEL_CL_C1IO) {
 		    /* C1 I/O then Halt */
 		    cx_ptr->res_rid = sc->cpu_cx_count;
@@ -872,7 +874,9 @@
 			  "degrading to C1 Halt", (int)address);
 		    }
 		} else if (class == CST_FFH_INTEL_CL_MWAIT) {
-		    acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
+		    if (vendor == CST_FFH_VENDOR_INTEL ||
+			(vendor == CST_FFH_VENDOR_AMD && cpu_mon_mwait_edx != 0))
+		        acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
 		}
 	    }
 #endif
@@ -922,6 +926,7 @@
 	    acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type,
 		&cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE);
 	    if (cx_ptr->p_lvlx) {
+		cx_ptr->do_mwait = false;
 		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
 		     "acpi_cpu%d: Got C%d - %d latency\n",
 		     device_get_unit(sc->cpu_dev), cx_ptr->type,
diff --git a/sys/x86/include/x86_var.h b/sys/x86/include/x86_var.h
--- a/sys/x86/include/x86_var.h
+++ b/sys/x86/include/x86_var.h
@@ -62,6 +62,7 @@
 extern	char	cpu_model[];
 extern	u_int	cpu_vendor_id;
 extern	u_int	cpu_mon_mwait_flags;
+extern	u_int	cpu_mon_mwait_edx;
 extern	u_int	cpu_mon_min_size;
 extern	u_int	cpu_mon_max_size;
 extern	u_int	cpu_maxphyaddr;
diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c
--- a/sys/x86/x86/identcpu.c
+++ b/sys/x86/x86/identcpu.c
@@ -117,6 +117,7 @@
 uint64_t cpu_ia32_arch_caps;
 u_int	cpu_max_ext_state_size;
 u_int	cpu_mon_mwait_flags;	/* MONITOR/MWAIT flags (CPUID.05H.ECX) */
+u_int	cpu_mon_mwait_edx;	/* MONITOR/MWAIT supported on AMD (CPUID.05H.EDX) */
 u_int	cpu_mon_min_size;	/* MONITOR minimum range size, bytes */
 u_int	cpu_mon_max_size;	/* MONITOR minimum range size, bytes */
 u_int	cpu_maxphyaddr;		/* Max phys addr width in bits */
@@ -1634,6 +1635,7 @@
 	if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) {
 		do_cpuid(5, regs);
 		cpu_mon_mwait_flags = regs[2];
+		cpu_mon_mwait_edx = regs[3];
 		cpu_mon_min_size = regs[0] &  CPUID5_MON_MIN_SIZE;
 		cpu_mon_max_size = regs[1] &  CPUID5_MON_MAX_SIZE;
 	}