diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c
--- a/sys/dev/ichiic/ig4_pci.c
+++ b/sys/dev/ichiic/ig4_pci.c
@@ -168,6 +168,10 @@
 #define PCI_CHIP_ALDERLAKE_M_I2C_3	0x54eb8086
 #define PCI_CHIP_ALDERLAKE_M_I2C_4	0x54c58086
 #define PCI_CHIP_ALDERLAKE_M_I2C_5	0x54c68086
+#define PCI_CHIP_METEORLAKE_M_I2C_0     0x7e788086
+#define PCI_CHIP_METEORLAKE_M_I2C_1     0x7e798086
+#define PCI_CHIP_METEORLAKE_M_I2C_2     0x7e508086
+#define PCI_CHIP_METEORLAKE_M_I2C_3     0x7e518086
 
 struct ig4iic_pci_device {
 	uint32_t	devid;
@@ -280,6 +284,10 @@
 	{ PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE},
 	{ PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE},
 	{ PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE},
+	{ PCI_CHIP_METEORLAKE_M_I2C_0, "Intel Meteor Lake-M I2C Controller-0", IG4_TIGERLAKE},
+	{ PCI_CHIP_METEORLAKE_M_I2C_1, "Intel Meteor Lake-M I2C Controller-1", IG4_TIGERLAKE},
+	{ PCI_CHIP_METEORLAKE_M_I2C_2, "Intel Meteor Lake-M I2C Controller-2", IG4_TIGERLAKE},
+	{ PCI_CHIP_METEORLAKE_M_I2C_3, "Intel Meteor Lake-M I2C Controller-3", IG4_TIGERLAKE},
 };
 
 static int
diff --git a/sys/dev/ichsmb/ichsmb_pci.c b/sys/dev/ichsmb/ichsmb_pci.c
--- a/sys/dev/ichsmb/ichsmb_pci.c
+++ b/sys/dev/ichsmb/ichsmb_pci.c
@@ -113,6 +113,7 @@
 #define	ID_ALDERLAKE			0x7aa3
 #define	ID_ALDERLAKE2			0x51a3
 #define	ID_ALDERLAKE3			0x54a3
+#define ID_METEORLAKE                   0x7e22
 
 static const struct pci_device_table ichsmb_devices[] = {
 	{ PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA),
@@ -215,6 +216,8 @@
 	  PCI_DESCR("Intel Alder Lake SMBus controller") },
 	{ PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3),
 	  PCI_DESCR("Intel Alder Lake SMBus controller") },
+	{ PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE),
+	  PCI_DESCR("Intel Meteor Lake SMBus controller") },
 };
 
 /* Internal functions */